code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ClockDivisorTest;
reg clock;
reg rst = 1'b0;
wire dclock;
ClockDivisor #(
.TimerWidth(8),
.TimerStart(55)
) cd (
clock,
rst,
dclock
);
integer i;
initial begin
$dumpfile("test/time/ClockDivisorTest.vcd");
$dumpvars(0, cd);
i = 0;
clock = 0;
w... | 6.941748 |
module ClockDiv (
inclk0,
c0,
c1,
c2,
locked
);
input inclk0;
output c0;
output c1;
output c2;
output locked;
endmodule
| 6.569015 |
module ClockDiv_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out1,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_ClockDiv;
wire clk_in2_ClockDiv;
IBUF clkin1_ibufg (
.O(clk_in1_ClockDiv),
.I(clk_in1)
);
... | 7.961778 |
module ClockDiv (
inclk0,
c0,
c1,
c2,
locked
) /* synthesis synthesis_clearbox = 1 */;
input inclk0;
output c0;
output c1;
output c2;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 =... | 6.569015 |
module clockdiv_TB;
reg clk;
reg rst;
wire gclk;
wire dclk;
wire segclk;
wire secclk;
clockdiv clockdiv (
clk,
rst,
gclk,
segclk,
dclk,
secclk
);
initial begin
clk = 0;
rst = 1;
#1 rst = 0;
#2600 $finish;
end
always begin
#0.000_005 clk =... | 6.715722 |
module ClockDiv (
//Clock Input
input wire CLK_I,
//Clock Output
output wire CLK_O
);
// Refer to Spartan 6 clocking resource guide for more info in BUFIO2 and BUFG
wire ck;
BUFIO2 #(
.DIVIDE(2),
.DIVIDE_BYPASS(0)
) uBUFIO2 (
.I (CLK_I),
.DIVCLK (ck),... | 6.569015 |
module ClockDomain #(
parameter CYCLE = 10000 // 0.. [ps]
, parameter DUTY = 50 // 0..100 [%]
, parameter PHASE = 0 // 0..360 [°]
);
localparam N_CYCLE = CYCLE * (100 - DUTY) / 100;
localparam P_CYCLE = CYCLE * DUTY / 100;
localparam DELAY = CYCLE * PHASE / 360;
localparam STB = 1;
r... | 7.534641 |
modules for clock domain crossing.
*
* @author Yunye Pu
*/
module ClockDomainCross #(
parameter I_REG = 1,
parameter O_REG = 1
)(
input clki, input clko, input i, output o
);
wire internal;
PipeReg #(I_REG) inReg(.clk(clki), .i(i), .o(internal));
PipeReg #(O_REG) outReg(.clk(clko), .i(internal), .o(o));
endm... | 8.532958 |
module PipeReg #(
parameter DEPTH = 1
) (
input clk,
input i,
output o
);
generate
if (DEPTH < 1) assign o = i;
else if (DEPTH == 1) begin
(* SHREG_EXTRACT = "NO" *)
reg o_reg;
always @(posedge clk) o_reg <= i;
assign o = o_reg;
end else begin
(* SHREG_EXTRA... | 8.302948 |
module PipeReg_rst #(
parameter LEN = 3,
parameter INIT = 1'b0
) (
input clk,
input rst,
input i,
output o
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *)
reg [LEN-1:0] sync = {LEN{INIT}};
always @(posedge clk or posedge rst)
if (rst) sync <= {LEN{INIT}};
else sync <= {sync... | 8.632316 |
module Handshake_freqUp ( //clkAck has a higher frequency than clkStb
input clkStb,
input clkAck,
input stbI,
output reg stbO,
input ackI,
output reg ackO
);
always @(posedge clkAck)
if (ackI) stbO <= 1'b0;
else if (stbI) stbO <= 1'b1;
reg ack;
always @(posedge clkStb or posedge ... | 7.471674 |
module Handshake_freqDown ( // clkAck has a lower or equal frequency than clkStb
input clkStb,
input clkAck,
input stbI,
output reg stbO,
input ackI,
output reg ackO
);
always @(posedge clkAck or posedge stbI)
if (stbI) stbO <= 1'b1;
else if (ackI) stbO <= 1'b0;
always @(posedge cl... | 7.471674 |
module AsyncHandshake #(
parameter STB_FREQ = 100,
parameter ACK_FREQ = 100
) (
input clkStb,
input clkAck,
input stbI,
output stbO,
input ackI,
output ackO
);
generate
if (STB_FREQ < ACK_FREQ) begin : FREQ_UP
Handshake_freqUp up (
clkStb,
clkAck,
... | 7.449178 |
module EdgeDetector #(
parameter INIT = 1'b1
) (
input clk,
input rst,
input i,
output rise,
output fall
);
reg [1:0] in_reg = {2{INIT}};
always @(posedge clk)
if (rst) in_reg <= {2{INIT}};
else in_reg <= {in_reg[0], i};
assign rise = (in_reg == 2'b01);
assign fall = (in_reg ... | 6.893912 |
module clockdoubler (
CLKIN_IN,
RST_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT
);
input CLKIN_IN;
input RST_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
wire [6:0] GND_BUS_7;
wire [15:0] GND_BUS_16;
assign GND_BIT = 0;
assign GN... | 6.616186 |
module dff #(
parameter W = 1
) (
input wire [W-1:0] D,
input clk,
output reg [W-1:0] Q
);
always @(posedge clk) Q <= D;
endmodule
| 7.149811 |
module synchroniser #(
parameter W = 1
) (
input wire [W-1:0] D,
input clk,
output wire [W-1:0] Q
);
wire [W-1:0] M;
dff #(W) first_reg (
D,
clk,
M
);
dff #(W) last_reg (
M,
clk,
Q
);
endmodule
| 7.631043 |
module clocked_bus_slave #(
parameter ADRW = 1,
DATW = 1
) (
input aNE,
aNOE,
aNWE,
input wire [ADRW-1:0] aAn,
input wire[DATW-1:0] aDn,
input clk,
output wire[ADRW-1:0] r_adr,
output wire[ADRW-1:0] w_adr,
output reg do_read,
input wire[DATW-1:0] read_data,
outp... | 7.61414 |
module Clocked_Logic (
input i_Clk,
input i_Switch_1,
output o_LED_1,
output o_LED_2
);
reg r_LED_1 = 1'b0; // can give initial conditions to reg
reg r_Switch_1 = 1'b0;
wire w_Switch_1; // can not give initial conditions to wire
// instantiate Debounce Filter
Debounce_Switch Instance ... | 7.342895 |
module DFF (
D,
clk,
sync_reset,
Q
);
input D; // Data input
input clk; // clock input
input sync_reset; // synchronous reset
output reg Q; // output Q
always @(posedge clk) begin
if (sync_reset == 1'b1) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.795644 |
module: ClockExtender
module ClockExtenderTest;
// Inputs
reg clk;
// Outputs
wire ExtendedClk;
// Instantiate the Unit Under Test (UUT)
ClockExtender uut (
.clk(clk),
.ExtendedClk(ExtendedClk)
);
initial begin
// Initialize Inputs
clk = 0;
// Wait 100 ns for global reset to finish
#100;
en... | 6.731353 |
module which gates a clock
// To avoid glitches, CLK_GATE_OUT only changes when CLK_IN is low.
// CLK_GATE_OUT follows CLK_GATE_IN in the same cycle, but COND is first
// registered, thus delaying the gate condition by one cycle.
// In this model, the oscillator CLK_OUT does *not* stop when the CLK_GATE_IN or
// COND ... | 7.033269 |
module ClockGeneration (
input reset_n,
input main_clk,
output sys_clk,
output i2s_sclk,
output locked
);
/*
wire pll_clk;
BUFG BUFG_inst(
.I (main_clk),
.O (pll_clk)
);
*/
main_clk_gen instance_name (
// Status and control signals
.resetn (reset_n), // input resetn
... | 6.735566 |
module clockgen_top (
input SYSCLK_P,
input SYSCLK_N,
input GPIO_SW_C,
input GPIO_SW_E,
output [7:0] GPIO_LED,
output sma_direct_G24
);
wire sysclk;
wire btn_reset;
wire btn_prog;
reg pon_reset = 1'b1;
wire rst;
reg [4:0] pon_count = 5'h1F;
reg [7:0] O;
reg [3:0] D;
reg [6:... | 6.66301 |
module: CLOCKING
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ClockingTest;
// Inputs
reg RST;
reg CLK;
reg ADC_OTR;
reg [11:0] ADC_BIT;
reg UART_RX;
// Outputs
wire ADC... | 7.468056 |
module clocking_clk_wiz ( // Clock in ports
// Clock out ports
output CLK_50,
output CLK_25,
// Status and control signals
input reset,
output locked,
input CLK_100
);
// Input buffering
//------------------------------------
wire CLK_100_clocking;
wire clk_... | 7.580459 |
module Clocking_en_tb( );
reg clk;
wire clk_div;
reg state;
wire mode;
Clock_div Div (clk, clk_div);
clocking Divide (clk,clk_div,state,mode);
initial begin
clk = 0;
forever begin
#50 clk = ~clk;
end
end
initial begin
state = 0;
#100 state = 1;
end
endmodule
| 7.007945 |
module clocking_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
input ... | 7.34489 |
module clocking_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.... | 7.20614 |
module compression (
input [2047:0] w,
input [ 255:0] in_hash,
output [ 255:0] out_hash
);
// Space for 64 hashes (one input hash plus the 64 computed hashes)
// The 65th hash is the output hash
wire [16639:0] intermediate_hashes;
assign intermediate_hashes[255:0] = in_hash;
//Add the input h... | 6.550778 |
module with very few inputs/outputs for the logic_sha256 function
module small_test(input [31:0] message,
output [31:0] hash);
wire [511:0] m;
wire [255:0] in_hash;
wire [255:0] out_hash;
assign m = { 480'h00000000000000000000000000000000000000000000000000000000000... | 6.756715 |
module bitcoin_test (
input [255:0] in_hash,
input [31:0] hash_merkle, //Last (or first depending on endianness) word of merkle hash
input [31:0] block_time,
input [31:0] bits,
input [31:0] nonce,
output found,
output [255:0] bitcoin_hash
);
wire [511:0] sha_block;
wire [511:0] sha_blo... | 6.665043 |
modules in parallel
module bitcoin_tests_8(input [255:0] in_hash,
input [31:0] hash_merkle, //Last (or first depending on endianness) word of merkle hash
input [31:0] block_time,
input [31:0] bits,
input [31:0] nonce,
... | 6.928512 |
module ClockManager (
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1
);
ClockManager_clk_wiz inst (
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
... | 6.692734 |
module ClockManager_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_ClockManager;
wire clk_in2_C... | 8.318465 |
module ClockManager (
clk_out1,
reset,
locked,
clk_in1
);
output clk_out1;
input reset;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
ClockManager_clk_wiz_0_clk_wiz inst (
.clk_in1(clk_in1),
.clk_out1(clk_out1),
... | 6.692734 |
module handles all clock timing functions and outputs them
// The output clocks are very accurate because there is no extra interference.
//
// Dependencies: none
//////////////////////////////////////////////////////////////////////////////////
module ClockModule(
input CLK,
output CLK20Hz,
output C... | 6.922141 |
module which instantiates a simple clock muxing primitive.
// The primitive includes an internal register which maintains the selector
// state.
module ClockMux(
CLK,
SELECT,
SELECT_ENABLE,
A_CLK,
A_CLKGATE ,
B_CLK,
... | 8.6578 |
module clockrecovery (
input clk,
input reset,
input tos_in,
output tos_ce,
output tos_data
);
parameter CLK_FREQUENCY = 100000000;
parameter SAMPLE_RATE = 48000;
parameter BIT_RATE = SAMPLE_RATE * 32 * 2 * 2;
parameter CLOCKS_PER_PERIOD = CLK_FREQUENCY / BIT_RATE;
parameter SAMPLE_AT ... | 7.744733 |
module ClockRun (
input one_second_clk, //传入的是1s为周期的时钟信号
input [5:0] hour_set,
input [5:0] minute_set,
input [5:0] second_set, //这是用于设定时间的三个输入变量
input set_en, //这是用来标识是否进行时间设定的使能端
output reg [5:0] hour,
output reg [5:0] minute,
output reg [5:0] second //顾名思义，用于将时钟信号分开为三个时钟单位进行输出... | 7.465338 |
module which instantiates clock selection logic
// It is expected that custom logic will replace this module
// in general use.
// Module selects between 2 clock.
// For safety an output reset is asserted whenever a
// new clock is selected.
module ClockSelect(
CLK,
RST,
... | 8.6578 |
module will use behavioral verilog to generate a properly
// gated clock source at any frequency you desire.
// Params: ClockFreq: Desired output clock frequency
// SyncDisable: Will cause this generator to wait for a low value
// on the clock before disabling it when Enable
// transitions to low.
//... | 7.875146 |
module clockstretch (
clock,
reset,
clockOut
);
input clock;
input reset;
output clockOut;
// ------------------------------
// Define States
// ------------------------------
parameter [1:0] COUNTING = 2'b0;
parameter [1:0] INTERIM = 2'b1;
parameter [1:0] RESET = ... | 7.182983 |
module: clocks
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clocks_tb;
// Inputs
reg master;
reg rst;
// Outputs
wire t2Hz;
wire t1Hz;
wire fast;
wire adjust;
// Insta... | 8.795154 |
module clockTest ();
wire qa, qb, z;
reg clk;
clocker cl (
clk,
qa,
qb,
z
);
always begin
#1 clk = ~clk;
end
initial begin
$display("Start test");
//$display("Testing");
clk = 0;
#20000 $finish;
end
initial begin
$dumpfile("out.vcd");
$dumpvars(0... | 6.940835 |
module clocktime #(
parameter IDATA_WIDTH = 32,
parameter TIME_WIDTH = 64,
parameter ODATA_PADS = 0
) (
input wire clock,
input wire resetn,
input wire i... | 7.217262 |
module ClockFlop (
input clockIn,
input d,
output reg clockOut
);
// REPLACE ME WITH A CLOCK CELL IF DESIRED
always @(posedge clockIn)
clockOut = d; // This should be a blocking assignment to deterministically order clock edges
endmodule
| 7.000463 |
module PeriodMonitor #(
parameter longint minperiodps = 1000,
parameter longint maxperiodps = 1000 // Set to 0 to ignore
) (
input clock,
input enable
);
`ifndef VERILATOR
time edgetime = 1ps;
`else
time edgetime = 1;
`endif
longint period;
always @(posedge clock) begin
`ifndef VERILATOR
... | 7.874709 |
module Clockworks (
input wire CLK, // clock pin of the board
input wire RESET, // reset pin of the board
output wire clk, // (optionally divided) clock for the design.
// divided if SLOW is different from zero.
output wire resetn // (optionally timed) negative reset fo... | 6.883769 |
module clock_0_master_read_done_sync_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON" */;
reg data_out /* synt... | 6.920931 |
module clock_0_master_write_done_sync_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON" */;
reg data_out /* syn... | 6.920931 |
module clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else... | 6.604254 |
module clock_0_slave_read_request_sync_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON" */;
reg data_out /* sy... | 6.754368 |
module clock_0_slave_write_request_sync_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON" */;
reg data_out /* s... | 6.754368 |
module clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=... | 7.186895 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input b_clk,
input b_reset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge b_clk or posedge b_reset) begin
if (b_reset) begin
buffers_0 <= 1'b0;
... | 6.712921 |
module clock_100mhz ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//------------------------------------
// Instantiation o... | 6.584866 |
module clock_100MHz_27MHz ( // Clock in ports
input CLK_100_IN,
// Clock out ports
output CLK_27_OUT
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_100_IN)
);
// Clocking primitive
//------------------------------------
// I... | 6.706829 |
module clock_100MHz_27MHz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT
);
// Parameters for the cou... | 6.706829 |
module clock_100MHz_27MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time ... | 6.706829 |
module clock_10Hz (
output reg clk_10Hz, // 10Hz ʱź
input clk, // ϵͳʱź
input rst // λź
);
parameter PULSESCOUNT = 22'h26_25A0, RESETZERO = 22'h0;
reg [21:0] counter; //, 25 bits (1_0111_1101_0111_1000_0100_0000(bin))
// ڶϵͳʱм, Բ 10Hz ʱź
always @(posedge clk) begin
if (... | 6.870509 |
module clock_25mhz (
input clk,
input reset,
output reg pixel_clk
);
always @(posedge clk or negedge reset) begin
if (!reset) pixel_clk = 0;
else pixel_clk = ~pixel_clk; // Divide clock to 25mHz
end
endmodule
| 6.913519 |
module clock_2T (
inclk,
outclk
);
input inclk;
output reg outclk;
initial begin
outclk <= 0;
end
always @(posedge inclk) outclk <= ~outclk;
endmodule
| 6.935608 |
module Clock_3 (
input io_din,
output io_dout,
input a_clk,
input a_reset,
input b_clk
);
wire pulseCCByToggle_1_io_pulseOut;
PulseCCByToggle pulseCCByToggle_1 (
.io_pulseIn (io_din), //i
.io_pulseOut(pulseCCByToggle_1_io_pulseOut), //o
.a_clk ... | 6.716903 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input b_clk,
input a_reset_syncronized
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge b_clk or posedge a_reset_syncronized) begin
if (a_reset_syncron... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input b_clk,
input a_reset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge b_clk or posedge a_reset) begin
if (a_reset) begin
buffers_0 <= 1'b1;
... | 6.712921 |
module Clock_4 (
input io_din_valid,
output io_din_ready,
input [7:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [7:0] io_dout_payload,
input a_clk,
input a_reset,
input b_clk
);
wire streamCCByToggle_1_i... | 6.839313 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input b_clk,
input a_reset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge b_clk or posedge a_reset) begin
if (a_reset) begin
buffers_0 <= 1'b1;... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input a_clk,
input a_reset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge a_clk or posedge a_reset) begin
if (a_reset) begin
buffers_0 <= 1'b0;
... | 6.712921 |
module clock_4divider (
input clk,
output reg clk_div
);
reg counter;
initial counter = 0;
initial clk_div = 0;
always @(posedge clk) begin
if (counter) begin
counter <= 0;
clk_div <= ~clk_div;
end else counter <= 1;
end
endmodule
| 6.673327 |
module Clock_5 (
output reg io_c0,
output io_c1,
input clk,
input reset,
input sys_clk,
input sys_reset
);
reg tmp;
assign io_c1 = tmp;
always @(posedge clk or posedge reset) begin
if (reset) begin
io_c0 <= 1'b0;
end else begin
io_c0 <= (!io_c0... | 6.817828 |
module clock_50MHz_to_9600_baud (
ClkIn,
Reset,
En,
ClkOut
);
parameter MAX_CNT = 12'd2603; // 9600 baud // Set to 12'd1 for simulation purposes
// I/O
input ClkIn, Reset, En;
output reg ClkOut = 1'b0;
// Count down from 2604 for toggle (~ 2x baud rate)
reg [11:0] counter = MAX_CNT;
al... | 6.731549 |
module Clock_6 (
output reg io_c0,
output reg io_c1,
input clk,
input reset
);
always @(posedge clk or posedge reset) begin
if (reset) begin
io_c0 <= 1'b0;
io_c1 <= 1'b0;
end else begin
io_c0 <= (!io_c0);
io_c1 <= (!io_c1);
end
end
endmodule
| 6.715026 |
module Clock_7 (
output reg io_c0,
output reg io_c1,
input clk,
input reset
);
always @(posedge clk or posedge reset) begin
if (reset) begin
io_c0 <= 1'b0;
io_c1 <= 1'b0;
end else begin
io_c0 <= (!io_c0);
io_c1 <= (!io_c1);
end
end
endmodule
| 6.538015 |
module clock_adjust (
refclk,
resetn,
outclk
);
input refclk, resetn;
output reg outclk;
reg [31:0] counter;
parameter N = 2;
initial begin
counter <= 0;
outclk <= 0;
end
always @(posedge refclk or negedge resetn) begin
if (!resetn) begin
counter <= 0;
outclk <= 0;
... | 6.963138 |
module clock_beat #(
parameter CLK_FREQ = 50000000, // Unit:Hz
parameter BEAT_FREQ = 5 // Unit:Hz
) (
input wire clk,
output reg beat
);
localparam CYCLES = (CLK_FREQ / 2 / BEAT_FREQ);
reg [31:0] count = 0;
initial beat = 1'b0;
always @(posedge clk)
if (count < (CYCLES - 1))... | 7.197626 |
module clock_bootstrap_rom (
input [15:0] addr,
output [47:0] data
);
reg [47:0] rom[0:15];
//initial
// $readmemh("bootrom.mem", rom);
assign data = rom[addr];
initial begin
// First 16 bits are address, last 32 are data
// First 4 bits of address select which slave
rom[0] = 48'h0... | 7.856301 |
module clock_buffer (
input in,
output out
);
`ifdef BEHAVIORAL
assign out = in;
`else
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
$display("ERROR : %m : replace this section with user technology cell");
$finish;
`endif
endmodule
| 6.922673 |
module clock_buffer (
input A,
output Z
);
GCLKBUFF gclkbuff_0 (
.A(A),
.Z(Z)
);
//pragma attribute gclkbuff_0 ql_pack 1
//pragma attribute gclkbuff_0 hierarchy preserve
endmodule
| 6.922673 |
module clock_clk_wiz_0_0 (
// Clock out ports
output clk_dot,
output clk_color,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1
);
clock_clk_wiz_0_0_clk_wiz inst (
// Clock out ports
.clk_dot(clk_dot),
.clk_color(clk_colo... | 6.866685 |
module clock_clk_wiz_0_0 (
clk_dot,
clk_color,
reset,
locked,
clk_in1
);
output clk_dot;
output clk_color;
input reset;
output locked;
input clk_in1;
wire clk_color;
wire clk_dot;
(* IBUF_LOW_PWR *)wire clk_in1;
wire locked;
wire reset;
clock_clk_wiz_0_0_clk_wiz inst (
... | 6.866685 |
module clock_control (
input reset,
input aux_clk, // 25MHz, for before fpga clock is active
input clk_fpga, // real 100 MHz FPGA clock
output [1:0] clk_en, // controls source of reference clock
output [1:0] clk_sel, // controls source of reference clock
input ... | 6.894671 |
module clock_controller (
input wire clk,
output reg [6:0] clk_sequence,
input wire alive
);
reg [2:0] sc; // clk_sequence counter
always @(posedge (clk)) begin
if (alive) begin
case (sc)
3'd0: clk_sequence <= 7'b0000001;
3'd1: clk_sequence <= 7'b0000010;
3'd2: clk_s... | 6.894671 |
module clock_control_altclkctrl_181_bylxp4y_sub (
ena,
inclk,
outclk
) /* synthesis synthesis_clearbox=1 */;
input ena;
input [3:0] inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ena;
tri0 [3:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_... | 6.894671 |
module clock_control_altclkctrl_181_bylxp4y (
inclk,
outclk
);
input inclk;
output outclk;
wire sub_wire0;
wire outclk;
wire sub_wire1;
wire sub_wire2;
wire [3:0] sub_wire3;
wire [2:0] sub_wire4;
assign outclk = sub_wire0;
assign sub_wire1 = 1'h1;
assign sub_wire2 = inclk;
assign sub_... | 6.894671 |
module clock_control (
input wire inclk, // altclkctrl_input.inclk
output wire outclk // altclkctrl_output.outclk
);
endmodule
| 6.894671 |
module clock_control_tb ();
clock_control clock_control (
.reset(reset),
.aux_clk(aux_clk),
.clk_fpga(clk_fpga),
.clk_en(clk_en),
.clk_sel(clk_sel),
.clk_func(clk_func),
.clk_status(clk_status),
.sen (sen),
.sclk(sclk),
.sdi (sdi),
.sdo (sdo)
);
... | 6.894671 |
module Clock_Counter_Interface (
clk,
reset_n,
write,
writedata,
read,
readdata,
clk_count
);
input clk, reset_n, write, read;
input [31:0] writedata;
output [31:0] clk_count, readdata;
wire [31:0] data;
Clock_Counter CC (
.clk(clk),
.reset_n(reset_n),
.enable(... | 7.064966 |
module clock_cpu #(
parameter clk_freq = 1000000,
enable_interrupt_mux = 1,
enable_gpio = 1,
enable_timer = 1,
enable_uart = 1,
enable_pwm = 1,
enable_segments = 1,
enable_power_manager = 1
) (
input clk,
input reset_in,
//CPU monitoring
output debug,
output quit,
... | 6.784036 |
module clock_data_recovery (
input clk_x8,
input rst,
input d_in,
output reg d_out,
output reg d_out_valid,
output reg clk_out
);
parameter ds_width = 8;
parameter counter_top_default = 7; // x8 oversampling
reg [0:0] history;
reg [3:0] clk_counter;
// Combinational "regs":
reg [3... | 6.838999 |
module clock_data_recovery_tb;
// Inputs
reg clk_x8;
reg rst;
reg d_in;
// Outputs
wire d_out;
wire d_out_valid;
wire clk_out;
// Instantiate the Unit Under Test (UUT)
clock_data_recovery uut (
.clk_x8(clk_x8),
.rst(rst),
.d_in(d_in),
.d_out(d_out),
.d_out_valid(d... | 6.838999 |
module clock_DCM ( // Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
assign clkin1 = clk_in1;
// Clo... | 6.986934 |
module clock_DCM_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT,
// Status and control signals
o... | 6.735501 |
module clock_DCM_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 40... | 7.879162 |
module clock_detect (
input wire clk0,
input wire clk1,
output reg clk1_present = 0,
output reg switching = 0
);
wire thresh0;
wire [11:0] q;
reg clear = 0;
wire clear1;
clock_counter clk0_counter (
.clk(clk0),
.thresh0(thresh0),
.sclr(clear)
);
monoflop mf (
... | 6.739097 |
module posedge_detection (
signal,
clk,
posedge_signal
);
input signal;
input clk;
output posedge_signal;
reg l1, l2;
always @* l1 <= signal;
always @(posedge clk) l2 <= l1;
assign posedge_signal = (l1 && !l2);
endmodule
| 7.013204 |
module negedge_detection (
signal,
clk,
negedge_signal
);
input signal;
input clk;
output negedge_signal;
reg l1, l2;
always @* l1 <= signal;
always @(posedge clk) l2 <= l1;
assign negedge_signal = (!l1 && l2);
endmodule
| 6.623597 |
module Clock_display_tb ();
reg clk_100MHz;
reg rst_time;
reg select; //ѡʱĸı䣬һ
reg time_cnt; //Ϊ1ʱӦʱ+1
reg change; //changeΪ1ʱֶʱ
wire [3:0] L_sec;
wire [3:0] H_sec;
wire [3:0] L_min;
wire [3:0] H_min;
wire [3:0] L_hour;
wir... | 7.378094 |
module clock_div #(
parameter SIZE = 3 // Number of bits for the divider value
) (
in,
out,
N,
resetb
);
input in; // input clock
input [SIZE-1:0] N; // the number to be divided by
input resetb; // asynchronous reset (sense negative)
output out; // divided output clock
wire out_odd; ... | 7.573058 |
module odd #(
parameter SIZE = 3
) (
clk,
out,
N,
resetb,
enable
);
input clk; // slow clock
output out; // fast output clock
input [SIZE-1:0] N; // division factor
input resetb; // synchronous reset
input enable; // odd enable
reg [SIZE-1:0] counter; // these 2 counters are u... | 7.52996 |
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