code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module even #(
parameter SIZE = 3
) (
clk,
out,
N,
resetb,
not_zero,
enable
);
input clk; // fast input clock
output out; // slower divided clock
input [SIZE-1:0] N; // divide by factor 'N'
input resetb; // asynchronous reset
input not_zero; // if !not_zero divide by 1
input... | 7.144405 |
module Clock_Divide (
input Clk,
output reg Clk_Div
);
integer count = 0;
always @(posedge Clk) begin
if (count == 49999999) count <= 1'b0;
else count <= count + 1'b1;
end
always @(posedge Clk) begin
if (count == 49999999) Clk_Div <= ~Clk_Div;
else Clk_Div <= Clk_Div;
end
endmodule
| 6.57086 |
module Clock_Divider (
clock_in,
clock_out
);
input clock_in;
output reg clock_out;
reg [27:0] counter = 28'd0;
parameter DIVISOR = 28'd2;
always @(posedge clock_in) begin
counter <= counter + 28'd1;
if (counter >= (DIVISOR - 1)) counter <= 28'd0;
clock_out <= (counter < DIVISOR / 2) ? 1'... | 7.076409 |
module clock_divider (
output reg clk_1khz,
input clk_in,
input rst,
output reg [15:0] count
);
initial begin
clk_1khz = 1'b0;
count = 16'b0;
end
//while the counter arrive to the constant, it resets and flip the clk_1khz
always @(posedge clk_in) begin
count <= count + 1'b1;
if... | 6.818038 |
module clock_divider (
clk,
reset,
slow_CLK
);
// -------------------------- Inputs Declarations ---------------------------- //
input clk, reset;
// ------------------------- Outputs Declarations ---------------------------- //
output slow_CLK;
// --------------------------- Wire Declarations ---... | 6.818038 |
module notBlock (
input wire in,
output out
);
assign out = !in;
endmodule
| 9.858017 |
module andBlock (
input wire a,
input wire b,
output out
);
assign out = a & b;
endmodule
| 8.760649 |
module: clock_dividers
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clock_dividers_tb;
// Inputs
reg master;
reg rst;
// Outputs
wire t25MHz;
wire cursor_blink;
// Insta... | 6.515999 |
module clkdiv_1Hz (
clock,
clkdiv
);
input clock;
reg [31:0] count;
output reg clkdiv;
parameter C = 32'd1000;
always @(posedge clock) begin
if (count == C - 1) count <= 32'b0;
else count <= count + 1;
end
always @(posedge clock) begin
if (count == C - 1) clkdiv <= ~clkdiv;
else cl... | 7.008049 |
module clock_divider_2 #(
parameter [7:0] n = 3
) (
input clk,
input rst,
output div_clk
);
wire [7:0] n_1 = n - 1;
reg [7:0] cnt;
always @(posedge clk or posedge rst)
if (rst) cnt <= 0;
else if (cnt == n_1) cnt <= 0;
else cnt <= cnt + 1;
reg div_clk_unadjusted;
always @(po... | 6.818038 |
module clock_divider (
inclk0,
c0,
locked
);
input inclk0;
output c0;
output locked;
endmodule
| 6.818038 |
module clock_divider_by2 (
clk,
rst,
out_clk
);
output reg out_clk;
input clk;
input rst;
always @(posedge clk) begin
//if rest is 1, divider clock will set to 0
if (rst) out_clk <= 1'b0;
else
//else if reset is 0, all divider clock
out_clk <= ~out_clk;
end
endmodule
| 6.818038 |
module clock_divider_module (
output reg new_clk,
input clk
);
// The constant that defines the clock speed.
// define_speed = 50MHz/(2*desired_clock_frequency)
reg [20:0] define_speed = 20'd125000;
reg [20:0] count;
reg [20:0] count2;
always @(posedge (clk)) begin
if (count == define_speed... | 6.818038 |
module devide FPGA input clock
// by DIVIDER. Result is 50% duty cicle
// pulses.
//
//
module clock_divider #(
parameter DIVIDER =2,
parameter WIDTH =2
) (
input clk,
output clk_out);
reg state=1'b0, next_state=1'b1;
reg [WIDTH-1:0] counter = DIVIDER-1 ;
always@(posedge clk)begin
state <= next... | 7.591908 |
module clock_divider_param_tb ();
reg clk = 1'b0;
wire enable;
always #1 clk <= ~clk;
initial begin
#100;
$finish();
end
initial begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
... | 6.818038 |
module clock_divider_pulse #(
parameter N = 10
) (
input CLK,
output PULSE
);
function integer MinBitWidth;
input [1023:0] value;
begin
for (MinBitWidth = 0; value > 0; MinBitWidth = MinBitWidth + 1) begin
value = value >> 1;
end
end
endfunction
reg [MinBitWidth(N) -... | 6.818038 |
module clock_divider_pulse_tb;
reg clk;
wire clk_en;
clock_divider_pulse #(
.N(2)
) cdp (
.CLK (clk),
.PULSE(clk_en)
);
//Clock process
always #5 clk = ~clk;
initial begin
$display("MIN BIT WIDTH: %d", cdp.MinBitWidth(2));
$dumpfile("clock_divider_pulse_tb.vcd");
$dum... | 6.818038 |
module Clock_Divider_PWM_Dynamic #(
parameter DIVIDER = 10000,
parameter PWM_RESOLUTION = 8
) (
input wire clk_in,
output reg clk_out,
input wire rst,
input wire [PWM_RESOLUTION - 1 : 0] pwm_val
);
localparam PWM_STEP = DIVIDER / 2 ** PWM_RESOLUTION;
reg [$clog2(DIVIDER) - 1 : 0] cnt =... | 7.076409 |
module Clock_Divider_t;
reg clk = 1'b1;
reg rst_n = 1'b1;
reg [1:0] sel = 2'd0;
wire clk1_2;
wire clk1_4;
wire clk1_8;
wire clk1_3;
wire dclk;
// specify duration of a clock cycle.
parameter cyc = 10;
// generate clock.
always #(cyc / 2) clk = !clk;
Clock_Divider cd (
.clk(clk),
... | 7.076409 |
module: clock_divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clock_divider_tb;
// Inputs
reg clk_in;
reg rst;
// Outputs
wire clk_1khz;
wire [12:0] count;
// Inst... | 6.515999 |
module Clock_Divider_test;
reg CLK_in;
//reg [7:0] Duty;
wire Scan_clk;
wire pwm_clk;
wire Baud_clk;
Clock_Divider DUT (
.CLK_in (CLK_in),
//.Duty(Duty),
.Scan_clk(Scan_clk),
.pwm_clk (pwm_clk),
.Baud_clk(Baud_clk)
);
initial begin
CLK_in = 0;
//Duty = 0;
#... | 7.076409 |
module clock_divider_testbench (
input wire reset,
input wire input_clock,
output wire output_clock_1,
output wire output_clock_2,
output wire output_clock_3,
output wire output_clock_4
);
clock_divider #(
.clock_division(1)
) divider_by_1 (
.reset(reset),
.input_clock(i... | 6.818038 |
module clock_divider_to_125ms (
input clock_100mhz,
output reg clock_125ms = 0
);
parameter COUNTER_MAX = 6250000;
reg [25:0] counter = 0;
always @(posedge clock_100mhz) begin
if (counter < COUNTER_MAX - 1) begin
counter <= counter + 1'b1;
end else begin
counter <= 0;
clock_12... | 6.818038 |
module clock_divider_two_phase #(
parameter DIVISOR_BITS = 8
) (
input clk_in,
input rst,
input [DIVISOR_BITS-1:0] divisor,
input [DIVISOR_BITS-1:0] phase,
output reg clk_out,
output reg clk_out_phased
);
`include "auxilary_functions.v"
reg [ DIVISOR_BITS-1:0] cnt = 0;
reg [ DIVI... | 6.818038 |
module clock_divider_v1 (
input reset,
input ref_clk,
output wire clk_out
);
parameter delay = 1000;
//100MHz to 100kHz, not sure what the Virtex 5 is
reg [9:0] count = 0;
reg clk_tmp = 0;
assign clk_out = clk_tmp;
always @(posedge ref_clk) begin
if (count == (delay / 2) - 1) begin // ... | 6.818038 |
module clock_divider_w_divisor_in #(
parameter DIVISOR_BITS = 8
) (
input clk_in,
input rst,
input [DIVISOR_BITS-1:0] divisor,
output reg clk_out
);
`include "auxilary_functions.v"
reg [DIVISOR_BITS-1:0] cnt = 0;
always @(posedge clk_in) begin
if (rst) begin
cnt <= 0;
clk_ou... | 6.818038 |
module clock_divisor (
clk26,
clk
);
input clk;
output clk26;
reg [25:0] num;
wire [25:0] next_num;
always @(posedge clk) begin
num <= next_num;
end
assign next_num = num + 1'b1;
assign clk26 = num[25];
endmodule
| 6.578994 |
module clock_divisor (
clk17,
clk1,
clk
);
input clk;
output clk1;
output clk17;
reg [17:0] num;
wire [17:0] next_num;
always @(posedge clk) begin
num <= next_num;
end
assign next_num = num + 1'b1;
assign clk1 = num[1];
assign clk17 = num[17];
endmodule
| 6.578994 |
module: clock_divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clock_div_test;
// Inputs
reg clk_20;
// Outputs
wire clk;
// Instantiate the Unit Under Test (UUT)
clo... | 6.515999 |
module is just a fancy name for a shift register,
// but in the future it could use chip-specific mechanism specifically
// designed for clock domain crossing.
//
// If your silicon library supports metastable-hardened flip-flops, then the first stage
// here should use such a device. Typically, metastable-hardened flip-flo... | 8.343822 |
module clock_downscale (
input clk_i,
output reg clk_o
);
//count to 3 and toggle
reg [1:0] counter;
always @(posedge clk_i) begin
counter <= counter + 1'b1;
if (counter == 2'd2) begin
clk_o <= ~clk_o;
counter <= 2'd0;
end
end
endmodule
| 6.760337 |
module clock_driver (
i_clk,
i_mode,
i_pulse,
i_speed_up,
i_speed_down,
o_sample,
o_enable
);
parameter COUNTER_BITS = 28;
parameter DEBOUNCE_BITS = 22;
input wire i_clk;
input wire i_mode;
input wire i_pulse;
input wire i_speed_up;
input wire i_speed_down;
output wire o_sam... | 6.82592 |
module devide FPGA input clock
// by DIVIDER.
//
//
module clock_enable_param #(
parameter WAIT =1,
parameter WIDTH =1
) (
input clk,
output enable);
reg state=1'b0;
reg [WIDTH-1:0] counter = 1'b0 ;
always@(posedge clk)begin
if(counter == 0)begin
if (state == 1) begin
state <= 0... | 7.591908 |
module clock_enable_tb ();
reg clk = 1'b0;
wire enable0;
wire enable1;
wire enable2;
wire enable3;
always #1 clk <= ~clk;
initial begin
#100;
$finish();
end
initial begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Te... | 7.228695 |
module clock_en_control #(
parameter BASE_ADDRESS = 0,
parameter REGMAP_SIZE = 8'h4
) (
// Clock and reset
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr... | 7.096282 |
module CLOCK_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT
);
// Parameters for the counters
//---... | 7.169813 |
module clock_gater (
input clk,
input stop_clock,
output gated_clock
);
reg clock_prop;
always @(negedge clk) begin
clock_prop <= ~stop_clock;
end
assign gated_clock = clk & clock_prop;
endmodule
| 6.700087 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 15/8/2022 Mina Hanna final version
//---------------------------------------------... | 8.923686 |
module clock_strobe (
clk_in,
rst,
toggle_counter
);
input clk_in, rst;
output reg [7:0] toggle_counter;
reg strobe;
reg [1:0] a;
always @(posedge clk_in) begin
if (rst) begin
a <= 4'b00;
strobe <= 1'b0;
toggle_counter <= 8'b0000_0000;
end else begin
a <= a + 1'b1;
... | 6.751456 |
module clock_generators (
input clk48,
input IFCLK,
input clkgen_rst,
input clksel,
output fastclk,
output ifclk_out,
output clocks_locked
);
localparam period48 = 1000.0 / 48.0;
wire fbclk, fbclk_buf;
wire fbclk2, fbclk2_buf;
wire clk100, clk160, clkif180;
wire clk100_locked... | 6.801817 |
module clock_generator_ddr_s8_diff (
clk,
ioclkap,
ioclkan,
serdesstrobea,
ioclkbp,
ioclkbn,
serdesstrobeb,
gclk
);
parameter integer S = 8; // Parameter to set the serdes factor 1..8
parameter DIFF_TERM = "FALSE"; // Parameter to enable internal differential termination
input ... | 6.801817 |
module clock_generator_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [3:1] COUNT
);
// Parameters for the counters
//-------------------... | 6.801817 |
module clock_generator_pll_b1 (
clk_in,
rst_n,
gclk,
gclk2,
rxioclk,
reset,
rxserdesstrobe
);
input clk_in;
input rst_n;
output gclk;
output gclk2;
output rxioclk;
output reset;
output rxserdesstrobe;
// SIGNALS
wire clkfbout;
//wire gclk_unbuf;
wire ... | 6.801817 |
module clock_generator_pll_b2 (
clk_in,
rst_n,
gclk,
gclk2,
rxioclk,
reset,
rxserdesstrobe
);
input clk_in;
input rst_n;
output gclk;
output gclk2;
output rxioclk;
output reset;
output rxserdesstrobe;
// SIGNALS
wire clkfbout;
//wire gclk_unbuf;
wire ... | 6.801817 |
module clock_generator_pll_b3 (
clk_in,
rst_n,
gclk,
gclk2,
rxioclk,
reset,
rxserdesstrobe
);
input clk_in;
input rst_n;
output gclk;
output gclk2;
output rxioclk;
output reset;
output rxserdesstrobe;
// SIGNALS
wire clkfbout;
//wire gclk_unbuf;
wire ... | 6.801817 |
module clock_generator_sdr_s8_diff (
clkin_p,
clkin_n,
ioclka,
serdesstrobea,
ioclkbp,
ioclkbn,
serdesstrobeb,
gclk
);
parameter integer S = 8; // Parameter to set the serdes factor 1..8
parameter DIFF_TERM = "TRUE"; // Parameter to enable internal differential termination
inpu... | 6.801817 |
module clock_generator_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER... | 6.801817 |
module clock_gen_2 (
CLK,
CLK1,
CLK2,
O_S,
RST,
RST_C
);
/*******************************************************************************
** The inputs are defined here **
********************************************************************... | 7.450947 |
module clock_gen_tb;
reg clk, reset;
reg manual, sel, slow;
clock_generator U0 (
.clk (clk),
.manual_clk (manual),
.clk_select (sel)
);
initial begin
clk = 0;
sel = 0;
manual = 0;
end
always #5 clk = !clk;
initial begin
$dumpfile("clk_gen.vcd");
$dumpvars;
... | 7.363556 |
module top (
input wire clk,
input wire [1:0] sw,
output wire [9:0] led
);
plle2 plle2 (
.CLK(clk),
.RST(sw[0]),
.I_PWRDWN(sw[1]),
.O_LOCKED(led[8]),
.O_CNT (led[3:0])
);
mmcme2 mmcme2 (
.CLK(clk),
.RST(sw[0]),
.I_PWRDWN(sw[1]),
.O_LOCKED... | 7.233807 |
module clock_hs_phy (
/* byte clock */
input wire byte_clk,
/* bit clock: 4x byte clock */
input wire bit_clk,
/* reset signal */
input wire byte_rst,
bit_rst,
/* clock generation enable */
input wire enable,
/* controls the tri-stating of the hs lane */
input wire hi_z,
... | 7.780988 |
module Clock_Hz #(
parameter BOARD_CLOCK_FREQUENCY_IN_HZ = 100_000_000,
parameter OUTPUT_CLOCK_FREQUENCY_IN_HZ = 1
) (
input wire clk, // clock
input wire rst,
output wire clkOut
);
// localparams cannot be defined/depend on other local params. division is still ok.
// localparam OUTP... | 8.329622 |
module clock_inverter (
input rst, // just for simulation
input clk_in,
input invert,
output clk_out
);
`ifdef SUPPORTED_BUFGCTRL_INVERION
BUFGCTRL #(
.INIT_OUT (0),
.IS_CE0_INVERTED (1'b0),
.IS_CE1_INVERTED (1'b0),
.IS_I0_INVERTED (1'b1),
.IS_I... | 6.582674 |
module clock_inverter_test;
reg clk;
wire out;
clock_inverter uut (
.clk(clk),
.out(out)
);
initial begin
$dumpfile("clock_inverter.vcd");
$dumpvars(0, clock_inverter_test);
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
end
endmodule
| 6.582674 |
module clock_lane (
/* byte clock */
input wire byte_clk,
/* bit clock: 4x byte clock */
input wire bit_clk,
/* reset signal */
input wire byte_rst,
bit_rst,
/* generate clock (valid data present) */
input wire enable,
/* clock lane/data lane high-speed mode request */
inpu... | 9.10741 |
module to the main state machine
module clock_main_adp(clk,rst,en,toggle_btn);
endmodule
| 6.807287 |
module clock_generator (
output reg clk
);
initial clk <= 0;
always #5 clk <= (!clk);
endmodule
| 6.801817 |
module clock_monitor (
input clk,
rst,
ro_external,
input [7:0] FRO_MIN,
PSI_MIN,
PSI_MAX,
PSI_SET,
output [7:0] SET_PERIOD,
output reg FAIL
);
assign SET_PERIOD = (PSI_SET < PSI_MAX) ? PSI_MAX : (PSI_SET > PSI_MIN) ? PSI_MIN : PSI_SET;
reg [7:0] data_flag;
always @(posedge clk... | 6.868591 |
module clock_monitoring (
input clk50,
input clk_ex,
input [7:0] PSI_set,
input [7:0] PSI_min,
input [7:0] PSI_max,
input [7:0] FRO_min,
output reg Fail,
output reg [7:0] setPeriod
);
always @(PSI_set, PSI_min, PSI_max) begin
if (PSI_set < PSI_min) setPeriod <= PSI_min;
else i... | 6.868591 |
module Monitor_TB ();
reg clk = 1'b1, rst = 1'b1, preset = 1'b0, DN = 1'b1;
wire ring_clk, msb_co, ro_external, FAIL;
wire [7:0] adjustedDiv, setPeriod;
reg [7:0] FRO_MIN = 8'd100, PSI_MIN = 8'd160, PSI_MAX = 8'd90, PSI_SET = 8'd150;
/*freq_div_reg freq_div (.MSBQA(adjustedDiv[4]), .MSBQB(adjustedDiv[5]), .M... | 8.636454 |
module clock_mux (
input clk1, // Clock 1 supposed to be faster
input clk2, // Clock 2 supposed to be slower
input reset_n, // System reset
input sel_clk2, // Select clock2 when high
output clk1or2 // Selected clock
);
reg [1:0] meta1_off, sync1_off;
reg [1:0] meta1_on, syn... | 6.605449 |
module clock_n_creator (
refclk,
resetn,
outclk
);
input refclk, resetn;
output reg outclk;
reg [31:0] counter;
parameter N = 10;
initial begin
counter <= 0;
outclk <= 0;
end
always @(posedge refclk or negedge resetn) begin
if (!resetn) begin
counter <= 0;
outclk <=... | 6.570828 |
module clock_reg_latch #(
parameter data_size = 32
) (
input write_clk, // the APF clock
input read_clk, // the system clock
input reset_n,
input write_trigger,
input [data_size-1:0] write_data_in... | 7.962295 |
module clock_ripple (
input clk,
input reset,
output reg clk_div2,
output reg clk_div4,
output reg clk_div8,
output reg clk_div16,
output reg clk_div32,
output reg clk_div64,
output reg clk_div128,
output reg clk_div256
);
// simple ripple clock divider
always @(posedge clk... | 7.354446 |
module clock_rst_gen #(
parameter CLOCK_PERIOD = 5,
parameter RST_DELAY = 30,
parameter RST_DURATION = 2
) (
output reg clk,
output reg rstn
);
initial begin
clk = 'b0;
end
always #(CLOCK_PERIOD) clk = ~clk;
initial begin
rstn <= 'b1;
repeat (RST_DELAY) @(posedge clk);
rst... | 7.080269 |
module clock_run_2 (
clk,
rst,
seg_en,
seg_out,
onehz,
h1,
h2,
m1,
m2,
s1,
s2
);
input clk, rst;
output [7:0] seg_en;
output [7:0] seg_out;
output onehz;
wire [16:0] seconds;
wire rst;
output [3:0] h1, h2, m1, m2, s1, s2;
reg [7:0] en = 8'b1111111;
gene_... | 6.524528 |
module CLOCK_S (
// INPUTS
Clk, // posedge active
rst_n, // negedge active
start, // posedge active
alarm, // Timing configuration
// OUTPUTS
pluse // goods output
);
parameter SECONDS = 32'd32767; //32768-1
parameter IDLE = 4'b0000;
parameter TIME = 4'b0001;
input C... | 8.069734 |
module clock_sample (
clock,
din,
reset,
sample_req,
dout,
sample_valid,
sample_error,
sampling_timer_count,
stable_sample_count,
sample_idle,
edge_found,
ps_shift_count
);
// Module Parameters
//==================
parameter NUM_SAMPLES = 1000;
// Inputs and Out... | 7.265633 |
module clock_scaler (
input in,
output reg out
);
reg [14:0] current;
//(SHOULD run at 2400Hz but rounding means 2400.153609831Hz)
parameter load_value = 1302; //6.25MHz / 2400 Hz, rounded and divided by 2 as 2 pulses is one clock cycle
initial begin
current = load_value;
out = in;
end
al... | 6.926426 |
module clock_splitter (
input double_clock,
output reg a,
output reg b
);
reg counter = 1'b0;
always @(posedge double_clock) begin
if (counter == 1'b0) a <= ~a;
else if (counter == 1'b1) b <= ~b;
counter <= counter + 1'b1;
end
endmodule
| 6.805944 |
module clock_supporting_24hr (
press,
rst_before,
clk,
content_ctrl,
ssd_ctrl,
show,
am_or_not
);
input press, rst_before, clk, content_ctrl;
output [3:0] ssd_ctrl;
output [6:0] show;
output am_or_not;
/*
output [3:0] led;
output [3:0] ledc;
reg [3:0] led;
reg [3:0... | 6.805681 |
module clock_switch2_basic ( /*AUTOARG*/
// Outputs
clk_o,
// Inputs
rst0_i,
clk0_i,
rst1_i,
clk1_i,
enable,
select
);
input rst0_i;
input clk0_i;
input rst1_i;
input clk1_i;
input enable; // start&stop the clock
input select; // select which source clock
output c... | 8.135928 |
module clock_switch3_basic ( /*AUTOARG*/
// Outputs
clk_o,
// Inputs
rst0_i,
clk0_i,
rst1_i,
clk1_i,
rst2_i,
clk2_i,
enable,
select
);
input rst0_i;
input clk0_i;
input rst1_i;
input clk1_i;
input rst2_i;
input clk2_i;
input enable; // start&stop output clock... | 8.756495 |
module clock_switch4_basic ( /*AUTOARG*/
// Outputs
clk_o,
// Inputs
rst0_i,
clk0_i,
rst1_i,
clk1_i,
rst2_i,
clk2_i,
rst3_i,
clk3_i,
enable,
select
);
input rst0_i;
input clk0_i;
input rst1_i;
input clk1_i;
input rst2_i;
input clk2_i;
input rst3_i;
i... | 8.372262 |
module clock_switc_module(
input wire rst_n , //
input wire clka , //
input wire clkb , //
input wire sel_clkb , //
input wire clk_o //
);
//`define USE_GATE_CELL
`ifdef USE_GATE_CELL
`define CLK_EDGE posedge
`else
`define CLK_EDGE negedge
`endif
reg sel_c... | 6.629628 |
module clock_switc_module_tb ();
reg rst_n;
reg clka;
reg clkb;
reg sel_clkb;
wire clk_o;
clock_switc_module clock_switc_module (
.rst_n (rst_n), //
.clka (clka), //
.clkb (clkb), //
.sel_clkb(sel_clkb), //
.clk_o (clk_o) //
);
initial b... | 6.629628 |
module clock_synchronizer (
input wire clk_i,
input wire nrst_i,
input wire data_i,
output wire data_o
);
reg data_next;
reg data_edge;
always @(posedge clk_i or negedge nrst_i) begin
if (~nrst_i) begin
data_edge <= 0;
data_next <= 0;
end else begin
data_next <= data... | 6.708089 |
module clock_sync_accel #(
parameter C_FAMILY = "virtex6",
parameter integer C_DATA_WIDTH = 32,
parameter integer C_MODE = 0 // 0 = Light-weight, 1 = Fully-registered
) (
// System Signals
input wire ACLK, // Interface clock from faster clock domain
input wire ARES... | 6.579805 |
module clock_sync_decel #(
parameter C_FAMILY = "virtex6",
parameter integer C_DATA_WIDTH = 32,
parameter integer C_MODE = 0 // 0 = Light-weight, 1 = Fully-registered
) (
// System Signals
input wire ACLK, // Interface clock from faster clock domain
input wire ARES... | 6.956512 |
module cde_clock_sys #(
parameter FREQ = 48,
PLL_MULT = 2,
PLL_DIV = 4,
PLL_SIZE = 4,
CLOCK_SRC = 0,
RESET_SENSE = 0
) (
input wire a_clk_pad_in,
input wire b_clk_pad_in,
input wire pwron_pad_in,
output wire ... | 7.880461 |
module CLOCK_S_tb;
//--------------------< Port Name >------------------------------------------
parameter SECONDS = 32'd32767;
// INPUTS
reg Clk;
reg rst_n;
reg start;
reg [7:0] alarm;
// OUTPUTS
wire pluse;
// ----------------------------------------------------------... | 6.712265 |
module freq_div;
input wire out_clock;
output reg clock;
output reg reset;
freq_div_by2 freq1 (
clock,
reset,
out_clock
);
initial clock <= 1'b0;
always #10 clock <= ~clock;
initial begin
$monitor($time, "clock = %b, reset = %b, out_clock = %b", clock, reset, out_clock);
re... | 7.168792 |
module divider_50 (
input clk,
output reg clk_div50,
output reg [5:0] count_50
);
always @(posedge clk) begin
if (count_50 == 24) begin
count_50 <= 0;
clk_div50 <= ~clk_div50;
end else count_50 <= count_50 + 1;
end
endmodule
| 6.509489 |
module
// Module Name: clock_to_display_tb
// Project Name: Multifunctional Digital Clock
// Target Devices: Nexys A7 100T FPGA board
// Tool Versions: Vivado 2016.2
// Description: tests the clock to display module
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
/////////... | 6.999332 |
module clock_transmitter (
clk_fast,
clk_slow,
counter,
header,
go,
TxD,
done
);
input clk_fast;
input clk_slow;
input [31:0] counter;
input [7:0] header;
input go;
output TxD;
output done;
parameter s_idle = 0;
parameter s_transmit_tx = 1;
parameter s_transmit_wait = 2... | 7.419145 |
module lc4_we_gen (
clk,
i1re,
i2re,
dre,
gwe
);
input clk;
output i1re;
output i2re;
output dre;
output gwe;
//generate gwe, ire, and dre signals by counting the small clock
wire [1:0] clk_counter;
count #(2) global_we_count (
.clk(clk),
.out(clk_counter)
);
assi... | 6.844745 |
module clock_wizard #(
parameter OUTPUT_PER = 10,
parameter INPUT_PER = 4
) ( // Clock in ports
// Clock out ports
output clk_out1,
input clk_in1_p,
input clk_in1_n
);
// Input buffering
//------------------------------------
wire clk_in1_clock_wizard;
wire clk_in2_clock_wizard;
I... | 7.335704 |
module fulladd4 (
sum,
c_out,
a,
b,
c_in
);
// Inputs and outputs
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;
// Internal wires
wire p0, g0, p1, g1, p2, g2, p3, g3;
wire c4, c3, c2, c1;
// compute the p for each stage
assign p0 = a[0] ^ b[0], p1 = a[1] ^ b[1],... | 7.254809 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
as... | 7.603405 |
module CLOScell4 (
input clock,
input [63:0] io_in4_0,
input [63:0] io_in4_1,
input [63:0] io_in4_2,
input [63:0] io_in4_3,
output [63:0] io_out4_0,
output [63:0] io_out4_1,
output [63:0] io_out4_2,
output [63:0] io_out4_3,
input [ 7:0] io_ctrl
);
wire CrossBarSwit... | 7.132057 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitchNew.scala 15:17 CrossBarSwitchNew.scala 16:18 CrossBarSwitchNew.scala 18... | 7.603405 |
module CLOScell4New (
input [63:0] io_input_0,
input [63:0] io_input_1,
input [63:0] io_input_2,
input [63:0] io_input_3,
output [63:0] io_output_0,
output [63:0] io_output_1,
output [63:0] io_output_2,
output [63:0] io_output_3,
input [ 7:0] io_ctrl
);
wire [63:0] CrossBarSwi... | 6.528338 |
module CrossBarCell (
input [64:0] io_fw_left,
input [64:0] io_fw_top,
output [64:0] io_fw_bottom,
output [64:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
as... | 7.603405 |
module CLOScell4 (
input clock,
input reset,
input [64:0] io_in4_0,
input [64:0] io_in4_1,
input [64:0] io_in4_2,
input [64:0] io_in4_3,
output [64:0] io_out4_0,
output [64:0] io_out4_1,
output [64:0] io_out4_2,
output [64:0] io_out4_3,
input [ 7:0] io_ct... | 7.132057 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitchNew.scala 15:17 CrossBarSwitchNew.scala 16:18 CrossBarSwitchNew.scala 18... | 7.603405 |
module CLOScell4New (
input clock,
input reset,
input [63:0] io_input_0,
input [63:0] io_input_1,
input [63:0] io_input_2,
input [63:0] io_input_3,
output [63:0] io_output_0,
output [63:0] io_output_1,
output [63:0] io_output_2,
output [63:0] io_output_3,
... | 6.528338 |
module ClosePath #(
parameter size_in_mantissa = 24, //1.M
parameter size_out_mantissa = 24,
parameter size_exponent = 8,
parameter pipeline = 0,
parameter pipeline_pos = 0, // 8 bits
parameter size_counter = 5, //log2(size_in_mantissa) + 1 = 5)
parameter double_size_in_mantissa = size_in... | 7.42857 |
module closest_note // latency = 5
#( // parameters
parameter FUNDAMENTAL_WIDTH = 38 // 16Q21
) ( // ports
input clock,
reset_n,
input [FUNDAMENTAL_WIDTH*2-1:0] note_data,
input note_valid,
input [FUNDAMENTAL_WIDTH-1:0] fundamental,
output [FUNDAMENTAL_WIDTH-1:0] inv_note
);
localpara... | 7.40014 |
module CrossBarCell (
input [64:0] io_fw_left,
input [64:0] io_fw_top,
output [64:0] io_fw_bottom,
output [64:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
as... | 7.603405 |
module CLOScell4 (
input clock,
input [64:0] io_in4_0,
input [64:0] io_in4_1,
input [64:0] io_in4_2,
input [64:0] io_in4_3,
output [64:0] io_out4_0,
output [64:0] io_out4_1,
output [64:0] io_out4_2,
output [64:0] io_out4_3,
input [ 7:0] io_ctrl
);
wire CrossBarSwit... | 7.132057 |
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