code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module clos_20 #(
parameter WIDTH = 16
) (
input clk,
input [4*2*5+5*3*4+4*2*5-1:0] sels,
input [20*WIDTH-1:0] din,
output [20*WIDTH-1:0] dout
);
wire [WIDTH*20-1:0] x0, x0p, x1, x1p;
wire [4*2*5-1:0] sel0, sel2;
wire [5*3*4-1:0] sel1;
assign {sel2, sel1, sel0} = sels;
//////////////////... | 7.956758 |
module clos_20_perm #(
parameter WIDTH = 320
) (
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
localparam WORD_WIDTH = WIDTH / 20;
wire [WORD_WIDTH-1:0] w0,w1,w2,w3, w4,w5,w6,w7, w8,w9,wa,wb, wc,wd,we,wf, wg,wh,wi,wj;
assign {w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, wa, wb, wc, wd, we, wf, wg, w... | 6.872648 |
module clos_20_unperm #(
parameter WIDTH = 320
) (
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
localparam WORD_WIDTH = WIDTH / 20;
wire [WORD_WIDTH-1:0] w0,w1,w2,w3,w4, w5,w6,w7,w8,w9, wa,wb,wc,wd,we, wf,wg,wh,wi,wj;
assign {w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, wa, wb, wc, wd, we, wf, wg, ... | 6.854589 |
module cloz ( /*AUTOARG*/
//Inputs
data_in,
io,
//Outputs
data_out
);
input [31:0] data_in;
input io;
output [31:0] data_out;
/*
reg [31:0] v, c, data_out;
always @* begin
if (io == 1)
v = ~(data_in ^ (data_in - 1));
else
v = data_in ^... | 6.929117 |
module is total combinational logic.
// Examples: input data: 1111 0001 0000 0000 0000 0000 0000 0000
// one_or_zero: 1 (CLO Count Leading Ones)
// output 4 in decimal for there're 4 ones leading.
//DATE: 2020-10-02
//AUTHOR: Thimble... | 9.026705 |
module ClrOrInv (
input [11:0] IN,
input CLR,
input [11:0] DOR,
input INV,
output [11:0] OUT
);
wire nCLR = ~CLR;
wire [11:0] stage1 = IN & {12{nCLR}};
wire [11:0] stage2 = stage1 | DOR;
wire [11:0] stage3 = stage2 ^ {12{INV}};
assign OUT = stage3;
endmodule
| 7.695665 |
module clr_fg_component #(
parameter DEVICE_FAMILY = "Cyclone III"
) (
// Interface: s1_clk
input wire rsi_s1_reset,
input wire csi_s1_clk,
// Interface: Avalon-MM slave
input wire [1:0] avs_s1_address,
input wire avs_s1_write,
input wire [31:0] avs_s1_writedata,
input wire avs_s1_r... | 7.514374 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module counter_31_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 31) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
... | 7.299146 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module weight_buffer_18_9_3_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_3_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else i... | 6.854847 |
module counter_8_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 8) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
en... | 6.902674 |
module counter_63_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 63) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
... | 7.231427 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_reg... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge c... | 7.738783 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module weight_buffer_18_9_42_3_2688Wixr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wfxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Woxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wixr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wcxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module weight_buffer_18_9_42_3_2688Woxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wfxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wcxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module shift_register_group_18_16_3 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.324518 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else ... | 6.854847 |
module counter_20_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 20) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.020974 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module weight_buffer_18_16_2_64_Wfc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module weight_buffer_18_16_2_64_bf_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_2_64_bi_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_2_64_bo_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_2_64_Wic_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module counter_63_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 63) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
... | 7.360162 |
module weight_buffer_18_16_2_64_Woc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module weight_buffer_18_16_2_64_bc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else i... | 6.854847 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module counter_14_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 14) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.798894 |
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.324518 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module counter_31_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 31) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.103667 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else ... | 6.854847 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge c... | 7.738783 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_reg... | 6.854847 |
module shift_register_group_18_16_3 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module weight_buffer_18_9_42_2_2688Wcxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wcxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wixr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wfxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wixr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Woxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wfxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Woxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module counter_31_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 31) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
... | 7.08126 |
module weight_buffer_18_9_2_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_2_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module weight_buffer_18_9_42_1_2688Woxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Wixr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Woxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Wcxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module weight_buffer_18_9_42_1_2688Wfxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Wixr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module weight_buffer_18_9_42_1_2688Wfxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Wcxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
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