code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module weight_buffer_18_16_1_64_Wfc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module weight_buffer_18_16_1_64_bo_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_1_64_bc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_1_64_Woc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module weight_buffer_18_16_1_64_bi_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_1_64_bf_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_1_64_Wic_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module counter_31_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 31) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.103667 |
module weight_buffer_18_9_1_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [10:0] index
);
... | 6.6283 |
module weight_buffer_18_9_1_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [10:0] index
);
... | 6.6283 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge c... | 7.738783 |
module shift_register_group_18_16_10 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
inpu... | 6.854847 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_group_18_16_18 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
inpu... | 6.854847 |
module shift_register_group_18_16_14 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
inpu... | 6.854847 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_group_18_16_6 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.324518 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else ... | 6.854847 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_reg... | 6.854847 |
module shift_register_group_18_16_3 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module pipelined_input_18_1_16 (
input clk,
input reset,
input enable,
input load_input,
input [17:0] i_data_0_0,
input [17:0] i_data_0_1,
input [17:0] i_data_0_2,
input [17:0] i_data_0_3,
input [17:0] i_data_0_4,
input [17:0] i_data_0_5,
input [17:0] i_data_0_6,
input [1... | 7.243184 |
module counter_30_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 30) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.816296 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else i... | 6.854847 |
module CLA_4bits (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire p0, p1, p2, p3, g0, g1, g2, g3, g4;
wire c1, c2, c3, c4;
assign p0 = a[0] ^ b[0], p1 = a[1] ^ b[1], p2 = a[2] ^ b[2], p3 = a[3] ^ b[3];
assign g0 = a[0] & b[0], g1 = a[1] & ... | 6.807214 |
module: cls_spi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cls_spi_tb;
// Inputs
reg clock;
reg reset;
reg [31:0] data;
reg miso;
// Outputs
wire ss;
wire mosi;
wire ... | 7.056483 |
module documentation
*/
module clusterv_caravel_top(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User... | 8.406034 |
module documentation
*/
module clusterv_main_sram_bfm(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // Us... | 8.406034 |
module documentation
*/
module clusterv_main_sram_sky130_openram(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout v... | 8.406034 |
module documentation
*/
module clusterv_mem_ctrl_2k(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 ... | 8.406034 |
module documentation
*/
module clusterv_mem_ctrl_4k(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 ... | 8.406034 |
module documentation
*/
module clusterv_mem_ctrl_8k(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 ... | 8.406034 |
module documentation
*/
module clusterv_mgmt_if #(
parameter DEFAULT_RESET_VECTOR = 32'h10000000
) (
/*
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
... | 8.406034 |
module documentation
*/
module clusterv_tile #(
parameter HARTID=32'h8000_0000
) (
`ifdef UNDEFINED
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // Use... | 8.406034 |
module documentation
*/
module clusterv_tile_sram_bfm(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // Us... | 8.406034 |
module documentation
*/
module clusterv_tile_sram_sky130_openram(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout v... | 8.406034 |
module documentation
*/
module clusterv_tile_sram_wrapper(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, /... | 8.406034 |
module cluster_header ( /*AUTOARG*/
// Outputs
dbginit_l,
cluster_grst_l,
rclk,
so,
// Inputs
gclk,
cluster_cken,
arst_l,
grst_l,
adbginit_l,
gdbginit_l,
si,
se
);
input gclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
input gd... | 6.65365 |
module cluster_header_ctu ( /*AUTOARG*/
// Outputs
dbginit_l,
cluster_grst_l,
rclk,
so,
// Inputs
gclk,
cluster_cken,
arst_l,
grst_l,
adbginit_l,
gdbginit_l,
si,
se
);
input gclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
inpu... | 6.65365 |
module cluster_header_dup ( /*AUTOARG*/
// Outputs
dbginit_l,
cluster_grst_l,
rclk,
so,
// Inputs
gclk,
cluster_cken,
arst_l,
grst_l,
adbginit_l,
gdbginit_l,
si,
se
);
input gclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
inpu... | 6.65365 |
module cluster_header_sync ( /*AUTOARG*/
// Outputs
dram_rx_sync_local,
dram_tx_sync_local,
jbus_rx_sync_local,
jbus_tx_sync_local,
so,
// Inputs
dram_rx_sync_global,
dram_tx_sync_global,
jbus_rx_sync_global,
jbus_tx_sync_global,
cmp_gclk,
cmp_rclk,
si,
se
);... | 6.65365 |
module clz (
input [31:0] num,
output reg [31:0] result = 0
);
integer i = 31;
always @(*) begin
result = 0;
for (i = 31; !num[i] && i >= 0; i = i - 1) begin
result = result + 1;
end
end
endmodule
| 7.055978 |
module: clz32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clz32_test;
// Inputs
reg [31:0] a;
// Outputs
wire [5:0] z;
// Instantiate the Unit Under Test (UUT)
clz32 uut... | 7.1662 |
module CLZCounter (
input [31:0] rs_value,
input start,
output busy,
output reg [31:0] result
);
/*
* 先使用组合逻辑
* 之后补上状态机
*/
assign busy = 1'b0;
always @(*) begin
if (rs_value[31:0] == 32'b0) begin
result = 32'd32;
end else if (rs_value[31:0] == 32'b1) begin
result = 32'd... | 6.939886 |
module cl (
output reg out,
input wire a,
b,
input wire [1:0] s
);
always @(a, b, s) begin
case (s)
2'b00: out = a & b;
2'b01: out = a | b;
2'b10: out = a ^ b;
2'b11: out = ~a;
default: out = 1'bx;
endcase
end
endmodule
| 7.239388 |
module CL_fsm (
input clk,
input pause_SW, //debounced pause switch
input data_loaded,
input song_loaded,
input reset_trigger, //debounced reset button
output reg pause, //pause game state
output reg reset //reset game signal
);
always @(posedge clk) begin
pause <= pause_SW || !(d... | 7.812184 |
module cl_serial_out (
clk_fix,
rst_fix_n,
measured_baud,
lvds_swap,
fifo_empty,
fifo_ren,
fifo_dout,
cl_sertfg_p,
cl_sertfg_n
);
// clock & reset
input clk_fix;
input rst_fix_n;
input [15:0] measured_baud;
input lvds_swap;
// fifo info
input fifo_empty;
input [7:0... | 7.767743 |
module CL_song_timer (
input clk, //100mhz clock
input pause, //high if game is paused
input reset, //high to clear song_time
output reg [15:0] song_time //10ms clock with pause
);
reg [19:0] counter; //counts to 1_000_000
initial counter = 0;
initial song_time = 0;
always @(posedge clk)... | 6.799108 |
module cl_tb;
//declaracion de se�ales
reg [1:0] test_s;
reg test_a, test_b, test_c, test_d;
wire test_out;
//instancia del modulo a testear, con notaci�n de posiciones de argumentos y con notaci�n de nombres
cl celda_logica (
test_out,
test_a,
test_b,
test_s
);
initial begin
... | 6.790412 |
module cm0_dbg_reset_sync #(
parameter PRESENT = 1
) (
input wire RSTIN,
input wire CLK,
input wire SE,
input wire RSTBYPASS,
output wire RSTOUT
);
// This module is instantiated where a reset synchroniser is required.
// The purpose of this module is to produce a reset which is asynchr... | 7.515556 |
module CM138 (
pi0,
pi1,
pi2,
pi3,
pi4,
pi5,
po0,
po1,
po2,
po3,
po4,
po5,
po6,
po7
);
input pi0, pi1, pi2, pi3, pi4, pi5;
output po0, po1, po2, po3, po4, po5, po6, po7;
wire new_n23_;
assign po0 = pi2 | new_n23_ | pi0 | pi1;
assign po1 = pi2 | new_n23_ ... | 6.984691 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/CM138_comb/CM138_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad
);
input a_pad, b_pad, c_pad, d_pad, e_pad... | 6.939825 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/CM150_comb/CM150_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad,
o_pad,
p_pad,
q_pad,
r_pad,... | 6.939825 |
module CM151 (
pi00,
pi01,
pi02,
pi03,
pi04,
pi05,
pi06,
pi07,
pi08,
pi09,
pi10,
pi11,
po0,
po1
);
input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11;
output po0, po1;
wire new_n17_, new_n18_, new_n19_, new_n20_, new_n21_, new_n22_,... | 6.555275 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/CM151_comb/CM151_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad
);
input a_pad, b_pad, c_pad, d_pad, e_pad... | 6.939825 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/CM162_comb/CM162_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad,
o_pad,
p_pad,
q_pad,
r_pad,... | 6.939825 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/CM163_comb/CM163_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad,
o_pad,
p_pad,
q_pad,
r_pad,... | 6.939825 |
module CM1_JTAG (
input HCLK, // AHBʱ
input rst_x, // 弶ȫ첽λź
// JTAG inputs
input nTRST, // JTAG reset
input TCK, // JTAG clock
input TDI, // JTAG data in
inout TMS, // JTAG mode select
// JTAG outputs
... | 7.0911 |
module icarus_toplevel (
input input_clk,
input reset,
// UART interface (to host)
input uart_rx,
output uart_tx,
// Secondary UART (slave)
input aux_uart_rx,
output aux_uart_tx,
// Switch config
input [2:0] switch_config,
// Some leds to ease debugging/supervision?
... | 8.465558 |
module output_arb_t (
hclk,
hreset_n,
req_port0_i,
req_port1_i,
hreadym_i,
hselm_i,
htransm_i,
hburstm_i,
hmastlockm_i,
addr_in_port_o,
no_port_o
);
input hclk; // AHB system clock
input hreset_n; // AHB system reset
input req_port0_i; // Port 0 request signal
i... | 8.000296 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/CM42_comb/CM42_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad
);
input a_pad, b_pad, c_pad, d_pad;
outpu... | 6.939825 |
module cm4ik_sram #(
parameter MEMNAME = "", // Memory Name
parameter MEMFILE = "image.bin", // Image Filename
parameter DATAWIDTH = 32, // Data Width
parameter ADDRWIDTH = 18, // Address Width
parameter MEMBASE = 32'h00000000,
parameter MEMTOP = 3... | 8.449876 |
module CM82 (
pi0,
pi1,
pi2,
pi3,
pi4,
po0,
po1,
po2
);
input pi0, pi1, pi2, pi3, pi4;
output po0, po1, po2;
wire new_n12_, new_n13_, new_n14_;
assign po0 = pi0 ^ new_n14_;
assign po1 = ~new_n12_ ^ new_n13_;
assign po2 = (~new_n12_ & (pi3 | pi4)) | (pi3 & pi4);
assign new_n... | 7.008431 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/CM82_comb/CM82_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad
);
input a_pad, b_pad, c_pad, d_pad, e_pad;
output f_pad, g_pad, h_pad;
wire new_n12_;
assign f_pad = a_... | 6.939825 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/CM85_comb/CM85_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad
);
input a_pad, b_pad, c_pad, d_pad, e_pad, ... | 6.939825 |
module cmac (
input wire clk,
input wire rst,
input wire [15:0] data,
input wire [15:0] weight,
output reg [15:0] result,
input wire data_ready,
output reg data_valid,
output reg conv_ready
);
reg [15:0] a_mult, b_mult;
wire operatio... | 7.489356 |
module cmacc # (parameter AWIDTH = 16, BWIDTH = 18, SIZEOUT = 40)
module cmacc # (parameter AWIDTH = 4, BWIDTH = 5, SIZEOUT = 9)
(
input clk,
input sload,
input signed [AWIDTH-1:0] ar,
input signed [AWIDTH-1:0] ai,
input signed [BWIDTH-1:0] br,
input signed [BWIDTH-1:0] bi,
output signed [SIZEOU... | 7.13861 |
module
*/
module cmac_pad #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 512,
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire ... | 7.587875 |
module cmac_padding ();
//----------------------------------------------------------------
// pad_block()
//
// pad a given block in with the given amount of data by
// zeroisingt non-data bits and then adding a one to the first
// bit after data.
//-------------------------------------------------------... | 6.670584 |
module cmac_tb;
reg clk;
reg rst;
reg rst_acc;
reg [15:0] tmp_sum;
reg [15:0] data;
reg [15:0] weight;
wire [15:0] result;
reg conv_valid;
wire conv_ready;
reg data_ready;
wire data_valid;
reg [15:0] tmp_sum_fifo[0:9];
reg [15:0] data_fifo[0:9];
reg [15:0] weight_fifo[0:9];
initial begi... | 6.628216 |
module CmbALU (
op,
data_x,
data_y,
shamt,
data_res
);
input [`ALU_OP_BIT - 1:0] op;
input [31:0] data_x;
input [31:0] data_y;
input [4:0] shamt; // Separate input for shift
output reg [31:0] data_res;
always @(*) begin
case (op)
`ALU_OP_AND: data_res <= (data_x & data_y);
... | 8.087949 |
module CmbDecoder (
inst,
opcode,
rs,
rt,
rd,
shamt,
funct,
imm16,
imm26
);
input [31:0] inst;
output [5:0] opcode;
output [4:0] rs;
output [4:0] rt;
output [4:0] rd;
output [4:0] shamt;
output [5:0] funct;
output [15:0] imm16;
output [25:0] imm26;
assign opcode[... | 6.824185 |
module CmbExt (
imm16,
out_sign,
out_zero
);
input [15:0] imm16;
output [31:0] out_sign;
output [31:0] out_zero;
assign out_zero = {16'h0, imm16};
assign out_sign = {{16{imm16[15]}}, imm16};
endmodule
| 7.169288 |
module CmbForward (
mux_fwd_rf_a,
mux_fwd_rf_b,
ex_rf_data_a,
ex_rf_data_b,
ma_val_rf_w_tmp,
wb_val_rf_data_w,
mux_fwd_rc0_ie,
mux_fwd_rc0_epc,
ex_rc0_ie,
ex_rc0_epc,
ma_val_rc0_ie_w,
ma_val_rc0_epc_w,
wb_val_rc0_ie_w,
wb_val_rc0_epc_w,
ex_fwd_rf_a,
ex_fwd... | 6.578893 |
module CmbWTG (
input [`WTG_OP_BIT - 1:0] op,
input [31:0] off32,
input [25:0] imm26,
input signed [31:0] data_x,
input signed [31:0] data_y,
input [31:0] pc_4,
output reg [31:0] pc_new,
output reg branched,
output reg jumped,
output reg is_branch
);
// True on successful cond... | 6.864473 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/cmb_comb/cmb_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad,
o_pad,
p_pad,
q_pad,
r_pad,
... | 6.939825 |
module DFF (
in_a,
clk,
rst,
out_a
);
input in_a, clk, rst;
output reg out_a;
always @(posedge clk or negedge rst)
if (!rst) out_a = 0;
else out_a = in_a;
endmodule
| 8.336388 |
module cmd
(
input clk,
input reset,
input[7:0] cmd_axis_tdata_in,
input cmd_axis_tvalid_in,
input cmd_axis_tlast_in
// Commands sent to RapidIO
output cmd2rapidio_self_check,
output [7:0] cmd2rapidio_tdata_out,
output ... | 7.208593 |
module cmd4 (
input [31:0] data1,
input [31:0] data2,
input start,
input clk,
input mult_E,
input div_E,
output reg busy,
output [31:0] lo,
output [31:0] hi,
output reg [63:0] daboss,
output reg [31:0] dabss,
output reg [63:0] dabs
);
reg [31:0] loo;
reg [31:0] hii;
... | 6.618464 |
module cmdackfsm (
input reset,
input clk,
input cmd,
input cmd_ack,
output reg cmd_buffer = 1'b0
);
parameter IDLE_ST = 2'b00;
parameter VALID_ST = 2'b01;
parameter WAIT_ST = 2'b10;
reg [1:0] st = IDLE_ST;
always @(posedge clk)
if (reset) begin
cmd_buffer <= 1'b0;
st <=... | 7.273856 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module cmdparser_tb ();
reg nreset = 1;
reg clk = 0;
initial begin
$dumpfile("cmdparser_tb.vcd");
$dumpvars(clk);
end
always begin
#2 clk <= !clk;
end
register #(
.ADDRESS(8'hab),
.INITVAL(8'h10),
.MASK(8'h0f)
) register (
.nreset(nreset),
.clk(clk),
... | 6.760501 |
module cmdrecv #(
parameter MAGIC_CODE = 32'hC0C0C0CC
, parameter NPORT = 4'h4
, parameter PORT_NUM = 4'h3
) (
input sys_rst
, input sys_clk
// recieve flow data from RX-FIFO
, input [ 8:0] rx_dout
, input rx_empty
, output reg ... | 7.023234 |
module cmd_wb #(
parameter CORE_TYPE = CORE_TYPE_A2L2
) ();
endmodule
| 7.660038 |
module is the sub level RTL code of SDRAM Controller ASIC verilog
code. It will generate the command acknowledge signal.
Hossein Amidi
(C) April 2002
*********************************************************/
// DEFINES
`timescale 1ns / 10ps
module cmd_ack(// Input
reset,
clk0,
cmack,
load_t... | 6.572195 |
module cmd_analy (
input clk,
input rst_n,
input din_vld,
input [7:0] din,
output reg [1:0] cmd_out
);
//参数定义
parameter FRAME_HEAD = 3'b001;
parameter FRAME_DATE = 3'b010;
parameter FRAME_TAIL = 3'b100;
localparam HEAD = 8'h55;
localparam LED_O... | 10.746801 |
module bk_ay_orig (
strobe,
iwrbt,
bc1,
bc2,
bdir
);
input strobe, iwrbt;
output bc1, bc2, bdir;
parameter li1_delay = 20; // задержка 555ЛИ1, нс
assign bc2 = 1;
assign bdir = strobe;
assign #(li1_delay) bc1 = (iwrbt & strobe);
endmodule
| 6.533573 |
module cmd_ay_orig (
strobe,
iwrbt,
dout,
ay_inact,
ay_laddr,
ay_wrpsg,
ay_rdpsg
);
input strobe, iwrbt, dout;
output ay_inact, ay_laddr, ay_wrpsg, ay_rdpsg;
wire bc1, bc2, bdir;
bk_ay_orig bk_AY (
.strobe(strobe),
.iwrbt(iwrbt),
.bc1(bc1),
.bc2(bc2),
... | 6.719907 |
module bk_ay_stas1 (
strobe,
iwrbt,
bc1,
bc2,
bdir
);
input strobe, iwrbt;
output bc1, bc2, bdir;
parameter ln1_delay = 20; // задержка 555ЛН1
parameter ds_on = 10; // время отпирания диода
parameter ds_off = 10; // время запирания диода
wire bdir = 1;
wire bc2 = strobe;
// пе... | 6.72137 |
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