code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cmd_ay_stas1 (
strobe,
iwrbt,
dout,
ay_inact,
ay_laddr,
ay_wrpsg,
ay_rdpsg
);
input strobe, iwrbt, dout;
output ay_inact, ay_laddr, ay_wrpsg, ay_rdpsg;
wire bc1, bc2, bdir;
bk_ay_stas1 bk_AY (
.strobe(strobe),
.iwrbt(iwrbt),
.bc1(bc1),
.bc2(bc2),
... | 6.505328 |
module cmd_ay_stas2 (
strobe,
iwrbt,
dout,
ay_inact,
ay_laddr,
ay_wrpsg,
ay_rdpsg
);
input strobe, iwrbt, dout;
output ay_inact, ay_laddr, ay_wrpsg, ay_rdpsg;
wire bc1, bc2, bdir;
bk_ay_stas2 bk_AY (
.strobe(strobe),
.iwrbt(iwrbt),
.dout(dout),
.bc1(bc1),
... | 6.879603 |
module bk_ay_stas3 (
strobe,
iwrbt,
bc1,
bc2,
bdir
);
input strobe, iwrbt;
output bc1, bc2, bdir;
parameter ln1_delay = 15; // задержка 555ЛН1
parameter le1_delay = 15; // задержка 555ЛЕ1
assign bdir = 1;
assign #(ln1_delay) bc1 = ~strobe;
assign #(le1_delay) bc2 = ~(iwrbt | bc1);... | 6.524288 |
module cmd_ay_stas3 (
strobe,
iwrbt,
ay_inact,
ay_laddr,
ay_wrpsg,
ay_rdpsg
);
input strobe, iwrbt;
output ay_inact, ay_laddr, ay_wrpsg, ay_rdpsg;
wire bc1, bc2, bdir;
bk_ay_stas3 bk_AY (
.strobe(strobe),
.iwrbt(iwrbt),
.bc1(bc1),
.bc2(bc2),
.bdir(bdir)
... | 6.639778 |
module cmd_buf (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q
);
input aclr;
input clock;
input [3:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [3:0] q;
wire sub_wire0;
wire sub_wire1;
wire [3:0] sub_wire2;
wire empty = sub_wire0;
wi... | 7.01488 |
module cmd_buf (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q
);
input aclr;
input clock;
input [3:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [3:0] q;
endmodule
| 7.01488 |
module cmd_deser_single #(
parameter ADDR=0,
parameter ADDR_MASK='hffff,
parameter ADDR_WIDTH=8, // <=8
parameter DATA_WIDTH=1, // will 0 work?
parameter ADDR1=0,
parameter ADDR_MASK1=0,
parameter ADDR2=0,
parameter ADDR_MASK2=0,
parameter WE_WIDTH=1,
parameter WE_EARLY = 0 /... | 8.271034 |
module cmd_deser_dual #(
parameter ADDR=0,
parameter ADDR_MASK='hffff,
parameter ADDR_WIDTH=12, // <=16
parameter DATA_WIDTH=1, // will 0 work?
parameter ADDR1=0,
parameter ADDR_MASK1=0,
parameter ADDR2=0,
parameter ADDR_MASK2=0,
parameter WE_WIDTH=1,
parameter WE_EARLY = 0 ... | 8.367143 |
module cmd_deser_multi #(
parameter ADDR=0,
parameter ADDR_MASK='hffff,
parameter NUM_CYCLES=6, // >=3
parameter ADDR_WIDTH=16,
parameter DATA_WIDTH=32,
parameter ADDR1=0,
parameter ADDR_MASK1=0,
parameter ADDR2=0,
parameter ADDR_MASK2=0,
parameter WE_WIDTH=1,
parameter WE_EA... | 7.457589 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module cmd_fifo #(
parameter TYPE_WIDTH = 2,
parameter ADDR_WIDTH = 27,
parameter BRST_WIDTH = 6,
parameter DATA_WIDTH = 128,
parameter MASK_WIDTH = 16
) (
input rstn,
input push_clk,
input io_push_valid,
output io_push_ready,
... | 7.806128 |
module is the sub level RTL code of SDRAM Controller ASIC verilog
code. It will store the timing and refresh commands into internal registers.
Hossein Amidi
(C) April 2002
*********************************************************/
// DEFINES
`timescale 1ns / 10ps
module internal_reg(// Input
reset,
... | 6.572195 |
module cmd_pro (
clk,
res,
din_pro,
en_din_pro,
dout_pro,
en_dout_pro,
rdy
);
input clk;
input res;
input [7:0] din_pro; //指令和数据输入端口
input en_din_pro; //输入使能
output [7:0] dout_pro; //指令执行结果
output en_dout_pro; //指令输出使能
output rdy; //串口发送空闲
parameter addx = 8'h0a;
para... | 7.101772 |
module cmd_queue #(
parameter TS_BITS = 30,
parameter CMD_QUEUE_BITS = 5
) (
// CMD clock
input newcmd_clk,
input newcmd_reset,
// CMD control
output newcmd_ready,
input newcmd_valid,
input [TS_BITS - 1:0] newcmd_data,
// CMD statistics
... | 7.316169 |
module cmd_tb ();
//激励信号定义
reg clk;
reg rst_n;
reg [7:0] din; //串口接收模块接口
reg din_vld;
//输出信号定义
wire [7:0] dout; //写入FIFO的数据
wire dout_vld;
wire wr_en; //写请求
wire rd_en; //读请求
wire [8:0] addr; //读写地址
//时钟周期参数定义
parameter CLOCK_CYCLE... | 6.702655 |
module cmd_wb #(
parameter CORE_TYPE = `CORE_TYPE_WB2,
parameter BUS_TYPE = `BUS_TYPE_WB2
) (
input clk,
input rst,
input i_wb_cyc,
input i_wb_stb,
input [31:2] i_wb_adr,
input d_wb_cyc,
input d_wb_stb,
input d_wb_we,
input [3:0] d_wb_sel,
input [31:0] d_wb_adr,
inpu... | 7.660038 |
module ctlb_ram (
clk,
rst,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = `ctlb_width;
localparam ADDR_WIDTH = 6;
localparam ADDR_COUNT = 64;
input clk;
input rst;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
inpu... | 8.520327 |
module ctlb_way (
clk,
rst,
read_clkEn,
fStall,
addr,
tr_jump,
sproc,
read_data,
read_lru,
read_hit,
write_data,
write_wen,
write_tr,
invalidate,
init,
newLRU
);
parameter WAYNO = 0;
localparam DATA_WIDTH = `ctlb_width;
localparam OUTDATA_WIDTH = `c... | 6.521321 |
module cmm5t #(
parameter [ 0:0] A = 1.0,
parameter [ 0:0] P = 1.0
) (
input real top,
input real bottom,
input real subs
);
wire real top, bottom, subs;
/* Not modeled, for LVS purposes only */
endmodule
| 7.49708 |
module figures out what to do for scheduling Cpl transactions:
1) count up or count down,
2) how much to add or to subtract,
3) it counts the Cpl requested by TLM and USER separately.
It returns the number and a add/subtract_b signals to the Cpl
tracking counter. The outputs are based on how many non-p... | 7.738256 |
module figures out what to do for non-fatal errors:
1) count up or count down,
2) how much to add or to subtract.
It returns the number and a add/subtract_b signals to the error
tracking counter. The outputs are based on how many errors are
asserted by the error reporting modules.
*********************... | 7.738256 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cmodule(
input [31:0] data1,
input [31:0] ... | 7.088073 |
module cmod_a7 (
input CLK, // Тактовый сигнал 12 MHz
output [1:0] LED, // Два светодиода
output RGB0_Red, // Красная часть трехцветного светодиода
output RGB0_Green, // Зеленая часть трехцветного светодиода
output RGB0_Blue, // Синяя часть трехцветного светодиода
input [1:0] BTN, //... | 7.304554 |
module spi_transmitter (
input clock,
input reset,
input [7:0] data,
input transmit,
output reg ready,
output reg sclk,
output reg sdi,
output reg cs
);
localparam IDLE = 0, DRIVE_POSEDGE_CLOCK = 1, DRIVE_DATA = 2;
reg d_ready;
reg d_sclk;
reg d_sdi;
... | 7.405138 |
module cmos2gram2vga_tb ();
wire sdram_clk,
sdram_cke,
sdram_cs_n,
sdram_ras_n,
sdram_cas_n,
sdram_we_n,
sdram_dqmh,
sdram_dqml;
wire [12:0] sdram_addr;
wire [ 1:0] sdram_bkaddr;
wire [15:0] sdram_data;
reg _clk_, _rst_n_, wr_en, wr_clk;
reg [15:0]... | 6.566631 |
module: cmosand
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cmosandtest;
// Inputs
reg a;
reg b;
// Outputs
wire f53;
// Instantiate the Unit Under Test (UUT)
cmosand u... | 6.670021 |
module cmoscmos_test;
reg source, n_gate, p_gate;
wire drain1, drain2;
cmos c1 (drain1, source, n_gate, p_gate);
cmoscmos c2 (
drain2,
source,
n_gate,
p_gate
);
initial begin
source = 0;
n_gate = 0;
p_gate = 0;
#1 source = 0;
n_gate = 0;
p_gate = 0;
#1 so... | 6.633134 |
module cmosnand (
out,
ina,
inb
);
input ina, inb;
output out;
wire w_n; // connect the 2 cmos transistors
supply1 vdd;
supply0 gnd;
// pmos name(drain, source, gate);
pmos p1 (out, vdd, inb);
pmos p2 (out, vdd, ina);
// nmos name(drain, source, gate);
nmos n2 (w_n, gnd, inb);
nmos... | 6.92586 |
module cmosnor (
out,
ina,
inb
);
input ina, inb;
output out;
wire w_p;
supply1 vdd;
supply0 gnd;
// pmos name (drain, source, gate);
pmos p1 (w_p, vdd, ina);
pmos p2 (out, w_p, inb);
// nmos name (drain, source, gate);
nmos n1 (out, gnd, ina);
nmos n2 (out, gnd, inb);
endmodule
| 6.823061 |
module: cmosoai
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cmosoaitest;
// Inputs
reg a;
reg b;
reg c;
reg d;
// Outputs
wire f53;
// Instantiate the Unit Under Test ... | 6.636895 |
module cmosor (
input a,
input b,
output f53
);
supply1 vdd;
supply0 gnd;
//OR
wire w1;
pmos (f53, vdd, ~a);
pmos (f53, vdd, ~b);
nmos (f53, w1, ~a);
nmos (w1, gnd, ~b);
endmodule
| 6.725953 |
module: cmosor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cmosortest;
// Inputs
reg a;
reg b;
// Outputs
wire f53;
// Instantiate the Unit Under Test (UUT)
cmosor uut ... | 6.516147 |
module cmosxnor (
input a,
input b,
output f53
);
supply1 vdd;
supply0 gnd;
wire w1, w2, w3;
pmos (w1, vdd, a);
pmos (w1, vdd, ~b);
pmos (f53, w1, b);
pmos (f53, w1, ~a);
nmos (f53, w2, a);
nmos (f53, w3, b);
nmos (w2, gnd, ~b);
nmos (w3, gnd, ~a);
endmodule
| 6.680061 |
module cmos_8_16bit (
input rst,
input pclk,
input [ 7:0] pdata_i,
input de_i,
output reg [15:0] pdata_o,
output reg hblank,
output reg de_o
);
reg [ 7:0] pdata_i_d0;
reg [11:0] x_cnt;
always @(posedge pclk) begin
pdata_i_d0 <=... | 6.778856 |
module cmos_capture_data (
input rst_n, //复位信号
//摄像头接口
input cam_pclk, //cmos 数据像素时钟
input cam_vsync, //cmos 场同步信号
input cam_href, //cmos 行同步信号
input [ 7:0] cam_data, //cmos 数据
//用户接口... | 7.843901 |
module cmos_capture_raw_gray #(
parameter CMOS_FRAME_WAITCNT = 4'd10 //等待数据稳定所需要的帧数
) (
//global clock
input clk_cmos, //锁相环分频时钟
input rst_n, //复位信号，低有效
//CMOS Sensor Interface
input cmos_pclk, //摄像头输入时钟
output cmos_xclk, //摄像头驱动时钟
input cmos_vsync, //摄像头... | 7.843901 |
modules of the same cmos_cells.lib
//
// Adding relative relative delay times to AND, OR,
// NOT gates since NOR and NAND are expected to be faster
// NOT gate #2.4 ns
// AND gate #4.3 ns
// OR gate #4.6 ns
// FF gate #6 ns
// The following approach is related:
// NOR = abs(#NOT - #OR) = abs(2.4 - 4.6) = 2.2
// NAND... | 7.083423 |
module NOT (
A,
Y
);
input A;
output Y;
assign #2.4 Y = ~A;
endmodule
| 7.213424 |
module NAND (
A,
B,
Y
);
input A, B;
output Y;
assign #1.9 Y = ~(A & B);
endmodule
| 8.177563 |
module NOR (
A,
B,
Y
);
input A, B;
output Y;
assign #2.2 Y = ~(A | B);
endmodule
| 8.177256 |
module DFF (
C,
D,
Q
);
input C, D;
output reg Q;
always @(posedge C) Q <= #6 D;
endmodule
| 7.813248 |
module DFFSR (
C,
D,
Q,
S,
R
);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S) Q <= #6 1'b1;
else if (R) Q <= #6 1'b0;
else Q <= D;
endmodule
| 6.733438 |
module BUF (
A,
Y
);
input A;
output Y;
assign Y = A;
endmodule
| 7.249964 |
module NOT (
A,
Y
);
input A;
output Y;
assign Y = ~A;
endmodule
| 7.213424 |
module NAND (
A,
B,
Y
);
input A, B;
output Y;
assign Y = ~(A & B);
endmodule
| 8.177563 |
module NOR (
A,
B,
Y
);
input A, B;
output Y;
assign Y = ~(A | B);
endmodule
| 8.177256 |
module DFF (
C,
D,
Q
);
parameter PwrC = 0;
input C, D;
output reg Q;
always @(posedge C) begin
Q <= D;
end
always @(posedge Q) begin
tb_tx.m1.PwrCntr[PwrC] = tb_tx.m1.PwrCntr[PwrC] + 1;
end
endmodule
| 7.813248 |
module DFFSR (
C,
D,
Q,
S,
R
);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S) Q <= 1'b1;
else if (R) Q <= 1'b0;
else Q <= D;
endmodule
| 6.733438 |
module cmos_decode (
//system signal.
input cmos_clk_i, //cmos senseor clock.
input rst_n_i, //system reset.active low.
//cmos sensor hardware interface.
input cmos_pclk_i, //input pixel clock.
input cmos_href_i, //input pixel hs signal.
input cmos_vsync_i, //input pixel vs signal.
... | 7.278948 |
module cmos_decode (
//system signal.
input cmos_clk_i, //cmos senseor clock.
input rst_n_i, //system reset.active low.
//cmos sensor hardware interface.
input cmos_pclk_i, //input pixel clock.
input cmos_href_i, //input pixel hs signal.
input cmos_vsync_i, //input pixel vs signal.
... | 7.278948 |
module CMOS_DRIVE_LFL1402 (
input clk,
input rst_n,
output clk_lfl1402,
output clk_st_lfl1402,
output DIS_lfl1402,
output [7:0]pixel_cnt
);
localparam CLKLFL1402_PARA = 50; //50Ƶ
localparam CLKLFL1402_PARA_2 = 25;
/*
localparam CLKLFL1402_PARA = 1000; //1000Ƶ
localparam CLKL... | 7.467687 |
module CMOS_get_data (
input clk,
input rst_n,
input vs_in,
input href_in,
input pclk_in,
input [7:0] data_in /*synthesis noprune*/,
input system_init_done,
input xclk_in,
output reg led2,
output led3_pclk_cnt,
output fifo_write_clk,
output reg fifo_write_en,
outp... | 7.537188 |
module cmos_top (
input clk,
input rst_n,
output scl,
inout sda,
output pwdn,
output reset,
output cfg_done
);
//信号定义
wire req;
wire [3:0] cmd;
wire done;
wire [7:0] dout;
wire i2c_scl;
wire i2c_sda_i;
wire i2c_sda_o;
wire i2c_sda_oe... | 8.121043 |
module cmos_write_req_gen (
input rst,
input pclk,
input cmos_vsync,
output reg write_req,
output reg [1:0] write_addr_index,
output reg [1:0] read_addr_index,
input write_req_ack
);
reg cmos_vsync_d0;
reg cmos_vsync_d1;
always @(posedg... | 6.59359 |
module cmov (
clk,
rst,
verify_true,
rd_base_sel,
read_address,
read_data,
write_address,
write_data,
write_en,
done
);
input clk, rst;
input verify_true;
output rd_base_sel;
output [8:0] read_address;
input [63:0] read_data;
output [8:0] write_address;
output [63... | 7.420354 |
module CMOVC32 (
a,
b,
CF,
out
);
input [31:0] a;
input [31:0] b;
input CF;
output [31:0] out;
mux #(
.INPUTS(2),
.WIDTH (32)
) cmovc_mux (
.in({b, a}),
.out(out),
.select(CF)
);
endmodule
| 7.738139 |
module CMOVC16 (
a,
b,
CF,
out
);
input [15:0] a;
input [15:0] b;
input CF;
output [15:0] out;
mux #(
.INPUTS(2),
.WIDTH (16)
) cmovc_mux (
.in({b, a}),
.out(out),
.select(CF)
);
endmodule
| 7.030873 |
module cmp8 (
input wire [7:0] A,
B,
output wire Go,
Eo,
Lo
);
//*********<例化>*************
cmp cmp1 (
0,
0,
0,
A[i],
B[i],
Gi[1],
Ei[1],
Li[1]
);
generate
genvar i;
for (i = 0; i < 7; i = i + 1) begin
cmp cmp2 (
Gi[i],... | 7.603244 |
module _80_lcu_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
genera... | 6.895825 |
module $__CMP2LCU (A, B, P, G, Y);
parameter AB_WIDTH = 0;
parameter AB_SIGNED = 0;
parameter LCU_WIDTH = 1;
parameter BUDGET = 0;
parameter CI = 0;
(* force_downto *)
input [AB_WIDTH-1:0] A; // A from original $gt/$ge
(* force_downto *)
input [AB_WIDTH-1:0] B; // B from original $gt/$ge
(* force_downto *)
input [LCU... | 8.083463 |
module _90_lut_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_CONSTMSK_A_ = 0;
parameter _TECHMAP_CONSTVAL... | 6.895568 |
module cmp3 (
input X1,
X2,
X3,
X4,
Cin,
output Sum,
Carry,
Cout
);
wire w3, w4;
xnor (w3, X3, X4);
xnor (w4, X1, X2);
nand (Sum, w3, w4);
assign Carry = X4;
assign Cout = 1'b0;
endmodule
| 6.962954 |
module cmp4 (
input X1,
X2,
X3,
X4,
Cin,
output Sum,
Carry,
Cout
);
wire w1, w2, w3, w4;
nand (w1, X1, X2);
nand (w2, X3, X4);
nand (Carry, w1, w2);
xnor (w3, X3, X4);
xnor (w4, X1, X2);
nand (Sum, w3, w4);
assign Cout = 1'b0;
endmodule
| 6.94667 |
module cmp6 (
output equal,
input [0:5] a,
input [0:5] b
);
wire eq_0;
wire eq_1;
wire eq_2;
wire eq_3;
wire eq_4;
wire eq_5;
// DUPLO.NET (123) - eq[0-5] : en
assign eq_0 = ~(a[0] ^ b[0]);
assign eq_1 = ~(a[1] ^ b[1]);
assign eq_2 = ~(a[2] ^ b[2]);
assign eq_3 = ~(a[3] ^ b[3]);
... | 6.717214 |
module cmp6i (
output equal_n,
input [0:5] a,
input [0:5] b
);
wire eq_0;
wire eq_1;
wire eq_2;
wire eq_3;
wire eq_4;
wire eq_5;
// DUPLO.NET (130) - eq[0-5] : en
assign eq_0 = ~(a[0] ^ b[0]);
assign eq_1 = ~(a[1] ^ b[1]);
assign eq_2 = ~(a[2] ^ b[2]);
assign eq_3 = ~(a[3] ^ b[3]);
... | 6.657589 |
module CMPBlock (
input [15:0] OutputA,
input [15:0] OutputB,
output [ 3:0] CMPFlag
);
wire signed [15:0] a;
wire signed [15:0] b;
assign a = OutputA;
assign b = OutputB;
assign CMPFlag[0] = (b == a);
assign CMPFlag[1] = (b > a);
assign CMPFlag[2] = (b >= a);
assign CMPFlag[3] = ~((b ==... | 8.151404 |
module cmpl_mult #(
parameter REAL_WIDTH = 18,
parameter IMGN_WIDTH = 18,
localparam CPLX_WIDTH = REAL_WIDTH + IMGN_WIDTH
) (
input clock,
input [REAL_WIDTH-1:0] dataa_real,
input [IMGN_WIDTH-1:0] dataa_imag,
input [REAL_WIDTH-1:0] datab_real,
input [IMGN_WIDTH-1:... | 7.333495 |
module cmpMul_wrapper #(
parameter DATALEN = 16
) (
input clk,
input rstn,
input s_axis_a_tvalid,
input [2*DATALEN-1 : 0] s_axis_a_tdata,
input s_axis_b_tvalid,
input [2*DATALEN-1 : 0] s_axis_b_tdata,
output m_axis_dout_tvalid,
output [2*DATALEN-1 : 0] m_axis_dout_tdata
);
wire ... | 6.548276 |
module CMPR (
branchOp,
regIn,
reg15In,
jmpTrue,
result
);
input [1:0] branchOp;
input [15:0] regIn, reg15In;
output reg jmpTrue;
output reg [15:0] result;
always @(*) begin
result = regIn - reg15In;
if (branchOp == 2'b11) begin
if ((result[15] == 0) && (result > 0)) jmpT... | 7.913925 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module CMPR_tb ();
reg [1:0] branchOp;
reg [15:0] regIn, reg15In;
wire jmpTrue;
wire [15:0] result;
CMPR DUT (
.branchOp(branchOp),
.regIn(regIn),
.reg15In(reg15In),
.jmpTrue(jmpTrue),
.result(result)
);
initial begin
branchOp = 2'b00;
regIn = 10;
reg15In = 0;
... | 7.760732 |
module CMPTrig (
input clk,
input rst_n,
input [ 6:0] in1,
input [ 6:0] in2,
input [ 6:0] in3,
input [ 6:0] in4,
input [ 6:0] in5,
input [ 6:0] in6,
input [31:0] bin,
output reg [ 6:0] o1,
output reg [ 6:0] o2,
ou... | 6.710045 |
module CMPXCHG32 (
rm32,
r32,
eax_in,
dest,
eax_out,
eflags
);
input [31:0] rm32; //register or memory value, dest
input [31:0] r32; //always a register value, src
input [31:0] eax_in;
output [31:0] dest;
output [31:0] eax_out;
output [5:0] eflags;
wire zf;
comp32 cmp (
... | 7.999403 |
module CMPXCHG16 (
rm16,
r16,
ax_in,
dest,
ax_out,
eflags
);
input [15:0] rm16; //register or memory value, dest
input [15:0] r16; //always a register value, src
input [15:0] ax_in;
output [15:0] dest;
output [15:0] ax_out;
output [5:0] eflags;
wire zf;
comp16 cmp (
.a(... | 7.388079 |
module CMPXCHG8 (
rm8,
r8,
al_in,
dest,
al_out,
eflags
);
input [7:0] rm8; //register or memory value, dest
input [7:0] r8; //always a register value, src
input [7:0] al_in;
output [7:0] dest;
output [7:0] al_out;
output [5:0] eflags;
wire zf;
comp8 cmp (
.a(al_in),
... | 6.561809 |
module Cmp_1bit (
gt,
eq,
lt,
a,
b,
gt_up,
eq_up,
lt_up
);
input a;
input b;
input gt_up;
input eq_up;
input lt_up;
output gt;
output eq;
output lt;
wire a_n;
wire b_n;
wire gt_cur;
wire eq_cur;
wire lt_cur;
not (b_n, b);
and (gt_cur, a, b_n);
or (gt, g... | 6.523104 |
module cmp_2 (
DataA,
DataB,
AGEB
);
input [7:0] DataA, DataB;
output AGEB;
wire le_OUT, U1, U2, AND3_0_Y, NAND3A_0_Y, AO1D_0_Y, OR2A_1_Y,
AO1C_0_Y, AO1C_1_Y, OR2A_0_Y, AO1C_4_Y, NOR2A_0_Y,
AO1C_3_Y, AO1C_2_Y, OR2A_3_Y, AO1C_5_Y, NOR3A_0_Y,
OR2A_2_Y, NAND3A_1_Y, XNOR2_1_Y, ... | 6.684654 |
module cmp_32 (
input [31:0] a,
input [31:0] b,
input [2:0] ctrl,
output c
);
localparam cmp_EQ = 3'b001;
localparam cmp_NE = 3'b010;
localparam cmp_LT = 3'b011;
localparam cmp_LTU = 3'b100;
localparam cmp_GE = 3'b101;
localparam cmp_GEU = 3'b110;
wire res_EQ = a == b;
wire res_NE = ~re... | 6.593335 |
module cmp_43 (
input [7:0] io_dip,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
reg [15:0] holder;
always @* begin
holder = 1'h0;
case (io_dip[1+1-:2])
1'h1: begin
holder = {15'h0000, (a == b)};
end
2'h2: begin
holder = {15'h0000, (a < b)};... | 6.622231 |
module cmp_7 (
input clk,
input rst,
input [7:0] io_dip,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
reg [15:0] holder;
always @* begin
holder = 1'h0;
case (io_dip[1+1-:2])
1'h1: begin
holder = {15'h0000, (a == b)};
end
2'h2: begin
... | 6.572847 |
module cmp_and_mux_ID_BITS8_INTPRIORITY_BITS4 (
a_id,
a_priority,
b_id,
b_priority,
out_id,
out_priority
);
input [7:0] a_id;
input [3:0] a_priority;
input [7:0] b_id;
input [3:0] b_priority;
output [7:0] out_id;
output [3:0] out_priority;
wire [7:0] out_id;
wire [3:0] out_prior... | 7.470804 |
module get_read_addr_start #(
parameter MSB = `RAM_ADDR_MSB
) (
input [MSB:0] in, // total number of hashes (>0)
output [MSB-1:0] read_addr_start,
output [MSB-1:0] addr_diff_start
);
wire [MSB-1:0] in_shr = in[MSB:1];
genvar i;
generate
for (i = 0; i < MSB; i = i + 1) begin : gen_read_addr
... | 7.446357 |
module cmp_D (
input [31:0] RD1,
input [31:0] RD2,
input [31:0] Instr,
output Branch
);
`include "macros.v"
wire [31:0] instr;
assign instr = Instr; //궨ʹ
assign Branch = (`beq && (RD1 == RD2)) ? 1 : (`bgez && ($signed(
RD1
) >= 0)) ? 1 : (`bgtz && ($signed(
RD1
) > 0)) ? 1 : (... | 8.004554 |
module cmp_data (
clk,
data_valid,
lfsr_data,
read_data,
rst,
read_data_out,
lfsr_data_out,
led_error_output,
data_valid_out
);
input clk;
input data_valid;
input [143:0] lfsr_data /* synthesis syn_keep=1 */;
input [143:0] read_data;
input rst;
output [143:0] read_data_... | 6.643498 |
module CMP_ERROR (
input [3:0] A,
B,
output reg ERROR
);
always @(A, B) begin
if (B > A) ERROR = 1;
else ERROR = 0;
end
endmodule
| 6.542926 |
module cmp_ls #(
parameter W = 32
) (
input sgn,
input [W-1:0] a,
input [W-1:0] b,
output [W-1:0] out
);
wire [W-1:0] found;
wire [W-1:0] cmp_res;
assign found[W-1] = a[W-1] ^ b[W-1];
assign cmp_res[W-1] = ~a[W-1] & b[W-1];
genvar i;
generate
for (i = W - 2; i >= 0; i... | 7.191576 |
module CMP_unit #(
parameter A_WIDTH = 8,
B_WIDTH = 8,
OUT_WIDTH = 16,
ALU_FUN_WIDTH = 2
) (
input wire [ A_WIDTH-1:0] A,
input wire [ B_WIDTH-1:0] B,
input wire [ALU_FUN_WIDTH-1:0] ALU_FUN,
input wire CMP_Enable,
input wire CLK,
... | 8.168587 |
module <<default_slave_name>> (
// Common AHB signals
HCLK,
HRESETn,
// AHB control input signals
HSEL,
HTRANS,
HREADY,
// AHB control output signals
HREADYOUT,
HRESP
);
// -----------------------------------------------------------------------------
// Input and Output... | 6.859126 |
module cmsdk_ahb_default_slave (
// Inputs
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HSEL, // Slave select
input wire [1:0] HTRANS, // Transfer type
input wire HREADY, // System ready
// Outputs
output wire HREADYOUT, // Slav... | 7.999759 |
module cmsdk_ahb_eg_slave #(
// Parameter for address width
parameter ADDRWIDTH = 12
) (
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire [3:0] ECOREVNUM, // Engineering-change-order revision bits
// AHB connection to master
input wire HSELS,
input ... | 8.10503 |
module cmsdk_ahb_fileread_funnel (
// Clock and Reset
input wire HCLK,
input wire HRESETn,
// Interface to AHB
input wire HADDR2S,
input wire [63:0] HWDATAS,
input wire HREADYS,
output wire [63:0] HRDATAS,
// Interface to slave
output reg [31:0] ... | 9.761503 |
module cmsdk_ahb_fileread_master32 #(
parameter InputFileName = "filestim.m2d", // stimulus data file name
parameter MessageTag = "FileReader:", // tag on each FileReader message
parameter StimArraySize = 5000
) // stimulus data array size:
// should be large enough to hold
// entire stim... | 9.761503 |
module ties together the sub blocks that
// form the 64-bit File Reader Bus Master, namely an
// AHB-Lite File Reader Core and a wrapper logic.
// --========================================================================--
// Note
// This top level ... | 9.884596 |
module cmsdk_ahb_to_ahb_apb_async_launch #(
parameter WIDTH = 32
) (
input wire CLK,
input wire RSTn,
input wire EN,
input wire [WIDTH-1:0] D,
output wire [WIDTH-1:0] Q
);
// --------
// Clock enabled D-type register.
reg [WIDTH-1:0] q_q;
always... | 8.926898 |
module cmsdk_ahb_to_ahb_apb_async_sample_and_hold #(
parameter WIDTH = 32
) (
input wire CLK,
input wire EN,
input wire MASK,
input wire [WIDTH-1:0] D,
output wire [WIDTH-1:0] Q
);
// --------
// Clock enabled D-type register.
reg [WIDTH-1:0] q_q;
... | 8.926898 |
module cmsdk_ahb_to_ahb_apb_async_synchronizer (
input wire CLK,
input wire D,
output wire Q
);
reg [1:0] q_q;
always @(posedge CLK) q_q <= {q_q[0], D};
assign Q = q_q[1];
endmodule
| 8.926898 |
module define a double flip-flop synchronizer
//
module cmsdk_ahb_to_apb_async_syn (
// --------------------------------------------------------------------------
// Port Definitions
// --------------------------------------------------------------------------
input wire clk,
input wire resetn,
input... | 8.610844 |
module cmsdk_ahb_to_iop
// ----------------------------------------------------------------------------
// Port Definitions
// ----------------------------------------------------------------------------
( // AHB Inputs
input wire HCLK, // system bus clock
input wire HRESETn, // system bus r... | 8.926898 |
module cmsdk_ahb_upsizer64 (
input wire HCLK, // Clock
input wire HRESETn, // Reset
// AHB connection to master
input wire HSELS,
input wire [31:0] HADDRS,
input wire [ 1:0] HTRANSS,
input wire [ 2:0] HSIZES,
input wire HWRITES,
input wire HREADYS,
input ... | 9.28891 |
module cmsdk_apb3_eg_slave #(
// parameter for address width
parameter ADDRWIDTH = 12
) (
// IO declaration
input wire PCLK, // pclk
input wire PRESETn, // reset
// apb interface inputs
input wire PSEL,
input wire [ADDRWIDTH-1:0] PADDR,
input wire ... | 8.085052 |
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