code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module.
// Convert APB BUS protocol to simple register read write protocol
//-----------------------------------------------------------------------------
module cmsdk_apb3_eg_slave_interface #(
// parameter for address width
parameter ADDRWIDTH = 12)
(
// IO declaration
input wire ... | 7.106232 |
module.
// Convert APB BUS protocol to simple register read write protocol
//-----------------------------------------------------------------------------
module cmsdk_apb3_eg_slave_interface_led #(
// parameter for address width
parameter ADDRWIDTH = 12)
(
// IO declaration
input wire ... | 7.106232 |
module cmsdk_apb3_eg_slave_led #(
// parameter for address width
parameter ADDRWIDTH = 12
) (
// IO declaration
input wire PCLK, // pclk
input wire PRESETn, // reset
// apb interface inputs
input wire PSEL,
input wire [ADDRWIDTH-1:0] PADDR,
input wire ... | 8.085052 |
module. Transfer APB BUS protocol to
// simple register read write protocol
//-----------------------------------------------------------------------------
module cmsdk_apb4_eg_slave_interface #(
// parameter for address width
parameter ADDRWIDTH = 12)
(
// IO declaration
input wire ... | 8.043293 |
module cmsdk_apb_test_slave (
// IO declaration
input wire PCLK, // clock
input wire PRESETn, // reset
// APB interface inputs
input wire PSEL,
input wire [11:2] PADDR,
input wire PENABLE,
input wire PWRITE,
input wire [31:0] PWDATA,
input wire [ 3:0] PST... | 6.690237 |
module cmsdk_clock_gate #(
// ---------------------------------------------------------------------------
// Parameters
// ---------------------------------------------------------------------------
parameter CLKGATE_PRESENT = 0
) (
// ----------------------------------------------------------------... | 9.333318 |
module cmsdk_debug_tester_ahb_interconnect ( // Inputs
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire HREADYOUTS0,
input wire [31:0] HRDATAS0,
input wire HRESPS0,
input wire HREADYOUTS1,
input wire [31:0] HRDATAS1,
... | 7.69895 |
module cmsdk_flash_rom16 #(
// --------------------------------------------------------------------------
// Parameter Declarations
// --------------------------------------------------------------------------
parameter AW = 16, // Address width
parameter filename = "image.dat",
... | 8.052916 |
module cmsdk_flash_rom32 #(
// --------------------------------------------------------------------------
// Parameter Declarations
// --------------------------------------------------------------------------
parameter AW = 16, // Address width
parameter filename = "image.dat",
... | 8.052916 |
module cmsdk_fpga_rom #(
// --------------------------------------------------------------------------
// Parameter Declarations
// --------------------------------------------------------------------------
parameter AW = 16,
parameter filename = ""
) (
// Inputs
input wire CLK,
... | 7.319234 |
module cmsdk_fpga_sram #(
// --------------------------------------------------------------------------
// Parameters
// --------------------------------------------------------------------------
parameter AW = 16
) (
// Inputs
input wire CLK,
input wire [AW-1:0] ADDR,
input wir... | 6.914352 |
module cmsdk_irq_sync (
input wire RSTn,
input wire CLK,
input wire IRQIN,
output wire IRQOUT
);
reg [2:0] sync_reg;
wire [2:0] nxt_sync_reg;
assign nxt_sync_reg = {sync_reg[1:0], IRQIN};
always @(posedge CLK or negedge RSTn) begin
if (~RSTn) sync_reg <= 3'b000;
else sync_reg <= n... | 6.866149 |
module cmsdk_L1AhbMtx_default_slave (
// Common AHB signals
HCLK,
HRESETn,
// AHB control input signals
HSEL,
HTRANS,
HREADY,
// AHB control output signals
HREADYOUT,
HRESP
);
// -----------------------------------------------------------------------------
// Input and ... | 7.074088 |
module cmsdk_mcu_clkctrl #(
parameter CLKGATE_PRESENT = 0
) (
input wire XTAL1, // Clock source
input wire NRST, // active low external reset
input wire APBACTIVE, // APB active status
input wire SLEEPING, // Sleep status
input wire SLEEPDEEP, // Deep Sleep status
input wire SY... | 8.53182 |
module cmsdk_mcu_mtx4x2_default_slave (
// Common AHB signals
HCLK,
HRESETn,
// AHB control input signals
HSEL,
HTRANS,
HREADY,
// AHB control output signals
HREADYOUT,
HRESP
);
// -----------------------------------------------------------------------------
// Input an... | 8.338315 |
module cmsdk_mcu_stclkctrl #(
// Ratio between FCLK and SysTick reference clock
parameter DIV_RATIO = 18'd01000,
// Divide by half for each phase
parameter DIVIDER_RELOAD = (DIV_RATIO >> 1) - 1
) (
input wire FCLK, // Free running clock
input wire SYSRESETn, // System reset
output wir... | 7.381038 |
module cmsdk_MyBusMatrixName_default_slave (
// Common AHB signals
HCLK,
HRESETn,
// AHB control input signals
HSEL,
HTRANS,
HREADY,
// AHB control output signals
HREADYOUT,
HRESP
);
// -----------------------------------------------------------------------------
// Inp... | 7.887525 |
module cmsdk_sram256x16 #(
parameter AW = 18, // Address width
parameter filename = ""
) (
input wire [AW-1:0] Address,
inout wire [ 15:0] DataIO,
input wire WEn,
input wire OEn,
input wire CEn,
input wire LBn,
input wire UBn
);
... | 7.656791 |
module cmsdk_sram256x8 #(
parameter AW = 18, // Address width
parameter filename = ""
) (
input wire [AW-1:0] Address,
inout wire [ 7:0] DataIO,
input wire WEn,
input wire OEn,
input wire CEn
);
reg [7:0] ram_data [0:((1<<AW)-1)]; // 256k... | 7.656791 |
module cmt_apb (
clk,
rst_n,
//---------------------------------
//APB bus interface
psel_i,
pwrite_i,
penable_i,
paddr_i,
pwdata_i,
prdata_o,
pslverr_o,
pready_o,
//---------------------------------
// Register file interface
reg_wen_o,
reg_wdata_o,
r... | 8.42478 |
module cmt_common #(
parameter FREQ_IN = 48,
parameter CLK2_DIVIDE = 8,
parameter CLK2_FREQ = 192,
parameter PLL_FREQ = 0
) (
input I,
output CLK2,
output PLL_CLK
);
// ******************************************************
//
// Available frequencies from CLK2 (FREQ_IN=48)
// (*) ... | 7.789994 |
module cmu (
clk_in,
clk_out,
stop,
resume_n
);
input clk_in;
input stop;
input resume_n;
output clk_out;
wire clk_stop_n;
wire clk_stop_n_tmp;
// if stop == 1 && resume_n = 1
// then stop clock
nand2$ nand_0 (
clk_stop_n_tmp,
stop,
resume_n
);
dff$ dff_clk (
... | 6.622265 |
module cmul7p8 // ------> Interface
(
input signed [4:0] x, // System input
output signed [4:0] y0,
y1,
y2,
y3
);
// The 4 system outputs y=7*x/8
// --------------------------------------------------------
assign y0 = 7 * x / 8;
assign y1 = x / 8 * 7;
assign y2 = x / 2 + x / 4 + x / 8;
... | 6.623133 |
module cmu_sim (
input wire clk,
input wire rst,
output reg [7:0] clk_count = 0,
output reg [7:0] inst_count = 0,
output reg [7:0] hit_count = 0
);
// instruction
reg [3:0] index = 0;
wire valid;
wire write;
wire [31:0] addr;
wire [2:0] u_b_h_w;
wire stall;
inst INST (
.clk(cl... | 6.793663 |
module cm_alloc ( /*AUTOARG*/
`ifndef ENABLE_CRRD
s,
`endif
// Outputs
sra,
wra,
nra,
era,
lra,
scfg,
ncfg,
wcfg,
ecfg,
lcfg,
// Inputs
wr,
er,
sr,
nr,
lr
);
//requests from all IMs
input [1:0] wr, er;
input [3:0] sr, nr, lr;
// ack to I... | 7.405136 |
module will auto-drain (read from) the CM FIFO when RingBufferMode
is enabled. It will stop on packet boundaries (designated by bit 8 of
the FIFO data).
-----------------------------------------------------------------------------*/
`timescale 1ns / 10ps
module CM_FIFO_autodrain (
input rst,
input FFE_CLK_g... | 7.582444 |
module CND_IR_CCAS (
in_a,
out_b,
out_c,
out_d
);
input [2:0] in_a;
output reg [1:0] out_b, out_c;
output out_d;
parameter param_a = 2;
parameter param_b = 3;
assign out_d = param_b ? 0 : 1;
always @(in_a) begin
case (1'b1)
in_a[0]: out_b = 2'b00;
in_a[1]: out_b = 2'b01;
... | 6.76906 |
module.
// Note: doesn't empty the buffer during operation
//
//
// Change history:
//
///////////////////////////////////////////////////////////////////////////////
module cnet_iface(
// CNET interface signals
// CPCI->CNET
input [31:0] p2n_data, // Data goin... | 7.106232 |
module cnna_udp_top (
// delete due to closed-source
);
// UDP interface
// --------------------------------------------------------------------------
// This part instance the UDP module, which is closed-source.
// --------------------------------------------------------------------------
// cnn accele... | 6.620531 |
module full_subber (
input [7:0] io_in_a,
input [7:0] io_in_b,
output [7:0] io_out_s,
output io_out_c
);
wire [8:0] _result_T = io_in_a - io_in_b; // @[Arithmetic.scala 70:23]
wire [9:0] _result_T_2 = _result_T - 9'h0; // @[Arithmetic.scala 70:34]
wire [8:0] result = _result_T_2[8:0]; /... | 6.57301 |
module twoscomplement (
input [7:0] io_in,
output [7:0] io_out
);
wire [7:0] x = ~io_in; // @[Arithmetic.scala 26:10]
assign io_out = x + 8'h1; // @[Arithmetic.scala 27:17]
endmodule
| 7.994634 |
module twoscomplement_1 (
input [23:0] io_in,
output [23:0] io_out
);
wire [23:0] x = ~io_in; // @[Arithmetic.scala 26:10]
assign io_out = x + 24'h1; // @[Arithmetic.scala 27:17]
endmodule
| 7.994634 |
module leadingOneDetector (
input [23:0] io_in,
output [ 4:0] io_out
);
wire [1:0] _hotValue_T = io_in[1] ? 2'h2 : 2'h1; // @[Mux.scala 47:70]
wire [1:0] _hotValue_T_1 = io_in[2] ? 2'h3 : _hotValue_T; // @[Mux.scala 47:70]
wire [2:0] _hotValue_T_2 = io_in[3] ? 3'h4 : {{1'd0}, _hotValue_T_1}; // @[Mux.... | 6.713451 |
module full_adder_1 (
input [7:0] io_in_a,
input [7:0] io_in_b,
output [7:0] io_out_s
);
wire [8:0] _result_T = io_in_a + io_in_b; // @[Arithmetic.scala 56:23]
wire [9:0] _result_T_1 = {{1'd0}, _result_T}; // @[Arithmetic.scala 56:34]
wire [8:0] result = _result_T_1[8:0]; // @[Arithmetic.scala 55... | 6.657465 |
module full_subber (
input [14:0] io_in_a,
input [14:0] io_in_b,
output [14:0] io_out_s,
output io_out_c
);
wire [15:0] _result_T = io_in_a - io_in_b; // @[Arithmetic.scala 70:23]
wire [16:0] _result_T_2 = _result_T - 16'h0; // @[Arithmetic.scala 70:34]
wire [15:0] result = _result_T_2[... | 6.57301 |
module twoscomplement (
input [14:0] io_in,
output [14:0] io_out
);
wire [14:0] x = ~io_in; // @[Arithmetic.scala 26:10]
assign io_out = x + 15'h1; // @[Arithmetic.scala 27:17]
endmodule
| 7.994634 |
module twoscomplement_1 (
input [112:0] io_in,
output [112:0] io_out
);
wire [112:0] x = ~io_in; // @[Arithmetic.scala 26:10]
assign io_out = x + 113'h1; // @[Arithmetic.scala 27:17]
endmodule
| 7.994634 |
module full_adder_1 (
input [14:0] io_in_a,
input [14:0] io_in_b,
output [14:0] io_out_s
);
wire [15:0] _result_T = io_in_a + io_in_b; // @[Arithmetic.scala 56:23]
wire [16:0] _result_T_1 = {{1'd0}, _result_T}; // @[Arithmetic.scala 56:34]
wire [15:0] result = _result_T_1[15:0]; // @[Arithmetic.s... | 6.657465 |
module full_subber (
input [4:0] io_in_a,
input [4:0] io_in_b,
output [4:0] io_out_s,
output io_out_c
);
wire [5:0] _result_T = io_in_a - io_in_b; // @[Arithmetic.scala 70:23]
wire [6:0] _result_T_2 = _result_T - 6'h0; // @[Arithmetic.scala 70:34]
wire [5:0] result = _result_T_2[5:0]; /... | 6.57301 |
module twoscomplement (
input [4:0] io_in,
output [4:0] io_out
);
wire [4:0] x = ~io_in; // @[Arithmetic.scala 26:10]
assign io_out = x + 5'h1; // @[Arithmetic.scala 27:17]
endmodule
| 7.994634 |
module twoscomplement_1 (
input [10:0] io_in,
output [10:0] io_out
);
wire [10:0] x = ~io_in; // @[Arithmetic.scala 26:10]
assign io_out = x + 11'h1; // @[Arithmetic.scala 27:17]
endmodule
| 7.994634 |
module leadingOneDetector (
input [10:0] io_in,
output [ 3:0] io_out
);
wire [1:0] _hotValue_T = io_in[1] ? 2'h2 : 2'h1; // @[Mux.scala 47:70]
wire [1:0] _hotValue_T_1 = io_in[2] ? 2'h3 : _hotValue_T; // @[Mux.scala 47:70]
wire [2:0] _hotValue_T_2 = io_in[3] ? 3'h4 : {{1'd0}, _hotValue_T_1}; // @[Mux.... | 6.713451 |
module full_adder_1 (
input [4:0] io_in_a,
input [4:0] io_in_b,
output [4:0] io_out_s
);
wire [5:0] _result_T = io_in_a + io_in_b; // @[Arithmetic.scala 56:23]
wire [6:0] _result_T_1 = {{1'd0}, _result_T}; // @[Arithmetic.scala 56:34]
wire [5:0] result = _result_T_1[5:0]; // @[Arithmetic.scala 55... | 6.657465 |
module full_subber (
input [10:0] io_in_a,
input [10:0] io_in_b,
output [10:0] io_out_s,
output io_out_c
);
wire [11:0] _result_T = io_in_a - io_in_b; // @[Arithmetic.scala 70:23]
wire [12:0] _result_T_2 = _result_T - 12'h0; // @[Arithmetic.scala 70:34]
wire [11:0] result = _result_T_2[... | 6.57301 |
module twoscomplement (
input [10:0] io_in,
output [10:0] io_out
);
wire [10:0] x = ~io_in; // @[Arithmetic.scala 26:10]
assign io_out = x + 11'h1; // @[Arithmetic.scala 27:17]
endmodule
| 7.994634 |
module twoscomplement_1 (
input [52:0] io_in,
output [52:0] io_out
);
wire [52:0] x = ~io_in; // @[Arithmetic.scala 26:10]
assign io_out = x + 53'h1; // @[Arithmetic.scala 27:17]
endmodule
| 7.994634 |
module full_adder_1 (
input [10:0] io_in_a,
input [10:0] io_in_b,
output [10:0] io_out_s
);
wire [11:0] _result_T = io_in_a + io_in_b; // @[Arithmetic.scala 56:23]
wire [12:0] _result_T_1 = {{1'd0}, _result_T}; // @[Arithmetic.scala 56:34]
wire [11:0] result = _result_T_1[11:0]; // @[Arithmetic.s... | 6.657465 |
module cnn_2_weights_1_0_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_2_weights_1... | 7.468744 |
module cnn_2_weights_1_0 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_2_weights_1_0_rom ... | 7.468744 |
module cnn_2_weights_1_1_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_2_weights_1... | 7.468744 |
module cnn_2_weights_1_1 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_2_weights_1_1_rom ... | 7.468744 |
module cnn_2_weights_1_2_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_2_weights_1... | 7.468744 |
module cnn_2_weights_1_2 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_2_weights_1_2_rom ... | 7.468744 |
module cnn_2_weights_1_3_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_2_weights_1... | 7.468744 |
module cnn_2_weights_1_3 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_2_weights_1_3_rom ... | 7.468744 |
module cnn_2_weights_1_4_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_2_weights_1... | 7.468744 |
module cnn_2_weights_1_4 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_2_weights_1_4_rom ... | 7.468744 |
module cnn_2_weights_1_5_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_2_weights_1... | 7.468744 |
module cnn_2_weights_1_5 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_2_weights_1_5_rom ... | 7.468744 |
module cnn_2_weights_1_6_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_2_weights_1... | 7.468744 |
module cnn_2_weights_1_6 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_2_weights_1_6_rom ... | 7.468744 |
module cnn_2_weights_1_7_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_2_weights_1... | 7.468744 |
module cnn_2_weights_1_7 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_2_weights_1_7_rom ... | 7.468744 |
module cnn_2_weights_1_8_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_2_weights_1... | 7.468744 |
module cnn_2_weights_1_8 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_2_weights_1_8_rom ... | 7.468744 |
module cnn_3_weights_2_0_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_3_weights_... | 7.187693 |
module cnn_3_weights_2_0 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_3_weights_2_0_rom... | 7.187693 |
module cnn_3_weights_2_1_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_3_weights_... | 7.187693 |
module cnn_3_weights_2_1 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_3_weights_2_1_rom... | 7.187693 |
module cnn_3_weights_2_2_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_3_weights_... | 7.187693 |
module cnn_3_weights_2_2 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_3_weights_2_2_rom... | 7.187693 |
module cnn_3_weights_2_3_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_3_weights_... | 7.187693 |
module cnn_3_weights_2_3 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_3_weights_2_3_rom... | 7.187693 |
module cnn_3_weights_2_4_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_3_weights_... | 7.187693 |
module cnn_3_weights_2_4 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_3_weights_2_4_rom... | 7.187693 |
module cnn_3_weights_2_5_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_3_weights_... | 7.187693 |
module cnn_3_weights_2_5 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_3_weights_2_5_rom... | 7.187693 |
module cnn_3_weights_2_6_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_3_weights_... | 7.187693 |
module cnn_3_weights_2_6 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_3_weights_2_6_rom... | 7.187693 |
module cnn_3_weights_2_7_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_3_weights_... | 7.187693 |
module cnn_3_weights_2_7 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_3_weights_2_7_rom... | 7.187693 |
module cnn_3_weights_2_8_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./cnn_3_weights_... | 7.187693 |
module cnn_3_weights_2_8 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
cnn_3_weights_2_8_rom... | 7.187693 |
module cnn_accel (
clk,
resetn,
o_rd_rdy,
i_start,
i_we,
i_waddr,
i_din,
o_we,
o_dout,
o_cycles,
o_commands,
o_fc_cycles,
i_debug_rdy,
o_debug_vld,
o_fill,
i_fifo_empty,
i_fifo_low,
o_fifo_rd,
i_fifo_dout,
o_status
);
input clk;
input r... | 7.153993 |
module cnn_accel (
clk,
resetn,
o_rd_rdy,
i_start,
i_we,
i_waddr,
i_din,
o_we,
o_dout,
o_cycles,
o_commands,
o_fc_cycles,
i_debug_rdy,
o_debug_vld,
o_fill,
i_fifo_empty,
i_fifo_low,
o_fifo_rd,
i_fifo_dout,
o_status
) /* synthesis syn_black... | 7.153993 |
module cnn_acc_ci (
// Clock & Reset
clk,
reset_n,
i_soft_reset,
i_cnn_weight,
i_in_valid,
i_in_fmap,
o_ot_valid,
o_ot_ci_acc
);
`include "defines_cnn_core.vh"
localparam LATENCY = 1;
input clk;
input reset_n;
input i_soft_reset;
input [CI*KX*KY*W_BW-1 : 0] i_cnn_weight;... | 6.666568 |
module cnn_add_layer14 (
clk,
reset,
valid_in_no1,
in_no1,
valid_in_no2,
in_no2,
out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
///////////////////////////////////////////////////... | 7.336426 |
module cnn_add_layer2 (
clk,
reset,
valid_in_no1,
in_no1,
valid_in_no2,
in_no2,
out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
////////////////////////////////////////////////////... | 7.336426 |
module cnn_add_layer3 (
clk,
reset,
valid_in_no1,
in_no1,
valid_in_no2,
in_no2,
out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
////////////////////////////////////////////////////... | 7.336426 |
module for cnn_AVS_top module
* It is just a simulated module.
*
* ports:
* tb_load_done_i: write data to ddr done.
* rd_data_full_i: read data to feature in buffer finish
* rd_data_load_ddr_done_rising_edge_i: write data to ddr done rising edge
*/
module cnn_AVS_control_sim
#(
)
(
// port definiti... | 8.068489 |
module cnn_conv_relu (
clk,
reset,
valid_in,
in,
out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
/////////////////////////////////////////////////////////////////////////
// Port Declara... | 7.549662 |
module cnn_fifo (
//input
clk
, reset
, write
, read
, data_in
//output
, data_out
, full
, empty
);
/////////////////////////////////////////////////////////////////////////
// Parameter
parameter DATA_WIDTH = 32;
parameter DATA_DEPTH = 131072;
parameter POINTER_WIDTH... | 8.264873 |
module cnn_kernel (
// Clock & Reset
clk,
reset_n,
i_soft_reset,
i_cnn_weight,
i_in_valid,
i_in_fmap,
o_ot_valid,
o_ot_kernel_acc
);
`include "defines_cnn_core.vh"
localparam LATENCY = 2;
input clk;
input reset_n;
input i_soft_reset;
input [KX*KY*W_BW-1 : 0] i_cnn_weight... | 6.504565 |
module
module convolutional_layer(input clk, input [15:0] data_in, output reg [15:0] data_out, parameter H = 256, parameter W = 256, parameter padding = 1, parameter filters = 64);
// Define the parameters for the convolutional layer
// (these will be specific to the trained CNN)
parameter filter_width = 3;
pa... | 6.789571 |
module CNNmemory (
output [399:0] data_out, //25 * 16 bit
input [15:0] address,
input [15:0] data_in,
input write_enable,
input clk
);
reg [15:0] CNNmemory [0:65535]; //2^16 //memory size 6*5*5 (150)+ 96*5*5 (2400) + 1920*5*5 (48000) + 32*32 (1024) io outputs + 3 + 6 + 96 + 1920 + 4704 + 1167... | 6.980202 |
module cnn_sigmoid (
clk
, reset
, valid_in
, in
, out
, valid_out
, done
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
/////////////////////////////////////////////////////////////////////////
// ... | 6.59677 |
module CNN_top (
input clk,
input rst_n,
input [7:0] data_in,
output [3:0] decision,
output valid_out_6
);
wire signed [11:0] conv_out_1, conv_out_2, conv_out_3;
wire signed [11:0] conv2_out_1, conv2_out_2, conv2_out_3;
wire signed [11:0] max_value_1, max_value_2, max_value_3;
wire signed [... | 6.64896 |
module cnn_upsampling_nn_test (
clk,
reset,
valid_in,
pxl_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter C... | 6.761193 |
module CNORM (
CLK,
ED,
START,
DR,
DI,
SHIFT,
OVF,
RDY,
DOR,
DOI
);
`USFFT64paramnb
output OVF;
reg OVF;
output RDY;
reg RDY;
output [nb+1:0] DOR;
wire [nb+1:0] DOR;
output [nb+1:0] DOI;
wire [nb+1:0] DOI;
input CLK;
wire CLK;
input ED;
wire ED;
inpu... | 6.532138 |
module cnot_gate (
input a,
b,
output w,
x
);
assign w = a;
assign x = a ^ b;
endmodule
| 6.503187 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.