code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module CNROM #(
parameter MIRRORING_VERTICAL = 1
) (
output led,
input m2,
input romsel,
input cpu_rw_in,
output [18:12] cpu_addr_out,
input [14:0] cpu_addr_in,
input [7:0] cpu_data_in,
output cpu_wr_out,
output cpu_rd_out,
output cpu_flash_ce,
output cpu_sram_ce,
i... | 6.974396 |
module cnt (
input clk,
input rst_n,
//input clr, //Counter synchronous reset
output reg [ 3:0] data, //counter value
output reg t, // carry enable signal
output reg [31:0] bin
);
always @(posedge clk or negedge rst_n) begin
if (rst_n ==... | 7.276992 |
module cnt0 (
out0,
clk,
rst
);
input clk, rst;
output reg [3:0] out0;
always @(posedge clk or negedge rst) begin
if (!rst) begin
out0 <= 4'b0000;
end else if (out0 == 9) begin
out0 <= 4'b0000;
end else begin
out0 <= out0 + 1;
end
end
endmodule
| 7.292556 |
module cnt138t (
input clk,
input rst_n,
output [7:0] cnt8
);
reg [7:0] CNT;
wire LD;
always @(posedge clk or posedge LD or negedge rst_n) begin
if (!rst_n) CNT <= 8'b00000000;
else if (LD) CNT <= 8'b00000000;
else CNT <= CNT + 1;
end
assign cnt8 = CNT;
assign LD = (CNT == ... | 6.84866 |
module cnt16 (
clk,
rst_n,
cnt
);
input clk;
input rst_n;
output [3:0] cnt;
reg [3:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
cnt <= 4'b0000;
end else if (&cnt) begin
cnt <= 4'b0000;
end else begin
cnt <= cnt + 4'b0001;
end
end
endm... | 7.109542 |
module cnt16_tb ();
reg tb_clk;
reg tb_rst_n;
wire [3:0] tb_cnt;
cnt16 dut (
.clk (tb_clk),
.rst_n(tb_rst_n),
.cnt (tb_cnt)
);
initial begin
tb_clk = 1'b0;
end
always #10 tb_clk = ~tb_clk;
initial begin
tb_rst_n = 1'b1;
#11 tb_rst_n = 1'b0;
#25 tb... | 6.873507 |
module cnt16_tb ();
reg tb_clk, tb_rst_n;
reg tb_clk, tb_rst_n;
cnt16 dut
(.clk(tb_clk), .rst_n(tb_rst_n), cnt(tb_cnt));
initial begin
tb_clk = 1b0;
end
always #10 tb_clk = ~tb_clk;
initial begin
tb_rst_n = 1b1;
#11 tb_rst_n = 1b0;
#25 tb_rst_n = 1b1;
#100 $finis... | 6.873507 |
module CNT2 (
input CLK,
input nLOAD,
CEN1,
CEN2,
input [3:0] D,
output reg [3:0] Q
);
always @(posedge CLK) begin
if (!nLOAD) Q <= D;
else if (CEN1 & CEN2) Q <= Q + 1'b1;
end
endmodule
| 6.73408 |
module cnt2s (
input clk,
rst_n,
output [3:0] o_cnt
);
reg [3:0] cnt;
//异步复位
/* always @ (posedge clk or negedge rst_n) begin
if ( !rst_n )
cnt <= 4'b0000;
else if ( cnt == 4'b1111 )
cnt <= 4'b0000;
else
cnt <= cnt + 1'b1;
end */
//同步复位
always @(posedge clk) beg... | 6.977068 |
module cnt5 (
cnt,
clk,
reset_n,
inc
); //cnt5
input clk, reset_n, inc; // 3 inputs
output [2:0] cnt; // 3bits output cnt
parameter zero = 3'b000; // define zero = 000
parameter one = 3'b001; // define one = 001
parameter two = 3'b010; // define tow = 010
parameter three = 3'b011... | 7.363188 |
module CNT7B (
input clk,
input reset_n,
input en,
output reg [6:0] q
);
always @(posedge clk, negedge reset_n)
if (!reset_n) q <= 0;
else if (en) q <= q + 1'b1;
endmodule
| 6.678774 |
module cnte3 (
output count_0,
output count_1,
output count_2,
input cnten,
input clk,
input reset_n,
input sys_clk // Generated
);
wire sum_1;
wire carry_1;
wire sum_2;
wire cnti_0;
wire count_n_0;
wire cnti_1;
wire cnti_2;
wire countt_0;
wire countt_1;
wire countt... | 6.814505 |
module cnt_johnson (
input clk,
rst_n,
output [3:0] o_cnt
);
reg [3:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 4'b0000;
end else begin
cnt <= {~cnt[0], cnt[3:1]};
end
end
assign o_cnt = cnt;
endmodule
| 7.714034 |
module cntlz16 (
input [15:0] i,
output [ 4:0] o
);
wire [3:0] cnt1, cnt2;
cntlz8 u1 (
i[7:0],
cnt1
);
cntlz8 u2 (
i[15:8],
cnt2
);
assign o = cnt2[3] ? cnt1 + 4'h8 : cnt2;
endmodule
| 7.396899 |
module cntlz48 (
input [47:0] i,
output [ 5:0] o
);
wire [4:0] cnt1, cnt2, cnt3;
cntlz16 u1 (
i[15:0],
cnt1
);
cntlz16 u2 (
i[31:16],
cnt2
);
cntlz16 u3 (
i[47:32],
cnt3
);
assign o = !cnt3[4] ? cnt3 : !cnt2[4] ? cnt2 + 7'd16 : cnt1 + 7'd32;
endmodule
| 6.536275 |
module cntlz32Reg (
input clk,
input ce,
input [31:0] i,
output reg [5:0] o
);
wire [5:0] o1;
cntlz32 u1 (
i,
o1
);
always @(posedge clk) if (ce) o <= o1;
endmodule
| 7.612335 |
module cntlz64Reg (
input clk,
input ce,
input [63:0] i,
output reg [6:0] o
);
wire [6:0] o1;
cntlz64 u1 (
i,
o1
);
always @(posedge clk) if (ce) o <= o1;
endmodule
| 7.779508 |
module cntlo8 (
input [7:0] i,
output [3:0] o
);
cntlz8 u1 (
~i,
o
);
endmodule
| 6.664244 |
module cntlo16 (
input [15:0] i,
output [ 4:0] o
);
cntlz16 u1 (
~i,
o
);
endmodule
| 6.902003 |
module cntlo32 (
input [31:0] i,
output [ 5:0] o
);
cntlz32 u1 (
~i,
o
);
endmodule
| 6.875718 |
module cntlo48 (
input [47:0] i,
output [ 5:0] o
);
cntlz48 u1 (
~i,
o
);
endmodule
| 7.365986 |
module cntr (
clk,
ena,
rst,
sload,
sdata,
sclear,
q
);
parameter WIDTH = 16;
input clk, ena, rst, sload, sclear;
input [WIDTH-1:0] sdata;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or posedge rst) begin
if (rst) q <= 0;
else begin
if (ena) be... | 7.241485 |
module cntr4 (
input clk,
input reset,
input pe,
input [3:0] p,
input ce,
output [3:0] q,
output tc
);
wire [3:0] myd, qinc;
adder4 add_inc (
.A(q),
.B(4'b0001),
.C0(1'b0),
.S(qinc),
.C4() // open / unattached
);
reg4e cntr_reg (
.clk(clk),
... | 7.743502 |
module cntr8 (
clk,
reset_n,
inc,
load,
d_in,
d_out,
o_state
);
input clk, reset_n, inc, load;
input [7:0] d_in;
output [7:0] d_out;
output [2:0] o_state;
wire [2:0] next_state;
wire [2:0] state;
assign o_state = state;
ns_logic U1_ns_logic (
load,
inc,
s... | 7.799123 |
module countread (
clk,
clr,
in,
adr,
out
);
input clk;
input clr;
input [7:0] in;
output [1:0] adr;
output [31:0] out;
reg [31:0] out;
reg [31:0] buffer;
reg [ 3:0] cnt = 0;
assign adr[1] = cnt[3];
assign adr[0] = cnt[2];
always @(posedge clk or posedge clr) begin
if (... | 7.485981 |
module cnt_ring (
input clk,
rst_n,
output [3:0] o_cnt
);
reg [3:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 4'b0001;
end else begin
cnt <= {cnt[0], cnt[3:1]};
end
end
assign o_cnt = cnt;
endmodule
| 7.462111 |
module ROM #(
parameter BITS = 16,
ROWS = 16,
FILENAME = "filter_memory.mem"
) (
input [$clog2(ROWS)-1:0] addr,
input rd,
input clk,
output reg [BITS-1:0] out
);
reg [BITS-1:0] rom[0:ROWS-1];
initial begin
$readmemh(FILENAME, rom);
end
always @(posedge clk) begin
if (rd) ... | 8.457495 |
module DREGISTER #(
parameter BITS = 16
) (
input [BITS-1:0] in,
input clr,
input clk,
input enable,
output [BITS-1:0] out,
//DIAGNOSTICS
output clk2
);
//Clear all registers if clr flag is set
wire [BITS-1:0] clr_wire;
assign clr_wire = clr ? 1 : 0;
//"latch" enable
reg en... | 6.9946 |
module DFF (
input d,
input clr,
input clk,
output reg q
);
initial q = 1'b0;
always @(posedge clk, posedge clr) begin
if (clr) q <= 1'b0;
else begin
if ((d === 1'bx) | (d === 1'bz)) q <= q;
else q <= d;
end
end
endmodule
| 7.464833 |
module DATAPATH #(
parameter BITS = 16,
ORDER = 4,
ROWS = 16
) (
input clk,
input [$clog2(ROWS)-1:0] h_rom_addr,
input h_rom_rd,
input [$clog2(ROWS)-1:0] x_rom_addr,
input x_rom_rd,
input [ORDER:0] clrs,
input [ORDER:0] enables,
output [BITS*2-1:0] y,
//DIAGNOSTICS
... | 7.961048 |
module TAP_M #(
parameter BITS = 16
) (
input [BITS-1:0] tap,
input [BITS-1:0] x,
//For Tap register
input clr,
input enable,
input clk,
output reg [BITS*2-1:0] out,
//DIAGNOSTICS
output [BITS-1:0] tap_reg_out,
output clk2,
output [1:0] ctr_out
);
wire [BITS-1:0] ta... | 7.476 |
module TAP_X #(
parameter BITS = 16
) (
input [ BITS-1:0] tap,
input [ BITS-1:0] x,
input [BITS*2-1:0] prev_stage,
//FOR TAP REGISTER
input clr,
input enable,
input clk,
output reg [BITS*2-1:0] out,
//DIAGNOSTICS
output [BITS-1:0] tap_reg_out,
output clk2
);
wire ... | 7.163672 |
module TAP_0 #(
parameter BITS = 16
) (
input [ BITS-1:0] tap,
input [ BITS-1:0] x,
input [BITS*2-1:0] prev_stage,
input clr,
input enable,
input clk,
output reg [BITS*2-1:0] out,
//DIAGNOSTICS
output [BITS-1:0] tap_reg_out,
output clk2
);
//Setup Register to hold tap... | 7.285892 |
module CLA #(
parameter bits = 64
) ( //parameter to specify number of bits for adder
input [bits-1:0] A,
B, //augend and addend
input Cin, //first carry in
output [bits-1:0] Sum, //sum output
output Cout //carry out bit
//output [bits-1:0]carries //for testbench
);
wire [bits-1:0]... | 8.541544 |
module handles the carry outs for each partial full adder
//Acts as a wrapper to individual carry_gen modules
module CLL #(parameter bits = 8) (
input Cin,
input [bits-1: 0] P, G,
output [bits-1: 0] Cout
);
//Create carry generator block for first bit
CARRY_GEN INST0(
.G(G[0]),
.P(P[0]),
... | 7.545049 |
module ADD_HALF (
output cout,
output sum,
input a,
input b
);
xor (sum, a, b);
and (cout, a, b);
endmodule
| 7.323935 |
module PFA (
input A,
B,
Cin,
output P,
G,
S
);
assign P = A ^ B; //xor gate for propagate
assign G = A & B; // and gate for generate
assign S = Cin ^ P; // xor gate for sum
endmodule
| 7.633788 |
module cntrlr4 (
input count_done1,
count_done2,
input serin,
clk,
rst,
output reg valid,
encounter1,
encounter2,
output reg [5:0] smbs_ports,
num_of_inputs
);
parameter [1:0] idle = 2'b00, getportandsize = 2'b01, data = 2'b10, endcheck = 2'b11;
reg [1:0] ps, ns;
reg [11:0]... | 7.008219 |
module cntrl_fsm (
input clk,
rst,
input [`DATA_FRAME_SIZE-1:0] data_frame,
input [`CAP-1:0] rdata0,
rdata1,
output reg pc_inc_en,
pc_set_en,
mem_en,
reg_r_en,
alu_en,
reg_w_en,
output reg [`CAP-1:0] pc_set = `CAP'd0,
output reg [`CAP-1:0] raddr0,
raddr1,
wadd... | 7.586986 |
module cntr_11_0_6da79292a37693ee (
clk,
ce,
sinit,
q
) /* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input sinit;
output [2 : 0] q;
// synthesis translate_off
wire \blk00000001/sig0000000f ;
wire \blk00000001/sig0000000e ;
wire \blk00000001/sig0000000d ;
wire \b... | 6.50478 |
module cntr_11_0_7a9f00e1c86c8fba (
clk,
ce,
sinit,
q
) /* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input sinit;
output [3 : 0] q;
// synthesis translate_off
wire \blk00000001/sig00000013 ;
wire \blk00000001/sig00000012 ;
wire \blk00000001/sig00000011 ;
wire \b... | 6.613637 |
module cntr_3ud (
up_down, //count control
clk, //clock
reset, //reset
bin_count //output
);
//port declaration
input up_down, clk, reset; //count control, clock, reset declaration
output reg [2:0] bin_count; //output declaration
/*implement the counter when reset is 0, then execute up c... | 7.580827 |
module cntr_3ud_tb; //testbench module
reg up_down, clk, reset; //register declaration
wire [2:0] bin_count; //wire declaration for output
reg [2:0] new_count; //register declaration for new count value
//instantiation of design under test
cntr_3ud dut (
.up_down (up_down), //count control
... | 7.325289 |
module cntr_example #(
parameter BITS = 4
)(
`ifdef USE_POWER_PINS
inout vdd, // User area 1 1.8V supply
inout vss, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wire wb_clk_i,
input wire wb_rst_i,
//input wire wbs_stb_i,
//input wire wbs_cyc_i,
//inpu... | 7.714774 |
module cntr #(
parameter BITS = 4
) (
input clk, // Declare input port for the clock to allow counter to count up
input rstn, // Declare input port for the reset to allow the counter to be reset to 0 when required
output reg [BITS-1:0] out // Declare 4-bit output port to get the count... | 7.786403 |
module cntr_modulus (
clk,
ena,
rst,
sload,
sdata,
sclear,
q
);
parameter WIDTH = 16;
parameter MOD_VAL = 50223;
input clk, ena, rst, sload, sclear;
input [WIDTH-1:0] sdata;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
wire maxed = (q == MOD_VAL - 1) /* synthesis keep */;
a... | 6.604955 |
module cntr_modulus_la (
clk,
ena,
rst,
sload,
sdata,
sclear,
q
);
parameter WIDTH = 16;
parameter MOD_VAL = 50223;
input clk, ena, rst, sload, sclear;
input [WIDTH-1:0] sdata;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
// This register will be 1 when the counter is
// in ... | 6.787223 |
module cntr_reg_interface (
sel_cntr_bytes1,
sel_cntr_bytes2,
sel_cntr_bytes3,
sel_cntr_bytes4,
cntr1_val_reg,
cntr2_val_reg,
cntr3_val_reg,
cntr4_val_reg,
cntr1_in_byte,
cntr2_in_byte,
cntr3_in_byte,
cntr4_in_byte
);
input [26:0] cntr1_val_reg;
input [26:0] cntr2_va... | 6.794603 |
module Control_Unit (
output reg pcsel,
RF_we,
dm_we,
b_sel,
a_sel,
output reg [1:0] wb_sel,
output reg [2:0] imm_sel,
output reg [3:0] alu_sel,
input [31:0] ins,
input beq
);
//parameter NOPE =7'b000_0000; //DEFAULT
parameter LW = 7'b000_0011;
parameter SW = 7'b010_0011... | 8.640647 |
module Cntr_Unit (
input clk,
input reset,
output reg new_clk
);
reg [31:0] r_reg;
always @(posedge clk, posedge reset) begin
if (reset) begin
r_reg <= 0;
new_clk <= 0;
end else begin
if (r_reg == 50000000) begin //10000000
new_clk <= ~new_clk;
r_re... | 6.70873 |
module cntr_updn (
clk,
ena,
rst,
sload,
sdata,
sclear,
inc_not_dec,
q
);
parameter WIDTH = 16;
input clk, ena, rst, sload, sclear, inc_not_dec;
input [WIDTH-1:0] sdata;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or posedge rst) begin
if (rst) q <= ... | 6.592299 |
module cnt_attr1 (
input signed clock
, input signed [1:0] reset
, input signed [1:0] cond
, input signed [16:0] inp
, output reg signed [16:0] out
);
reg signed [1:0] t_pin9;
reg signed [16:0] \#x ;
reg signed [16:0] \#x_next ;
reg signed [16:0] t_pin40;
reg signed [16:0] \#x_5 ;
reg si... | 7.297821 |
module cnt_attr2 (
input signed clock
, input signed [1:0] reset
, input signed [1:0] cond
, input signed [16:0] inp
, output reg signed [16:0] out
);
reg signed [1:0] t_pin9;
reg signed [16:0] \#x ;
reg signed [16:0] \#x_next ;
reg signed [16:0] t_pin40;
reg signed [16:0] \#x_5 ;
reg si... | 7.335475 |
module cnt_attr3 (
input signed clock
, input signed [1:0] reset
, input signed [1:0] cond
, input signed [16:0] inp
, output reg signed [16:0] out
);
reg signed [1:0] t_pin9;
reg signed [16:0] \#x ;
reg signed [16:0] \#x_next ;
reg signed [16:0] t_pin40;
reg signed [16:0] \#x_5 ;
reg si... | 7.105583 |
module cnt_attr4 (
input signed clock
, input signed [1:0] reset
, input signed [1:0] cond
, input signed [16:0] inp
, output reg signed [16:0] out
);
reg signed [1:0] t_pin9;
reg signed [16:0] \#x ;
reg signed [16:0] \#x_next ;
reg signed [16:0] t_pin40;
reg signed [16:0] \#x_5 ;
reg si... | 7.177018 |
module cnt_attr5 (
input signed clock
, input signed [1:0] reset
, input signed [1:0] cond
, input signed [16:0] inp
, output reg signed [16:0] out
);
reg signed [1:0] t_pin9;
reg signed [16:0] \#x ;
reg signed [16:0] \#x_next ;
reg signed [16:0] t_pin40;
reg signed [16:0] \#x_5 ;
reg si... | 7.254307 |
module cnt_attr6 (
input signed clock
, input signed [1:0] reset
, input signed [1:0] cond
, input signed [16:0] inp
, output reg signed [16:0] out
);
reg signed [1:0] t_pin9;
reg signed [16:0] \#x ;
reg signed [16:0] \#x_next ;
reg signed [16:0] t_pin40;
reg signed [16:0] \#x_5 ;
reg si... | 7.102011 |
module cnt_attr7 (
input signed clock
, input signed [1:0] reset
, input signed [1:0] cond
, input signed [16:0] inp
, output reg signed [16:0] out
);
reg signed [1:0] t_pin9;
reg signed [16:0] \#x ;
reg signed [16:0] \#x_next ;
reg signed [16:0] t_pin40;
reg signed [16:0] \#x_5 ;
reg si... | 7.052406 |
module cnt_attr8 (
input signed clock
, input signed [1:0] reset
, input signed [1:0] cond
, input signed [16:0] inp
, output reg signed [16:0] out
);
reg signed [1:0] t_pin9;
reg signed [16:0] \#x ;
reg signed [16:0] \#x_next ;
reg signed [16:0] t_pin40;
reg signed [16:0] \#x_5 ;
reg si... | 7.533855 |
module cnt_block #(
parameter BLOCK_WIDTH = 2,
parameter BLOCK_IND_WIDTH = 10,
parameter BLOCK_LEVEL = -1,
parameter BLOCK_WIDTH_LOG = clogb2(BLOCK_WIDTH)
) (
input [BLOCK_IND_WIDTH*BLOCK_WIDTH-1:0] cnts_in,
output [BLOCK_IND_WIDTH+BLOCK_WIDTH_LOG-1:0] cnt_out
);
generate
if (BLO... | 7.03643 |
module clock_div_async #(
parameter cfactor = 2
) (
input clk_in,
input rst_x,
output clk_out
);
reg clk_loc;
//reg [15:0] cnt;//allowed maximum clock division factor is 65536
reg [7:0] cnt; //allowed maximum clock division factor is 256
assign clk_out = (cfactor == 1) ? clk_in : clk_loc;
... | 6.752194 |
module cnt_clock_div (
aclr,
clock,
q
);
input aclr;
input clock;
output [24:0] q;
wire [24:0] sub_wire0;
wire [24:0] q = sub_wire0[24:0];
lpm_counter LPM_COUNTER_component (
.aclr(aclr),
.clock(clock),
.q(sub_wire0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
... | 6.794777 |
module cnt_div #(
parameter DIV_CNT = 10,
parameter WIDTH = $clog2(DIV_CNT)
) (
input clk_in,
input rst_n,
output clk_out
);
reg [WIDTH-1:0] cnt;
always @(posedge clk_in or negedge rst_n) begin
if (!rst_n) cnt <= {WIDTH{1'b0}};
else if (cnt == DIV_CNT - 1) cnt <= {WIDTH{1'b0}};
... | 7.376274 |
module cnt_div_tb;
localparam DIV_CNT = 10;
reg clk_in;
reg rst_n;
wire clk_out;
cnt_div #(
.DIV_CNT(DIV_CNT)
) cnt_dut (
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out(clk_out)
);
//Clock generation
initial begin
clk_in = 0;
forever #10 clk_in = !clk_in;
end
... | 6.52461 |
module cnt_down #(
parameter BW = 'd8
) (
input RSTX,
input CLK,
input DEC,
input LOAD,
input [BW-1:0] VAL,
output CNT0,
output reg [BW-1:0] CNT,
output [BW-1:0] CNT_NEXT
);
assign CNT_NEXT = LOAD ? VAL ... | 7.287787 |
module cnt_frm (
input wire disp_clk,
input wire disp_rst,
input wire vsync,
output reg [8:0] frm_cnt
);
reg [1:0] vsync_ff;
always @(posedge disp_clk) vsync_ff <= {vsync_ff[0], vsync};
wire vsync_ff_rising = vsync_ff == 2'b01;
always @(posedge disp_clk)
if (disp_rst) frm_cnt <=... | 6.521886 |
module cnt_load #(
parameter WIDTH = 16
) (
input clk,
input rst_n,
input load,
input [WIDTH-1:0] data_load,
output reg [WIDTH-1:0] cnt
);
always @(posedge clk or negedge rst_n) begin : cnt_with_load
if (!rst_n) cnt <= {WIDTH{1'b0}};... | 8.348072 |
module cnt_load_tb;
localparam NEW_WIDTH = 16;
reg clk;
reg rst_n;
reg load;
reg [NEW_WIDTH-1:0] data_load;
wire [NEW_WIDTH-1:0] cnt;
integer i;
integer pre_delay;
integer load_width;
... | 7.339062 |
module cnt_tact #(
parameter Nt = 4
) (
input R,
input clk,
output out
);
reg [7:0] cb_tact = 0;
assign out = (cb_tact == Nt - 1);
always @(posedge clk) begin
if (R) cb_tact <= 0;
else cb_tact <= cb_tact + 1;
end
endmodule
| 8.031461 |
module cnt_test (
input clk,
input in,
input rst_n,
output [5:0] seg_sel,
output [7:0] seg_data
);
reg [31:0] timer_cnt;
reg en_1hz; //1 second , 1 counter enable
always @(posedge clk) begin
if (rst_n == 1'b0) begin
en_1hz <= 1'b0;
timer_cnt <= 32'... | 6.659939 |
module cnt_updown #(
parameter WIDTH = 16
) (
input clk,
input rst_n,
input up_down,
output reg [WIDTH-1:0] cnt
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= {WIDTH{1'b0}};
else if (up_down) cnt <= cnt + 1'b1;
els... | 8.997177 |
module cnt_wnd #(
parameter VECT_WIDTH = -1,
parameter VECT_IND_WIDTH = -1,
parameter BLOCK_WIDTH = 2
) (
input [VECT_WIDTH-1:0] vect_in,
input select_set_in,
output [VECT_IND_WIDTH-1:0] cnt_out
);
wire [VECT_WIDTH-1:0] vect_wnd_set_bits;
genvar ii;
generate
... | 6.53194 |
module cnu (
en,
clk,
rst,
q,
r
);
parameter D = 8;
parameter res_w = 8;
parameter ext_w = 3;
parameter idx_w = 3;
localparam data_w = res_w + ext_w;
input clk, rst, en;
input [data_w*D-1:0] q;
output [res_w*D-1:0] r;
wire [data_w-1:0] min, min2;
wire signed [data_w+1:0] tmin, ... | 6.862632 |
module CNU_unit (
input clk,
input rst_n,
input load_to_CNU,
input [64*(`iniBW+`exBW)*27-1:0] LLRq_in,
input [64*(`iniBW+`exBW)*27-1:0] LLRr_in,
output [64*(`iniBW+`exBW)*27-1:0] LLRq_out,
output [64*(`iniBW+`exBW)*27-1:0] LLRr_out,
output reg storage
);
reg load_to_mem, load_temp, en_... | 6.79786 |
module cnv8to24 (
//input wire clk, // pck
input wire [7:0] data8b,
input wire en,
//input wire [20:0] startaddr8b,
input wire dclk,
output reg [23:0] addr2vram = 0,
output reg [1:0] count = 0,
output reg [7:0] data_rgb, //data_r=0,data_g=0,data_b=0,
output wire wea_r,
wea_g,
... | 7.122842 |
module cnvFHC (
charIn,
nybleOut
);
input [7:0] charIn;
output [3:0] nybleOut;
parameter _0_ = 7'h30;
parameter _1_ = 7'h31;
parameter _2_ = 7'h32;
parameter _3_ = 7'h33;
parameter _4_ = 7'h34;
parameter _5_ = 7'h35;
parameter _6_ = 7'h36;
parameter _7_ = 7'h37;
parameter _8_ = 7'h38;
... | 7.555319 |
module cnvTHC (
nybleIn,
charOut
);
input [3:0] nybleIn;
output [7:0] charOut;
parameter _0_ = 8'h30;
parameter _1_ = 8'h31;
parameter _2_ = 8'h32;
parameter _3_ = 8'h33;
parameter _4_ = 8'h34;
parameter _5_ = 8'h35;
parameter _6_ = 8'h36;
parameter _7_ = 8'h37;
parameter _8_ = 8'h38;
... | 7.303419 |
module CNW (
input [ 1:0] bit_type,
input [ 2:0] DM_otype,
input [31:0] idata,
output [31:0] odata
);
// 0-LH, 1-LB, 2-LHU, 3-LBU, default-LW
assign odata = (DM_otype==3'b000)?((bit_type==0)?{{16{idata[15]}}, idata[15:0]}:(bit_type==2)?{{16{idata[31]}}, idata[31:16]}:0):
(DM_... | 6.750696 |
module cn_core (
clk,
reset_l,
s_in,
s_out,
cfg
);
parameter ADDR_WIDTH = 17;
`include "cn.vh"
`include "io_link_symbols.vh"
input clk;
input reset_l;
input [8:0] s_in;
output reg [8:0] s_out;
input [CFG_BITS-1:0] cfg; // Static configuration settings
reg init, ctrl_start;
r... | 8.009594 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module MACRO_INC (
in,
out
);
input [3:0] in;
output [3:0] out;
assign out = in + 4'd1;
endmodule
| 6.888513 |
module Coarse_Counter_22 (
input clk,
input start,
input stop,
input reset,
output reg [15:0] data
);
reg start_hold;
reg [15:0] counter;
reg set;
reg [1:0] start_flag;
reg [15:0] thanos;
// initial begin
// start_flag = 0;
// state = WAIT_FS;
// counter =... | 6.677222 |
module Coarse_Time_Synch (
input clk,
rst,
cyc_i,
input ena,
input [23:0] P_Metric_mag,
input [23:0] R_Metric,
output reg Freoff_Est_Comp_ena
);
reg frm_dec;
wire [23:0] R_Metric_thr = R_Metric >> 1;
reg [3:0] smooth_cnt;
wire frm_dec_cmp = (P_Metric_mag > R_Metric_thr) & (|R_Metric... | 7.128519 |
module cob (
input [7:0] in,
output [7:0] out
);
assign out[0] = in[1] ^ in[0] ^ in[3] ^ in[2] ^ in[7];
assign out[1] = in[1] ^ in[4] ^ in[6];
assign out[2] = in[3] ^ in[2] ^ in[7] ^ in[6];
assign out[3] = in[1] ^ in[2] ^ in[7] ^ in[6];
assign out[4] = in[3] ^ in[2] ^ in[4] ^ in[7] ^ in[6];
assign ... | 6.593678 |
module CoCoSDCExt (
input _reset,
input clock,
input [15:0] address,
output [18:14] baddress,
inout [7:0] data,
inout [7:0] bdata,
input r_w,
input _cts,
output _cts_out,
input _scs,
input _slenb,
input _rom_enable,
output _ce_flash,
output _ce_sram,
output _c... | 7.393511 |
module tb (
input clk,
input reset,
input [31:0] externalResetVector,
//input timerInterrupt,
//input externalInterrupt,
//input softwareInterrupt,
//input externalInterruptS,
output wb_i_CYC,
output ... | 6.503647 |
module that ties together the skiplist(s) and packet
* storage.
*
*/
module cocotb_tm_bp_wrapper
#(
// Pkt AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_M_AXIS_TUSER_WIDTH = 128,
parameter C_S_AXIS_TUSER_WIDTH = 128,
// ... | 6.699401 |
module that ties together the skiplist(s) and packet
* storage.
*
*/
module cocotb_tm_drop_wrapper
#(
// Pkt AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_M_AXIS_TUSER_WIDTH = 128,
parameter C_S_AXIS_TUSER_WIDTH = 128,
/... | 6.699401 |
module that ties together the skiplist(s) and packet
* storage.
*
*/
module cocotb_tm_wrapper
#(
// Pkt AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_M_AXIS_TUSER_WIDTH = 128,
parameter C_S_AXIS_TUSER_WIDTH = 128,
// max... | 6.699401 |
module Coco_Alu (
A,
B,
Ctrl,
C,
Overflow,
Compare
);
input [31:0] A, B;
input [4:0] Ctrl;
output [31:0] C;
output Overflow, Compare;
assign C = (Ctrl==`ALU_ADDU)? A + B:
(Ctrl==`ALU_ADD )? A + B:
(Ctrl==`ALU_SUBU)? A + (~B + 1):
(Ctrl==`ALU_SUB )? A +... | 7.87442 |
module Coco_Extension (
Imm16,
ExtFunct,
ExtImm32
);
input [15:0] Imm16;
input ExtFunct;
output [31:0] ExtImm32;
assign ExtImm32 = (ExtFunct == 0) ? {16'b0, Imm16} : {{16{Imm16[15]}}, Imm16};
endmodule
| 7.582346 |
module Coco_MulDiv (
input Clk,
Reset,
input [31:0] Ain,
Bin,
input Start,
MorD,
HorL,
Sign,
We,
output Ready,
output [31:0] DC
);
reg [63:0] HILO;
reg [ 5:0] count;
wire [31:0] DA, DB;
wire [63:0] BB;
assign DA = (Sign && Ain[31]) ? (~Ain) + 1 : Ain;
assign DB ... | 7.783649 |
module Coco_Mux2x1 (
In0,
In1,
Sel,
Out
);
parameter N = 1;
input [N-1:0] In0, In1;
input Sel;
output [N-1:0] Out;
assign Out = (Sel == 0) ? In0 : In1;
endmodule
| 7.250888 |
module Coco_Mux3x1 (
In0,
In1,
In2,
Sel,
Out
);
parameter N = 1;
input [N-1:0] In0, In1, In2;
input [1:0] Sel;
output [N-1:0] Out;
assign Out = (Sel == 2'b00) ? In0 : (Sel == 2'b01) ? In1 : (Sel == 2'b10) ? In2 : 1'd0;
endmodule
| 7.293486 |
module Coco_Mux4x1 (
In0,
In1,
In2,
In3,
Sel,
Out
);
parameter N = 1;
input [N-1:0] In0, In1, In2, In3;
input [1:0] Sel;
output [N-1:0] Out;
assign Out=(Sel==2'b00)?In0:
(Sel==2'b01)?In1:
(Sel==2'b10)?In2:
(Sel==2'b11)?In3:1'd0;
endmodule
| 7.110463 |
module Coco_Mux5x1 (
In0,
In1,
In2,
In3,
In4,
Sel,
Out
);
parameter N = 1;
input [N-1:0] In0, In1, In2, In3, In4;
input [2:0] Sel;
output [N-1:0] Out;
assign Out=(Sel==3'b000)?In0:
(Sel==3'b001)?In1:
(Sel==3'b010)?In2:
(Sel==3'b011)?In3:
... | 6.971985 |
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