code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Coco_Mux6x1 (
In0,
In1,
In2,
In3,
In4,
In5,
Sel,
Out
);
parameter N = 1;
input [N-1:0] In0, In1, In2, In3, In4, In5;
input [2:0] Sel;
output [N-1:0] Out;
assign Out=(Sel==3'b000)?In0:
(Sel==3'b001)?In1:
(Sel==3'b010)?In2:
(Sel==3'b011)?In... | 7.004501 |
module Coco_Mux7x1 (
In0,
In1,
In2,
In3,
In4,
In5,
In6,
Sel,
Out
);
parameter N = 1;
input [N-1:0] In0, In1, In2, In3, In4, In5, In6;
input [2:0] Sel;
output [N-1:0] Out;
assign Out=(Sel==3'b000)?In0:
(Sel==3'b001)?In1:
(Sel==3'b010)?In2:
(S... | 7.071106 |
module Coco_Shift (
input [31:0] Din,
input [ 4:0] Num,
input [ 1:0] LorR,
output [31:0] Dout
);
wire [31:0] lr, ar, ll;
assign ll = Din << Num;
assign lr = Din >> Num;
assign ar = (Din[31]) ? ~((~Din) >> Num) : Din >> Num;
assign Dout = (LorR[1]) ? ll : (LorR[0]) ? lr : ar;
endmodule... | 7.125416 |
module Coco_TC (
input Clk,
Reset,
input [1:0] Add,
input We,
input [31:0] Data_In,
output [31:0] Data_Out,
output Out
);
reg [31:0] TC [2:0];
wire [31:0] kan;
assign kan = TC[2];
assign Out=(TC[2]==32'b0 && (TC[0][2:1]==2'b01 || TC[0][2:1]==2'b00))||
((TC[2]>(TC[1]>... | 6.901305 |
module prng (
input rst_n,
input clk,
input load_seed,
input [7:0] seed_in,
input encrypt_en,
output reg [7:0] prng
);
localparam SEED = 8'hCD; // default value for the SEED
wire feedback;
assign feedback = prng[7] ^ prng[5] ^ prng[4] ^ prng[3];
always @(posedge clk or negedge rst_n)... | 7.950416 |
module bcd2seven_seg (
a,
b,
cin,
SEG_SEL,
SEG_DATA,
sel
);
input [1:0] a;
input [1:0] b;
input [1:0] sel;
input cin;
output [4:0] SEG_SEL;
output [7:0] SEG_DATA;
reg [7:0] SEG_DATA;
wire [3:0] mux_out;
always @(mux_out) begin
case (mux_out)
0: SEG_DATA = 8'b00111111... | 6.591284 |
module code2code (
input wire clk_i ,
input wire FrameValid_i ,
input wire LineValid_i ,
input wire [7:0] Y_444_i ,
input wire [7:0] U_444_i ,
input wire [7:0] V_444_i ,
output wire [7:0] Y_422_o,
output wire [7:0] UV_422_o
);
reg FrameValid;
reg LineValid;
a... | 6.767746 |
module code2digits (
input [4:0] code,
output reg [6:0] digits
);
always @(code)
case (code)
0: digits <= 7'b1111111; //nothing
1: digits <= 7'b0001001; //h
2: digits <= 7'b0000110; //e
3: digits <= 7'b1000111; //l
4: digits <= 7'b1000000; //o
5: digits <= 7'b11110... | 6.985072 |
module code3_8 (
input wire [2:0] a,
output reg [7:0] y
);
integer i;
always @(*) begin //******
for (i = 0; i < 8; i = i + 1) begin
if (a == i) y[i] <= 0;
else y[i] <= 1;
end
end
endmodule
| 7.190225 |
module coder (
input isbigger,
input wire [3:0] a,
output reg [3:0] y1,
output reg [3:0] y2
);
integer i;
always @(*) begin //******
if (isbigger == 1'b0) begin
y1 = 4'b0000;
y2 = a;
end else begin
y1 = 4'b0001;
y2 = {~a[3], ~a[2], ~a[1], a[0]};
end
end
endmodu... | 6.919428 |
module code7 (
a,
b,
cin,
cout,
carry
);
input cin;
input [3:0] a;
input [3:0] b;
wire [2:0] car;
//output cout,carry;
output [3:0] cout;
output carry;
//wire w1,w2,w3;
wire [3:0] w1;
wire [3:0] w2;
wire [3:0] w3;
xor #(10) g1 (w1[0], a[0], b[0]);
and #(5) g2 (w2[0], a[0], ... | 6.529026 |
module code8 (
a,
b,
nand_out
);
input [1:0] a;
input [1:0] b;
output [1:0] nand_out;
nand g1 (nand_out[0], b[0], a[0]);
nand g2 (nand_out[1], b[1], a[1]);
endmodule
| 6.528127 |
module code8 (
a,
b,
nand_out
);
input [1:0] a;
input [1:0] b;
output [1:0] nand_out;
nand g1 (nand_out[0], b[0], a[0]);
nand g2 (nand_out[1], b[1], a[1]);
endmodule
| 6.528127 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module codec (
clk,
rstN,
file_in,
ldN,
din,
ldN_out,
data,
coder_busy
);
input [7:0] din;
output [7:0] data;
input clk, rstN, file_in, ldN;
output ldN_out, coder_busy;
wire file_code, ldN_code, decoder_busy;
wire [8:0] code;
coder coder (
.clk(clk),
.rstN(rs... | 7.021101 |
module cntrl_coder (
clk,
rstN,
file_in,
ldN,
coder_busy,
match_det,
byte_cnt,
code_sel,
file_code,
ldN_code,
decoder_busy
);
input clk, rstN, ldN, file_in, match_det, decoder_busy;
output file_code, ldN_code, coder_busy;
output [1:0] code_sel;
output [5:0] byte_cnt;... | 6.99637 |
module coder_fsm (
clk,
rstN,
file_in,
decoder_busy,
code_out_rdy,
two_bytes_left,
code_sel,
ldN_code,
coder_busy,
clrN_cntr,
one_byte_left
);
input clk, rstN, file_in, decoder_busy, code_out_rdy;
input two_bytes_left, one_byte_left;
output ldN_code, coder_busy, clrN_c... | 8.179711 |
module decoder (
clk,
rstN,
file_code,
ldN_code,
code,
decoder_busy,
ldN_out,
data
);
input [8:0] code;
input clk, rstN, file_code, ldN_code;
output [7:0] data;
output ldN_out, decoder_busy;
reg [7:0] literal;
wire data_out_sel, ldN_data, ldN_length, ldN_addr, ldN_cam;
re... | 7.018254 |
module cntrl_decoder (
clk,
rstN,
ldN_code,
code,
ldN_data,
ldN_length,
ldN_addr,
ldN_cam,
ldN_out,
data_out_sel,
decoder_busy
);
input clk, rstN, ldN_code;
input [8:0] code;
output ldN_data, ldN_length, ldN_addr, data_out_sel, ldN_out, ldN_cam;
output decoder_busy;
... | 7.083385 |
module decoder_fsm (
clk,
rstN,
last_code_byte,
dec_length,
ldN_out,
ldN_data,
ldN_addr,
ldN_cam,
data_out_sel,
decoder_busy_fsm
);
input clk, rstN, ldN_data, ldN_addr, last_code_byte;
output dec_length, ldN_out, ldN_cam, data_out_sel, decoder_busy_fsm;
reg [1:0] decoder_... | 7.859452 |
module CodecConfigurator (
input reset,
input inClock,
inout sda,
inout scl,
output reg ready,
output reg [3:0] ackNum
);
localparam DEVICE_ADDR = 8'h34;
reg i2cClockDisable;
reg [23:0] data;
reg [2:0] state;
wire txReady, ack;
I2CMaster i2cm1 (
.reset(reset),
.inClock... | 7.880376 |
module CodeCh (
input rst_n,
input clk,
input [7:0] HI_data,
input [7:0] TONE_data,
input beat,
output reg [7:0] data
);
reg [3:0] cnt = 1;
reg sign = 0;
always@(posedge rst_n ) //ʺ
begin
sign <= 1;
end
always @(posedge ... | 7.374598 |
module bcd_to_gray (
input [3:0] bin, //binary input
output [3:0] G //gray code output
);
//xor gates.
assign G[3] = bin[3];
assign G[2] = bin[3] ^ bin[2];
assign G[1] = bin[2] ^ bin[1];
assign G[0] = bin[1] ^ bin[0];
endmodule
| 6.541222 |
module for codec
//--------------------------------------------------------------------------------
`timescale 1ns/10ps
module codectb;
reg clk, rstN, file_in, ldN;
reg [7:0] din, rd8, ref8, mem[0:4095];
wire coder_busy, ldN_out;
wire [7:0] data;
reg write_done, file_read_done;
integer i, j, ... | 6.910999 |
module codec_avalon (
clk,
reset,
slave_read,
slave_write,
slave_address,
slave_readdata,
slave_writedata,
slave_chipselect,
slave_waitrequest,
slave_beginbursttransfer,
slave_burstcount,
slave_irq,
i2c_sclk,
i2c_sdat,
adcdat,
m_clk,
b_clk,
dac_lr_... | 9.009338 |
module codec_conditioner
by David Black-Schaffer, 15 December 2006
This module interfaces to the ac97 codec module to insure that the output
does not change while new_frame is high. What it does is store the *next*
sample and output that immediately when new_frame goes high.
When new_frame goes high it... | 8.165074 |
module codec_fix_tb;
// Signals
// -------
reg clk = 1'b0;
reg rst = 1'b1;
reg go = 1'b0;
wire rdy;
// Setup recording
// ---------------
initial begin
$dumpfile("codec_fix_tb.vcd");
$dumpvars(0, codec_fix_tb);
#2000000 $finish;
end
always #10 clk <= !clk;
initial begin
... | 6.731005 |
module codec_fsm #(
parameter OVERSAMPLE = 250,
parameter DATA_WIDTH = 32,
parameter CHANNELS = 2
) (
input wire xclk_i,
input wire reset_n,
input wire signed [31:0] right_i,
input wire signed [31:0] left_i,
output wire signed [31:0] right_o,
output wire signed [31:0] left_o,
... | 7.998806 |
module: codec
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module codec_t_v;
// Inputs
reg clk;
reg clk_temp;
reg reset;
reg en;
reg [7:0] data_in;
// Outputs
wire [31:0] codes... | 6.939225 |
module top_tb ();
// ----------------------------------------------------------------------------
reg clk, rst;
// ----------------------------------------------------------------------------
wire LRCK;
wire BCLK;
wire MCLK;
wire SDTI;
wire SDTO;
wire PDN;
reg [23:0] testData;
// -------------... | 7.81622 |
module CodeMap (
rst,
clk,
din,
I,
Q
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟
input [3:0] din; //输入的绝对码数据
output [2:0] I, Q; //转换后的相对码数据
//差分编码
wire c, d;
reg Dc, Dd;
reg [3:0] code;
always @(posedge clk or posedge rst)
if (rst) begin
Dc <= 1'b0;
Dd ... | 6.685552 |
module CodeMemory_Interface (
input iCLK,
iCLKMem,
// Barramento de IO
input tri wReadEnable,
wWriteEnable,
input tri [ 3:0] wByteEnable,
input tri [31:0] wAddress,
wWriteData,
output tri [31:0] wReadData
);
BootBlock BB0 (
.address(wAddress[8:2]),
... | 7.919532 |
module CodeModem (
rst,
clk,
ab_in,
cd,
ab_out
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟
input [1:0] ab_in; //输入的绝对码数据
output [1:0] cd; //转换后的相对码数据
output [1:0] ab_out; //反转换后的绝对码数据
//实例化绝对码转相对码模块ab2cd
wire [1:0] c_d;
ab2cd u1 (
.rst(rst),
.clk(clk),
.... | 6.964216 |
module coder (
in,
out
);
// inputs
input [3:0] in;
// outputs
output [6:0] out;
// regs
reg [6:0] code;
// assigns
assign out = code;
// alphabet
always @* begin
case (in)
4'b0000: code = 7'b1000000;
4'b0001: code = 7'b1111001;
4'b0010: code = 7'b0100100;
4'... | 6.919428 |
module coder32_5 (
input [31:0] wen1_rst,
output reg [4:0] Addr,
output reg Clear_en
);
always @(wen1_rst) begin
case (wen1_rst)
32'h00000000: begin
Addr = 5'b11111;
Clear_en = 1'b0;
end
32'h00000001: begin
Addr = 5'b00000;
Clear_en = 1'b1;
end
... | 7.7615 |
module coderam #(
parameter ADDR_WIDTH = 10,
DATA_WIDTH = 64, //TODO: I might try shrinking the opcodes at some point
localparam DEPTH = 2 ** ADDR_WIDTH
) (
input wire clk,
input wire en, //Clock enable
input wire [ADDR_WIDTH-1:0] wr_addr,
input wire [DATA_WIDTH-1:0] wr_data,
input wir... | 7.024515 |
module implements the CPU6 microcode ROM.
* Microcode is loaded from a text file, which is synthesizable.
*/
module CodeROM(input wire [10:0] address, output wire [55:0] data);
reg [55:0] memory[0:2047];
initial begin
$readmemh("roms/CodeROM.txt", memory);
end
assign data = memory[address];
e... | 7.842559 |
module coder_4_2_case (
input [1:0] index,
output reg [3:0] result
);
//Load other module(s)
//Definition for Variables in the module
//Logical
always @(*) begin
case (index)
2'b00: begin
result <= 4'b0001;
end
2'b01: begin
result <= 4'b0010;
end
2'b1... | 6.765889 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-22-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-22-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-22-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module coder_mensage (
aceito,
comprometido,
rejeitado,
out
);
output [1:0] out;
input aceito, comprometido, rejeitado;
assign out[0] = comprometido;
assign out[1] = rejeitado;
endmodule
| 6.689811 |
module CODESIGN #(
parameter WL = 16
) (
input signed [WL-1:0] d,
output reg signed [1:0] codeSign
);
always @(*) begin
codeSign = d[WL-1] == 'b1 ? 'b11 : d[WL-1] == 'b0 ? 'b01 : 'bXX;
end
endmodule
| 8.637227 |
module code
//----------------------------------------------------------------
// Inherited Module Params
//----------------------------------------------------------------
#(
parameter PARAM = 0
)
//----------------------------------------------------------------
// Ports
//-------------------------------------... | 6.836249 |
module: code
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CodeTestFixture;
// Inputs
reg Clk;
reg Reset;
reg Slt;
reg En;
// Outputs
wire [63:0] Output0;
wire [63:0] Out... | 7.151791 |
module CodeTrans (
rst,
clk,
din,
di,
dq
);
input rst; //复位信号，高电平有效
input clk; //时钟信号，数据速率/采样速率/FPGA系统时钟/8 MHz
input din; //输入的二进制原始数据/2Mbps
output signed [1:0] di; //串/并变换、差分编码、插值处理后的同相信号
output signed [1:0] dq; //串/并变换、差分编码、插值处理后的正交信号
//串/并转换，2 Mbps的单比特数据转换为1 Mbps的双比特码元
reg [... | 7.941254 |
module CODEWORD #(
parameter WL = 16
) (
input signed [WL-1:0] d,
delta,
output reg codeWord
);
wire signed [WL-1:0] d_c;
TWOS_COMPLEMENT #(
.WL(WL)
) D_TC (
.original (d),
.converted(d_c)
);
always @(*) begin
if (d_c >= delta) codeWord = 1;
else codeWord = 0;
end
... | 6.88892 |
module code_box (
led,
clk,
rst,
num_led1,
num_led2,
comf,
inputt_code,
button_code,
times1,
times2,
times3
);
input [2:0] inputt_code; //输入密码的拨码
input [2:0] button_code; //输入密码的按钮
input comf; //确认键
input clk; //时钟
input rst; //复位键
output [2:0] led; //解锁指示灯
... | 6.5833 |
module ZC (
zc_CxD,
//input
data_v,
flag_band,
h0,
h1,
v0,
v1,
d0,
d1,
d2,
d3
);
output [5:0] zc_CxD;
input data_v;
input [1:0] flag_band;
input h0, h1, v0, v1, d0, d1, d2, d3;
wire [4:0] CX;
wire [5:0] zc_CxD = {CX, data_v};
wire band_eq_1 = (flag_... | 6.726247 |
module code_change (
input code,
output signed [1:0] code_o
);
assign code_o = (code == 1'b1) ? 2'b01 : 2'b11;
endmodule
| 6.757734 |
module code_converter (
output [6:0] HEX0,
HEX1,
HEX7, // 7-segment displays
input [3:0] SW, // Input switches
input [2:0] KEY // Input buttons
);
wire [6:0] disp0, disp1, disp2, disp3; // Stores the output from the differet display modules
reg [1:0] mode; // This is used to remember ... | 8.480236 |
module t_code_converter;
wire [6:0] HEX0, HEX1, HEX7; // 7-segment displays
reg [3:0] SW; // Input switches
reg [2:0] KEY; // Input buttons
integer i, j;
code_converter M1 (
.HEX0(HEX0),
.HEX1(HEX1),
.HEX7(HEX7),
.SW (SW),
.KEY (KEY)
);
initial begin
SW = 0;
K... | 7.702034 |
module bcd_2_digit (
output reg [3:0] out0,
output reg out1,
input [3:0] in
);
always @(in) begin
if (in > 9) begin
out1 = 1'b1; // Output '1' on the second display
out0 = in - 4'd10; // Subtract 10 from the value
end else begin
out1 = 1'b0; // Output '0' on the second displa... | 7.012243 |
module bcd_1_digit (
output reg [3:0] out,
input [3:0] in
);
always @(in) begin
if (in > 9) out = 9; // Show '9' if the value is above 9
else out = in; // Output the input directly on the display
end
endmodule
| 6.894475 |
module display_driver (
output reg [6:0] out,
input [3:0] in
);
always @(in) begin
case (in)
4'b0000: out = 7'b1000000; // 0
4'b0001: out = 7'b1111001; // 1
4'b0010: out = 7'b0100100; // 2
4'b0011: out = 7'b0110000; // 3
4'b0100: out = 7'b0011001; // 4
4'b0101: ou... | 6.908978 |
module code_estimator #(
parameter BPS = 12,
parameter Z_IBITS = 4,
parameter Z_FBITS = 4,
parameter Z_NBITS = Z_IBITS + Z_FBITS
) (
input wire [(BPS*Z_NBITS)-1:0] z,
output reg [BPS-1:0] v_hat
);
integer i;
always @(*) begin
// If the value of z is greater than zero, the correspondin... | 8.615227 |
module cam (
clk, // Cam clock
cam_enable, // Cam enable
cam_data_in, // Cam data to match
cam_hit_out, // Cam match has happened
cam_addr_out // Cam output address
);
parameter ADDR_WIDTH = 8;
parameter DEPTH = 1 << ADDR_WIDTH;
//------------Input Ports--------------
input clk;
inp... | 6.732588 |
module clk_div (
clk_in,
enable,
reset,
clk_out
);
// --------------Port Declaration-----------------------
input clk_in;
input reset;
input enable;
output clk_out;
//--------------Port data type declaration-------------
wire clk_in;
wire enable;
//--------------Internal Registers----... | 7.520262 |
module clk_div_45 (
clk_in, // Input Clock
enable, // Enable is sync with falling edge of clk_in
clk_out // Output Clock
);
// --------------Port Declaration-----------------------
input clk_in;
input enable;
output clk_out;
//--------------Port data type declaration-------------
wire ... | 6.661732 |
module decoder_2to4_gates (
x,
y,
f0,
f1,
f2,
f3
);
input x, y;
output f0, f1, f2, f3;
wire n1, n2;
not i1 (n1, x);
not i2 (n2, y);
and a1 (f0, n1, n2);
and a2 (f1, n1, y);
and a3 (f2, x, n2);
and a4 (f3, x, y);
endmodule
| 6.936735 |
module decoder_using_assign (
binary_in, // 4 bit binary input
decoder_out, // 16-bit out
enable // Enable for the decoder
);
input [3:0] binary_in;
input enable;
output [15:0] decoder_out;
wire [15:0] decoder_out;
assign decoder_out = (enable) ? (1 << binary_in) : 16'b0;
endmodule
| 7.196438 |
module decoder_using_case (
binary_in, // 4 bit binary input
decoder_out, // 16-bit out
enable // Enable for the decoder
);
input [3:0] binary_in;
input enable;
output [15:0] decoder_out;
reg [15:0] decoder_out;
always @(enable or binary_in) begin
decoder_out = 0;
if (enable) begi... | 7.196438 |
module dff_async_reset (
data, // Data Input
clk, // Clock Input
reset, // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------... | 7.171044 |
module dff_sync_reset (
data, // Data Input
clk, // Clock Input
reset, // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Co... | 6.82334 |
module d_ff_gates (
d,
clk,
q,
q_bar
);
input d, clk;
output q, q_bar;
wire n1, n2, n3, q_bar_n;
wire cn, dn, n4, n5, n6;
// First Latch
not (n1, d);
nand (n2, d, clk);
nand (n3, n1, clk);
nand (dn, q_bar_n, n2);
nand (q_bar_n, dn, n3);
// Second Latch
not (cn, clk);
not ... | 7.466829 |
module d_latch_gates (
d,
clk,
q,
q_bar
);
input d, clk;
output q, q_bar;
wire n1, n2, n3;
not (n1, d);
nand (n2, d, clk);
nand (n3, n1, clk);
nand (q, q_bar, n2);
nand (q_bar, q, n3);
endmodule
| 7.691161 |
module encoder_4to2_gates (
i0,
i1,
i2,
i3,
y
);
input i0, i1, i2, i3;
output [1:0] y;
or o1 (y[0], i1, i3);
or o2 (y[1], i2, i3);
endmodule
| 6.823538 |
module full_adder_gates (
x,
y,
z,
sum,
carry
);
input x, y, z;
output sum, carry;
wire and1, and2, and3, sum1;
and U_and1 (and1, x, y), U_and2 (and2, x, z), U_and3 (and3, y, z);
or U_or (carry, and1, and2, and3);
xor U_sum (sum, x, y, z);
endmodule
| 8.163448 |
module full_subtracter_gates (
x,
y,
z,
difference,
borrow
);
input x, y, z;
output difference, borrow;
wire inv_x, borrow1, borrow2, borrow3;
not (inv_x, x);
and U_borrow1 (borrow1, inv_x, y), U_borrow2 (borrow2, inv_x, z), U_borrow3 (borrow3, y, z);
xor U_diff (difference, borrow1, ... | 8.333169 |
module GrayCounter #(
parameter COUNTER_WIDTH = 4
) (
output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk
);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1... | 7.225923 |
module gray_counter (
out, // counter out
enable, // enable for counter
clk, // clock
rst // active hight reset
);
//------------Input Ports--------------
input clk, rst, enable;
//----------Output Ports----------------
output [7:0] out;
//------------Internal Variables--------
wire [7:... | 6.858216 |
module half_adder_gates (
x,
y,
sum,
carry
);
input x, y;
output sum, carry;
and U_carry (carry, x, y);
xor U_sum (sum, x, y);
endmodule
| 7.281438 |
module lfsr (
out, // Output of the counter
enable, // Enable for counter
clk, // clock input
reset // reset input
);
//----------Output Ports--------------
output [7:0] out;
//------------Input Ports--------------
input enable, clk, reset;
//------------Internal Variables--------
reg ... | 6.692777 |
module mux_2to1_gates (
a,
b,
sel,
y
);
input a, b, sel;
output y;
wire sel, a_sel, b_sel;
not U_inv (inv_sel, sel);
and U_anda (asel, a, inv_sel), U_andb (bsel, b, sel);
or U_or (y, asel, bsel);
endmodule
| 7.411574 |
module mux_using_assign (
din_0, // Mux first input
din_1, // Mux Second input
sel, // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
... | 7.675569 |
module mux_using_case (
din_0, // Mux first input
din_1, // Mux Second input
sel, // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
re... | 6.739844 |
module mux_using_if (
din_0, // Mux first input
din_1, // Mux Second input
sel, // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
reg ... | 7.170064 |
module one_hot_cnt (
out, // Output of the counter
enable, // enable for counter
clk, // clock input
reset // reset input
);
//----------Output Ports--------------
output [7:0] out;
//------------Input Ports--------------
input enable, clk, reset;
//------------Internal Variables--------... | 6.95926 |
module parity_using_assign (
data_in, // 8 bit data in
parity_out // 1 bit parity out
);
output parity_out;
input [7:0] data_in;
wire parity_out;
assign parity_out = (data_in[0] ^ data_in[1]) ^
(data_in[2] ^ data_in[3]) ^
(data_in[4] ^ data_in[5]) ^
... | 7.821962 |
module parity_using_bitwise (
data_in, // 8 bit data in
parity_out // 1 bit parity out
);
output parity_out;
input [7:0] data_in;
assign parity_out = ^data_in;
endmodule
| 7.821962 |
module parity_using_function (
data_in, // 8 bit data in
parity_out // 1 bit parity out
);
output parity_out;
input [7:0] data_in;
wire parity_out;
function parity;
input [31:0] data;
begin
parity = (data_in[0] ^ data_in[1]) ^
(data_in[2] ^ data_in[3]) ^
... | 7.821962 |
module pri_encoder_using_assign (
binary_out, // 4 bit binary output
encoder_in, // 16-bit input
enable // Enable for the encoder
);
output [3:0] binary_out;
input enable;
input [15:0] encoder_in;
wire [3:0] binary_out;
assign binary_out = (!enable) ? 0 : (
(encoder_in == 16'bxxxx_... | 7.346021 |
module rom_using_case (
address, // Address input
data, // Data output
read_en, // Read Enable
ce // Chip Enable
);
input [3:0] address;
output [7:0] data;
input read_en;
input ce;
reg [7:0] data;
always @(ce or read_en or address) begin
case (address)
0: data = 10;
1... | 6.606049 |
module serial_crc_ccitt (
clk,
reset,
enable,
init,
data_in,
crc_out
);
//-----------Input Ports---------------
input clk;
input reset;
input enable;
input init;
input data_in;
//-----------Output Ports---------------
output [15:0] crc_out;
//------------Internal Variables-----... | 7.23712 |
module tff_async_reset (
data, // Data Input
clk, // Clock Input
reset, // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code... | 6.8872 |
module uart (
reset,
txclk,
ld_tx_data,
tx_data,
tx_enable,
tx_out,
tx_empty,
rxclk,
uld_rx_data,
rx_data,
rx_enable,
rx_in,
rx_empty
);
// Port declarations
input reset;
input txclk;
input ld_tx_data;
input [7:0] tx_data;
input tx_enable;
output tx_out;... | 7.996353 |
module up_counter (
out, // Output of the counter
enable, // enable for counter
clk, // clock Input
reset // reset Input
);
//----------Output Ports--------------
output [7:0] out;
//------------Input Ports--------------
input enable, clk, reset;
//------------Internal Variables--------
... | 6.762135 |
module up_counter_load (
out, // Output of the counter
data, // Parallel load for the counter
load, // Parallel load enable
enable, // Enable counting
clk, // clock input
reset // reset input
);
//----------Output Ports--------------
output [7:0] out;
//------------Input Ports-------... | 6.791177 |
module up_down_counter (
out, // Output of the counter
up_down, // up_down control for counter
clk, // clock input
reset // reset input
);
//----------Output Ports--------------
output [7:0] out;
//------------Input Ports--------------
input up_down, clk, reset;
//------------Internal Var... | 7.520907 |
module code_hold (
clk,
rst_n,
hold,
datain,
dataout
);
input clk, rst_n, hold;
input [31:0] datain;
output [31:0] dataout;
reg [31:0] dataout;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dataout <= 32'd0;
end else begin
if (hold == 1'b1) begin
... | 6.879503 |
module codemem (
input cs_code_mem,
clk,
rst,
input [7:0] pc,
output reg rdy_code_mem,
output reg [7:0] pc_data
);
reg [7:0] code_memo[0:(2**8-1)];
reg [7:0] state;
always @(posedge clk) begin
if (rst) begin
state = 0;
rdy_code_mem = 1'b1;
code_memo[0] = {8'b01000000... | 6.998629 |
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