code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module code_mt (
clk,
rst_n,
SigA,
SigB,
Start,
Clr,
Dout,
DoutM
);
input clk, rst_n, SigA, SigB, Start, Clr;
output [31:0] Dout, DoutM;
reg [31:0] Dout, DoutM;
reg [31:0] Dout1;
reg [31:0] count, countreg, count1, countreg1;
reg LastSigA, LastSigB;
reg ClkOut, DirOut, preD... | 7.008084 |
module branch_decode1 (
branch,
morethree,
fmulovf,
rsge64,
absign,
addsub,
manzero,
rs32,
eadd,
amsb,
rem_op,
qmsb,
a2func,
romselp_a
);
output romselp_a;
input [3:0] branch;
input morethree, fmulovf, rsge64, absign, addsub, manzero, rs32, eadd, amsb, rem_... | 6.613679 |
module branch_decode2 (
branch,
morethree,
fmulovf,
rsge64,
absign,
addsub,
manzero,
rs32,
eadd,
amsb,
rem_op,
qmsb,
a2func,
romselp_b
);
output romselp_b;
input [3:0] branch;
input morethree, fmulovf, rsge64, absign, addsub, manzero, rs32, eadd, amsb, rem_... | 6.613679 |
module branch_decode3 (
branch,
morethree,
fmulovf,
rsge64,
absign,
addsub,
manzero,
rs32,
eadd,
amsb,
rem_op,
qmsb,
a2func,
romselp_c
);
output romselp_c;
input [3:0] branch;
input morethree, fmulovf, rsge64, absign, addsub, manzero, rs32, eadd, amsb, rem_... | 6.613679 |
module branch_decode4 (
branch,
morethree,
fmulovf,
rsge64,
absign,
addsub,
manzero,
rs32,
eadd,
amsb,
rem_op,
qmsb,
a2func,
romselp_d
);
output romselp_d;
input [3:0] branch;
input morethree, fmulovf, rsge64, absign, addsub, manzero, rs32, eadd, amsb, rem_... | 6.613679 |
module code_sound (
idle,
clk_50Mhz,
code,
sound
);
input wire [7:0] code;
input wire clk_50Mhz;
input wire idle;
output reg [12:0] sound;
reg [7:0] key_control;
reg count;
initial begin
count <= 0;
key_control <= 0;
sound <= 0;
end
reg [7:0] prev_code;
reg [7:0] p... | 6.546598 |
module switch_fabric (
clk,
reset,
data_in0,
data_in1,
data_in2,
data_in3,
data_in4,
data_in5,
data_in_valid0,
data_in_valid1,
data_in_valid2,
data_in_valid3,
data_in_valid4,
data_in_valid5,
data_out0,
data_out1,
data_out2,
data_out3,
data_out4... | 6.929567 |
module switch (
clk,
reset,
data_in,
data_in_valid,
data_out,
data_out_ack
);
input clk;
input reset;
input [7:0] data_in;
input data_in_valid;
output [7:0] data_out;
output data_out_ack;
reg [7:0] data_out;
reg data_out_ack;
always @(posedge clk)
if (reset) begin
... | 6.864438 |
module code_stream (
clk,
reset,
en_regular,
en_run_1,
en_run_2,
k_run,
k_regular,
MErrval_run,
MErrval_regular,
glimit_run,
codes_r,
codes_r_len,
//output
codes,
en_out,
cod_32,
len_32
);
input clk, reset, en_regular, en_run_1, en_run_2;
input... | 6.663247 |
module: code
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module code_tb;
// Inputs
reg Clk;
reg Reset;
reg Slt;
reg En;
// Outputs
wire [63:0] Output0;
wire [63:0] Output1;
... | 7.151791 |
module asyn_reset (
clk,
reset,
a,
c
);
input clk;
input reset;
input a;
output c;
wire clk;
wire reset;
wire a;
reg c;
always @(posedge clk or posedge reset)
if (reset == 1'b1) begin
c <= 0;
end else begin
c <= a;
end
endmodule
| 7.114107 |
module blocking (
clk,
a,
c
);
input clk;
input a;
output c;
wire clk;
wire a;
reg c;
reg b;
always @(posedge clk) begin
b = a;
c = b;
end
endmodule
| 6.914027 |
module fsm_using_always (
clock, // clock
reset, // Active high, syn reset
req_0, // Request 0
req_1, // Request 1
gnt_0, // Grant 0
gnt_1
);
//-------------Input Ports-----------------------------
input clock, reset, req_0, req_1;
//-------------Output Ports--------------------------... | 8.167475 |
module fsm_using_function (
clock, // clock
reset, // Active high, syn reset
req_0, // Request 0
req_1, // Request 1
gnt_0, // Grant 0
gnt_1
);
//-------------Input Ports-----------------------------
input clock, reset, req_0, req_1;
//-------------Output Ports------------------------... | 8.965415 |
module fsm_using_single_always (
clock, // clock
reset, // Active high, syn reset
req_0, // Request 0
req_1, // Request 1
gnt_0, // Grant 0
gnt_1
);
//=============Input Ports=============================
input clock, reset, req_0, req_1;
//=============Output Ports===================... | 6.934766 |
module nonblocking (
clk,
a,
c
);
input clk;
input a;
output c;
wire clk;
wire a;
reg c;
reg b;
always @(posedge clk) begin
b <= a;
c <= b;
end
endmodule
| 7.775492 |
module reg_combo_example (
a,
b,
y
);
input a, b;
output y;
reg y;
wire a, b;
always @(a or b) begin
y = a & b;
end
endmodule
| 6.821972 |
module reg_seq_example (
clk,
reset,
d,
q
);
input clk, reset, d;
output q;
reg q;
wire clk, reset, d;
always @(posedge clk or posedge reset)
if (reset) begin
q <= 1'b0;
end else begin
q <= d;
end
endmodule
| 7.344106 |
module syn_reset (
clk,
reset,
a,
c
);
input clk;
input reset;
input a;
output c;
wire clk;
wire reset;
wire a;
reg c;
always @(posedge clk)
if (reset == 1'b1) begin
c <= 0;
end else begin
c <= a;
end
endmodule
| 6.521313 |
module wire_example (
a,
b,
y
);
input a, b;
output y;
wire a, b, y;
assign y = a & b;
endmodule
| 6.729577 |
module code_translate (
input clk,
input [3:0] code,
output new_code,
output is_floor // Flag to show if it is a floor dir
);
reg [2:0] floor_req; // floor(2bit) + up/down(1bit)
reg [2:0] elevr_req; // flor(2bit) + ascensor 1bit
reg flr_req = 1'b0; // 1 si es una floor request, 0 si es elevato... | 6.75435 |
module addbit (
a, // first input
b, // Second input
ci, // Carry input
sum, // sum output
co // carry output
);
//Input declaration
input a;
input b;
input ci;
//Ouput declaration
output sum;
output co;
//Port Data types
wire a;
wire b;
wire ci;
wire sum;
wire co;
/... | 7.120785 |
module bus_con (
a,
b,
y
);
input [3:0] a, b;
output [7:0] y;
wire [7:0] y;
assign y = {a, b};
endmodule
| 7.30857 |
module addbit (
a,
b,
ci,
sum,
co
);
// Input Ports Single line comment
input a;
input b;
input ci;
// Output ports
output sum;
output co;
// Data Types
wire a;
wire b;
wire ci;
wire sum;
wire co;
endmodule
| 7.120785 |
module testbench;
integer file;
reg clk = 0, reset = 0, enable = 0;
wire [3:0] count;
reg dut_error = 0;
counter U0 (
.clk (clk),
.reset (reset),
.enable(enable),
.count (count)
);
event reset_enable;
event terminate_sim;
initial file = $fopen(`outfile);
always #5 clk ... | 7.015571 |
module decoder (
in,
out
);
input [2:0] in;
output [7:0] out;
wire [7:0] out;
assign out = (in == 3'b000 ) ? 8'b0000_0001 :
(in == 3'b001 ) ? 8'b0000_0010 :
(in == 3'b010 ) ? 8'b0000_0100 :
(in == 3'b011 ) ? 8'b0000_1000 :
(in == 3'b100 ) ? 8'b0001_0000 :
(in == 3'b101 ) ? 8'b0010_0000 :
(in ==... | 7.018254 |
module decoder_always (
in,
out
);
input [2:0] in;
output [7:0] out;
reg [7:0] out;
always @(in) begin
out = 0;
case (in)
3'b001: out = 8'b0000_0001;
3'b010: out = 8'b0000_0010;
3'b011: out = 8'b0000_0100;
3'b100: out = 8'b0000_1000;
3'b101: out = 8'b0001_0000;
... | 8.054186 |
module d_ff (
d,
clk,
q,
q_bar
);
input d, clk;
output q, q_bar;
wire d, clk;
reg q, q_bar;
always @(posedge clk) begin
q <= d;
q_bar <= !d;
end
endmodule
| 7.640793 |
module \1dff (
q, // Q output
\q~ , // Q_out output
d, // D input
cl$k, // CLOCK input
\reset* // Reset input
);
input d, cl$k, \reset* ;
output q, \q~ ;
endmodule
| 7.062834 |
module dff (
q,
q_bar,
clk,
d,
rst,
pre
);
input clk, d, rst, pre;
output q, q_bar;
reg q;
assign q_bar = ~q;
always @(posedge clk)
if (rst == 1'b1) begin
q <= 0;
end else if (pre == 1'b1) begin
q <= 1;
end else begin
q <= d;
end
endmodule
| 8.035763 |
module first_counter (
clock, // Clock input of the design
reset, // active high, synchronous Reset input
enable, // Active high enable signal for counter
counter_out // 4 bit vector output of the counter
); // End of port list
//-------------Input Ports-----------------------------
input clock... | 6.853723 |
module flif_flop (
clk,
reset,
q,
d
);
input clk, reset, d;
output q;
reg q;
always @(posedge clk) begin
if (reset == 1) begin
q <= 0;
end else begin
q <= d;
end
end
endmodule
| 6.595577 |
module fsm_full (
clock, // Clock
reset, // Active high reset
req_0, // Active high request from agent 0
req_1, // Active high request from agent 1
req_2, // Active high request from agent 2
req_3, // Active high request from agent 3
gnt_0, // Active high grant to agent 0
gnt_1, ... | 8.949275 |
module addbit (
a,
b,
ci,
sum,
co
);
input a;
input b;
input ci;
output sum;
output co;
wire a;
wire b;
wire ci;
wire sum;
wire co;
endmodule
| 7.120785 |
module if_else ();
reg dff;
wire clk, din, reset;
always @(posedge clk)
if (reset) begin
dff <= 0;
end else begin
dff <= din;
end
endmodule
| 6.827631 |
module muliply (
a,
product
);
input [3:0] a;
output [4:0] product;
wire [4:0] product;
assign product = a << 1;
endmodule
| 6.552831 |
module mux_21 (
a,
b,
sel,
y
);
input a, b;
output y;
input sel;
wire y;
assign y = (sel) ? b : a;
endmodule
| 8.119254 |
module n_out_primitive ();
wire out, out_0, out_1, out_2, out_3, out_a, out_b, out_c;
wire in;
// one output Buffer gate
buf u_buf0 (out, in);
// four output Buffer gate
buf u_buf1 (out_0, out_1, out_2, out_3, in);
// three output Invertor gate
not u_not0 (out_a, out_b, out_c, in);
endmodule
| 7.329419 |
module port connection are done
// Coder : Deepak
//-----------------------------------------------------
module parity (
a , // First input
b , // Second input
c , // Third Input
d , // Fourth Input
y // Parity output
);
// Input Declaration
input a ;
input b ... | 8.460347 |
module simple_function ();
function myfunction;
input a, b, c, d;
begin
myfunction = ((a + b) + (c - d));
end
endfunction
endmodule
| 6.540619 |
module simple_if ();
reg latch;
wire enable, din;
always @(enable or din)
if (enable) begin
latch <= din;
end
endmodule
| 6.709566 |
module tri_buf (
a,
b,
enable
);
input a;
output b;
input enable;
wire b;
assign b = (enable) ? a : 1'bz;
endmodule
| 7.410938 |
module which_clock (
x,
y,
q,
d
);
input x, y, d;
output q;
reg q;
always @(posedge x or posedge y)
if (x) q <= 1'b0;
else q <= d;
endmodule
| 6.922689 |
module CodNormal (
output wire [1:0] valor,
input wire [3:0] a
);
nor (valor[1], a[0], a[1]);
nor (valor[0], a[0], a[2]);
endmodule
| 6.584096 |
module CodPrioridad (
output wire [1:0] valor,
input wire [3:0] a
);
wire ns, as;
not (ns, a[2]);
and (as, a[1], ns);
or (valor[1], a[2], a[3]);
or (valor[0], a[3], as);
endmodule
| 6.805759 |
module Codifica_Corriente (
input [4:0] Corriente,
output reg [3:0] Un,
output reg [3:0] De,
output reg [3:0] Ce,
output reg [3:0] Mi
);
always @* begin
case (Corriente)
//Con Corriente = 000 el numero a mostrar es 0.
5'b00000: begin
Un <= 4'b0000;
De <= 4'b1010; ... | 7.477898 |
module Codifica_Frecuencia (
input [2:0] Frec,
output reg [3:0] Un,
output reg [3:0] De,
output reg [3:0] Ce,
output reg [3:0] Mi
);
always @* begin
case (Frec)
//Con Frec = 000 el numero a mostrar es 30.
3'b000: begin
Un <= 4'b0000;
De <= 4'b0011;
Ce <= 4... | 7.594743 |
module: coding
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module coding_test;
// Inputs
reg CLK;
reg nRST;
// Outputs
wire [7:0] DATA_OUT;
// Instantiate the Unit Under Test (... | 6.525545 |
module zero_coding (
input clk,
input rstn,
input [1:0] band,
input h0,
h1,
v0,
v1,
input d0,
d1,
d2,
d3,
input d,
output reg [4:0] ctx,
output reg q
);
wire band_eq_1 = (band == 1);
wire band_... | 7.051632 |
module sign_coding (
input clk,
input rstn,
input h0,
h1,
v0,
v1,
input sign_h0,
sign_h1,
sign_v0,
sign_v1,
input d,
output reg [4:0] ctx,
output reg q
);
reg [1:0] h_contri;
reg [1:0] v_contri;
alway... | 6.610835 |
module mrc (
input clk,
input rstn,
input h0,
h1,
v0,
v1,
input d0,
d1,
d2,
d3,
input first_time,
input d,
output reg q,
output reg [4:0] ctx
);
wire all = h0 | h1 | v0 | v1 | d0 | d1 | d2 | d3;
always @(`CLK_RST_EDGE)
if (`RST) ctx <= 0;
els... | 7.172028 |
module Cod_Display (
input wire [2:0] Frecuencia,
input wire [4:0] Corriente,
input wire Sel,
output wire [3:0] Uni,
output wire [3:0] Dec,
output wire [3:0] Cen,
output wire [3:0] Mil
);
//////////////////////////////Seccion Codificadores///////////////////////////////
wire [3:0] Un_F... | 8.63854 |
module coefCal (
clk,
rst,
en,
xBgn,
xEnd,
yBgn,
yEnd,
inXRes,
inYRes,
outXRes,
outYRes,
kX,
kY,
inEn,
iVsyn
);
parameter INPUT_RES_WIDTH = 11;
parameter OUTPUT_RES_WIDTH = 11;
parameter SCALE_BITS = 8;
//-------------Module IO------------------------... | 7.254689 |
module coefficient_encoder (
input signed [15:0] coefficient,
output reg [15:0] coded_value,
output reg [3:0] coded_value_length
);
reg [15:0] absolute_value;
always @* begin
absolute_value = (coefficient[15] == 1'b1) ? (-coefficient) : (coefficient);
end
integer i;
always @* begin
if (a... | 6.762391 |
module coefficient_encoder_testbench;
reg signed [15:0] coefficient;
wire [15:0] coded_value;
wire [ 3:0] coded_value_length;
coefficient_encoder ce (
.coefficient(coefficient),
.coded_value(coded_value),
.coded_value_length(coded_value_length)
);
initial begin
$dumpfile(... | 6.762391 |
module implements a 7*7 register file that's used
to load up the necessary coefficents for filters.
........................
By: Abdullah Al-Dujaili
NTU, 2012
........................
*/
module coefficient_file
#(
parameter COFCNT_BIT=16, // # coefficient bit
MASK_WIDTH=7 // mask width
)
... | 6.904081 |
module coeff_3 (
datain,
dataout
);
input [19:0] datain;
output [19:0] dataout;
assign dataout = (datain>>10) + (datain>>12) + (datain>>13) + (datain>>14) + (datain>>17) +(datain>>18) + (datain>>20);
endmodule
| 6.999825 |
module coeff_32x512 (
clk,
cen_i,
oen_i,
wen_i,
addr_i,
data_i,
data_o
);
// ********************************************
//
// Input/Output DECLARATION
//
// ********... | 7.290284 |
module coeff_decomposer (
input rst,
input clk,
input valid_i,
output ready_i,
input [ 2:0] sec_lvl,
input [23:0] di,
output reg [23:0] doa = 0,
output reg [23:0] dob = 0,
output reg valid_o = 0,
input re... | 6.703591 |
module coeff_decomposer_tb;
reg rst;
reg clk;
reg valid_i;
reg ready_o;
reg [2:0] sec_lvl;
reg [23:0] di;
wire [23:0] doa = 0;
wire [23:0] dob = 0;
wire valid_o = 0;
wire ready_i;
parameter SEC_LVL_0 = 3'b000;
parameter SEC_LVL_2 = 3'b010;
parameter OUTPUT_W = 4;
parameter COEFF_W = 24;
... | 6.703591 |
module coeff_memory (
input wire write_enable,
read_enable,
Sclk,
input wire [15:0] in_data,
input wire [8:0] coeffwrite,
coeffread,
output wire [15:0] data_coeff
);
reg [15:0] coeffmem[0:511];
always @(posedge Sclk) begin
if (write_enable == 1'b1) coeffmem[coeffwrite] = in_data;
... | 6.757539 |
module coeff_ram (
input clock,
input [3:0] rd_addr,
output reg [15:0] rd_data
);
always @(posedge clock)
case (rd_addr)
4'd0: rd_data <= #1 -16'd16;
4'd1: rd_data <= #1 16'd74;
4'd2: rd_data <= #1 -16'd254;
4'd3: rd_data <= #1 16'd669;
4'd4: rd_data <= #1 -16'd1468;
... | 7.328273 |
module coeff_rom (
input clock,
input [2:0] addr,
output reg [15:0] data
);
always @(posedge clock)
case (addr)
3'd0: data <= #1 -16'd49;
3'd1: data <= #1 16'd165;
3'd2: data <= #1 -16'd412;
3'd3: data <= #1 16'd873;
3'd4: data <= #1 -16'd1681;
3'd5: data <= #1 16'... | 7.054666 |
module(s) does this file instantiate?
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module Coeff_token_enc(
clk,
rst_n,
state,
NC,
TrailOneNum,
TotalCoeff,
CodeBit,
CodeL... | 9.060532 |
module(s) does this file instantiate?
//
// $Id$
//-------------------------------------------------------------------
//VLC0
`include "enc_defines.v"
module Coeff_token_vlc0(
addr,
vlc_code
);
input [5:0] addr;
output reg [7:0] vlc_code;
always @(*)begin
case(addr)
6'd 0: vlc_code... | 9.060532 |
module(s) does this file instantiate?
//
// $Id$
//-------------------------------------------------------------------
//VLC1
`include "enc_defines.v"
module Coeff_token_vlc1(
addr,
vlc_code
);
input [5:0] addr;
output reg [7:0] vlc_code;
always @(*) begin
case(addr)
6'd 0: vlc_code... | 9.060532 |
module(s) does this file instantiate?
//
// $Id$
//-------------------------------------------------------------------
//VLC2
`include "enc_defines.v"
module Coeff_token_vlc2(
addr,
vlc_code
);
input [5:0] addr;
output reg [7:0] vlc_code;
always @(*)begin
case(addr)
6'd 0: vlc_code... | 9.060532 |
module(s) does this file instantiate?
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module Coeff_token_vlc_chromaDC(
addr,
vlc_code
);
input [3:0] addr;
output reg [5:0] vlc_code;
always @(*)begin
case(addr)
4'd0 : vlc_code ... | 9.060532 |
module coef_term1 (
in,
out
);
parameter DWIDTH = 32;
parameter t01 = 32'b0000_0000_1000_0000_0000_0000_0000_0000;
parameter t12 = 32'b0000_0000_1101_0001_0100_0000_0000_0000;
parameter t23 = 32'b0000_0000_1110_1100_1000_0000_0000_0000;
parameter t34 = 32'b0000_0000_1111_1000_0100_0000_0000_0000;
... | 6.963196 |
module coef_term2 (
in,
out
);
parameter DWIDTH = 32;
parameter t01 = 32'b0000_0000_0100_0000_0000_0000_0000_0000;
parameter t12 = 32'b0000_0000_0010_0110_0000_0000_0000_0000;
parameter t23 = 32'b0000_0000_0001_0001_1100_0000_0000_0000;
parameter t34 = 32'b0000_0000_0000_0111_0100_0000_0000_0000;
... | 7.017074 |
module coef_term3 (
in,
out
);
parameter DWIDTH = 32;
parameter t01 = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
parameter t12 = 32'b1111_1111_1111_0100_0000_0000_0000_0000;
parameter t23 = 32'b1111_1111_1111_1000_1000_0000_0000_0000;
parameter t34 = 32'b1111_1111_1111_1100_1100_0000_0000_0000;
... | 7.423713 |
module coe_display (
input clk,
input rst_n,
input [10:0] h_cnt,
input [10:0] v_cnt,
input [11:0] data_in,
input [10:0] H_VISIBLE,
input [10:0] H_BACK_PORCH,
input [10:0] V_VISIBLE,
input [10:0] V_BACK_PORCH,
output reg [16:0] data_addr,
output [3:0] o_r,
output [3:0] o_g... | 8.179707 |
module coe_in_ram (
clk,
wen,
waddr,
raddr,
wdat,
rdat
);
// parameter DWIDTH = 256 ;
parameter DWIDTH = 160;
// parameter AWIDTH = 13 ;
parameter AWIDTH = 10;
// parameter WORDS = 8192 ;
parameter WORDS = 1024;
input clk, wen;
input [AWIDTH-1:0] waddr, raddr;
input [DWID... | 7.440692 |
module coe_out_ram (
clk,
wen,
waddr,
raddr,
wdat,
rdat
);
// parameter DWIDTH = 256 ;
parameter DWIDTH = 160;
// parameter AWIDTH = 15 ;
// parameter WORDS = 32768 ;
parameter AWIDTH = 10;
parameter WORDS = 1024;
input clk, wen;
input [AWIDTH-1:0] waddr, raddr;
input [DW... | 8.00829 |
module cof (
clk,
en,
reset,
Wn_in,
AncEn,
Rn,
Wn_out,
Mu
);
parameter W1 = 24, //input/output bit width
W2 = 4, W3 = 22; //coefficient bit width
input en, reset, clk;
input [W1-1:0] Wn_in, AncEn, Rn;
input [W2-1:0] Mu;
output [W1-1:0] Wn_out;
wire [W1-1:0] Wn_in, AncEn... | 7.997472 |
module coffCulate #(
parameter SYM_WIDTH = 1,
parameter INT_WIDTH = 2,
parameter DEC_WIDTH = 5
) (
input wire signed [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] uk,
input wire signed [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] BufferQ1,
BufferQ2,
BufferQ3,
BufferQ4,
input wire signed [SYM_WIDTH+... | 6.644693 |
module COFFEE (
input CLOCK_50,
output [9:0] LEDG,
output [6:0] HEX0_D,
output [6:0] HEX1_D,
output [6:0] HEX2_D,
output [6:0] HEX3_D,
input [2:0] BUTTON
);
wire [11:0] instructionAddress;
wire [31:0] instruction;
wire [13:0] dataAddress;
wire [31:0] writeData;
wire [31:0] readDat... | 6.768416 |
module cog_ram (
input clk,
input ena,
input w,
input [8:0] a,
input [31:0] d,
output reg [31:0] q
);
// 512 x 32 ram
reg [511:0][31:0] r;
always @(posedge clk) begin
if (ena && w) r[a] <= d;
if (ena) q <= r[a];
end
endmodule
| 6.715089 |
module cog_vid (
input clk_cog,
input clk_vid,
input ena,
input setvid,
input setscl,
input [31:0] data,
input [31:0] pixel,
input [31:0] color,
input [7:0] aural,
input carrier,
output ack,
output [31:0] pin_out
);
// configuration
reg [31:0] vid;
reg... | 6.848332 |
module: BkfOfIDetector
// Desc: determine BktOfI and manipulate valid bits
//==============================================================================
module BkfOfIDetector (Enable, AddrOfI, DataIn, DataOut, DataOfI, Detect);
parameter DWidth = 512;
parameter ValidBitStart = 1, ValidBitEnd = 5;
parameter... | 7.960592 |
module Coherence_Bus_Arbiter (
clk,
request_signals,
grant_signals
);
parameter BITS_REQUEST = 2;
localparam NUM_REQUEST = 2 ** BITS_REQUEST;
integer i;
input clk;
input [NUM_REQUEST-1:0] request_signals;
output reg [NUM_REQUEST-1:0] grant_signals;
always @(*) begin : grant_block
if (re... | 8.48355 |
module.
// RTL diagram: RTLDiagrams/coherentSampler.pdf
// Author: Adriaan Peetermans
// imec-COSIC, KU Leuven.
//
//////////////////////////////////////////////////////////////////////////////////
module coherentSampler # (
parameter cntWidth = 16 // Coherent sampler counter width.
)(
input ... | 7.137165 |
module vending (
input clk,
rst,
i,
j,
output x,
y
);
parameter idle = 3'b000, st1 = 3'b001, st2 = 3'b010, st3 = 3'b011, st4 = 3'b100;
reg [2:0] next_state, state;
always @(*) begin
case (state)
idle: next_state = i ? (j ? st2 : st1) : idle;
st1: next_state = i ? (j ? st3 ... | 7.518694 |
module coincidence (
output wire cu_gate_pos,
output wire cu_gate_neg,
output wire order_sct, // To Tank Number Flashing Unit. Order is gated
// by g13 and SCT by g12 in their respective units.
output wire r_pulse, // To MCU to signal end of Stage 1 and start of Stage 2.
... | 8.061666 |
module coin_adder (
input [13:0] count_coin_500,
input [13:0] count_coin_100,
input [13:0] count_coin_50,
input [13:0] count_coin_10,
output [22:0] sum
);
assign sum = 500 * count_coin_500 + 100 * count_coin_100 + 50 * count_coin_50 + 10 * count_coin_10;
endmodule
| 6.821952 |
module coin_reg (
input reset,
input add,
input dollar,
input quarter,
input dime,
input nickel,
input gum,
input candy,
input cookies,
input chips,
output reg [7:0] coins
);
initial begin
coins = 0;
end
always @(posedge reset or posedg... | 6.952923 |
module coin_return (
input [7:0] coins,
input clk,
input start,
input reset,
output reg active,
output reg done,
output reg quarter_return,
output reg dime_return,
output reg nickel_return
);
reg [7:0] coin_count;
... | 6.88733 |
module main; //: root_module
wire w6; //: /sn:0 {0}(57,149)(42,149){1}
wire w7; //: /sn:0 {0}(57,165)(42,165){1}
wire w16; //: /sn:0 {0}(240,117)(255,117){1}
wire [7:0] w14; //: /sn:0 {0}(#:240,85)(255,85){1}
wire [2:0] w19; //: /sn:0 {0}(#:240,165)(255,165){1}
wire w15; //: /sn:0 {0}(240,101)(255,10... | 6.5859 |
module col16to21 (
dataline,
texelselect,
r,
g,
b
);
input [63:0] dataline;
input [1:0] texelselect;
output [6:0] r;
wire [6:0] r;
output [6:0] g;
wire [6:0] g;
output [6:0] b;
wire [ 6:0] b;
reg [15:0] col16;
always @(dataline or texelselect) begin
case (texelselect)
... | 7.148898 |
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
(
input wire Clock,
input wire Clear,
input wire [SIZE-1:0] D,
output reg [SIZE-1:0] Q
);
always @(posedge Clock or posedge Clear)
begin
if (Clear)
Q = 0;
else
Q = D;
end
endmodule
| 7.133475 |
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
(
input wire Clock,
input wire Reset,
input wire Enable,
input wire [SIZE-1:0] D,
output reg [SIZE-1:0] Q
);
always @ (posedge Clock)
begin
if ( Reset )
Q <= `WIDTH'b0;
else
begin
if (Enable)
Q <= D;
end
end//always
endm... | 7.169605 |
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
always @(posedge Clock )
begin
if (Reset)
Q <= Initial;
else
begin
if (Enable)
Q <= Q + 1;
end
end
endmodule
| 6.54867 |
module SELECT_1_TO_N #(
parameter SEL_WIDTH = 4,
parameter OUTPUT_WIDTH = 16
) (
input wire [SEL_WIDTH-1:0] Sel,
input wire En,
output wire [OUTPUT_WIDTH-1:0] O
);
reg [OUTPUT_WIDTH-1:0] shift;
always @(*) begin
if (~En) shift = 1;
else shift = (1 << Sel);
end
assign O = (~En) ?... | 8.064134 |
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
(
input wire [1:0] Sel,
input wire [SIZE-1:0]I1, I2, I3,I4,
output reg [SIZE-1:0] O1
);
always @( * )
begin
case (Sel)
2'b00: O1 = I1;
2'b01: O1 = I2;
2'b10: O1 = I3;
2'b11: O1 = I4;
default: O1 = SIZE-1'b0;
endcase
... | 7.073618 |
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
( input wire Clock,
input wire Reset,
input wire[SIZE-1:0] Initial,
input wire Enable,
output wire[SIZE-1:0] O
);
reg [SIZE-1:0] tmp;
always @(posedge Clock)
begin
if (Reset)
tmp <= Initial;
else
begin
if (Enable)
begin
... | 7.125109 |
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
(
input wire [2:0] Sel,
input wire [SIZE-1:0]I1, I2, I3,
output reg [SIZE-1:0] O1
);
always @( * )
begin
case (Sel)
3'b001: O1 = I1;
3'b010: O1 = I2;
3'b100: O1 = I3;
default: O1 = SIZE-1'b0;
endcase
end
endmodule... | 7.073618 |
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
input wire Reset,
input wire[SIZE-1:0] Initial,
input wire Enable,
output wire[SIZE-1:0] O
);
reg [SIZE-1:0] tmp;
always @(posedge Clock)
begin
if (Reset)
tmp <= Initial;
else
begin
if (Enable)
tmp <= tmp << 1;
en... | 7.280972 |
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
input wire Reset,
input wire[SIZE-1:0] Initial,
input wire Enable,
output wire[SIZE-1:0] O
);
reg [SIZE-1:0] tmp;
always @(posedge Clock)
begin
if (Reset || tmp[SIZE-1])
tmp <= Initial;
else
begin
if (Enable)... | 7.125109 |
module UpCounter_16E (
input wire Clock,
input wire Reset,
input wire [15:0] Initial,
input wire Enable,
output wire [15:0] Q
);
reg [15:0] Temp;
always @(posedge Clock or posedge Reset) begin
if (Reset) Temp = Initial;
else if (Enable) Temp = Temp + 1'b1;
end
assign Q = Temp;
end... | 6.552643 |
module UpCounter_3 (
input wire Clock,
input wire Reset,
input wire [2:0] Initial,
input wire Enable,
output wire [2:0] Q
);
reg [2:0] Temp;
always @(posedge Clock or posedge Reset) begin
if (Reset) Temp = Initial;
else if (Enable) Temp = Temp + 3'b1;
end
assign Q = Temp;
endmodul... | 6.903349 |
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