code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module FFD32_POSEDGE (
input wire Clock,
input wire [31:0] D,
output reg [31:0] Q
);
always @(posedge Clock) Q <= D;
endmodule
| 6.870369 |
module MUXFULLPARALELL_96bits_2SEL (
input wire Sel,
input wire [95:0] I1,
I2,
output reg [95:0] O1
);
always @(*) begin
case (Sel)
1'b0: O1 = I1;
1'b1: O1 = I2;
endcase
end
endmodule
| 7.073618 |
module MUXFULLPARALELL_16bits_2SEL_X (
input wire [ 1:0] Sel,
input wire [15:0] I1,
I2,
I3,
output reg [15:0] O1
);
always @(*) begin
case (Sel)
2'b00: O1 = I1;
2'b01: O1 = I2;
2'b10: O1 = I3;
default: O1 = 16'b0;
endcase
end
endmodule
| 7.073618 |
module MUXFULLPARALELL_16bits_2SEL (
input wire Sel,
input wire [15:0] I1,
I2,
output reg [15:0] O1
);
always @(*) begin
case (Sel)
1'b0: O1 = I1;
1'b1: O1 = I2;
endcase
end
endmodule
| 7.073618 |
module colldetect (
input clk,
input [10:0] left_paddle_pos,
input [10:0] right_paddle_pos,
input ball_dir,
input [10:0] ball_h,
input [10:0] ball_v,
input [ 3:0] ball_speed,
output reg [ 6:0] seg,
output reg [ 3:0] an,
output reg ... | 7.058521 |
module Collector #(
parameter WIDTH0 = 32
, parameter WIDTH1 = 32
, parameter PRIORITY = 0
) (
input iValid_AS0
, output oReady_AS0
, input [ WIDTH0-1:0] iData_AS0
, input iValid_AS1
, output ... | 7.651534 |
module collector_gpio (
input wire i_clk,
input wire i_rst,
input wire i_dat,
input wire i_wb_stb,
output reg o_wb_rdt,
output reg o_wb_ack
);
reg dat_r;
always @(posedge i_clk) begin
o_wb_ack <= i_wb_stb & !o_wb_ack;
dat_r <= i_dat;
o_wb_rdt <= dat_r;
if (i_rst) o_wb... | 7.559643 |
module collector_spi (
input wire i_clk,
input wire i_rst,
output wire o_sclk,
output wire o_cs_n,
output wire o_mosi,
input wire i_miso,
input wire [ 4:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire i_wb_we,
input wire... | 7.469002 |
module.
mod_enable: Signal that activate the collision analyze process.
s_r(0,1,2...): Bus data of the sprites storage in the registry file.
OUPUTS:
flags: Bus that contains the collision flags to each sprite.
//////////////////////////////////////////////////////////////////////////
**/
module collision #... | 7.535096 |
module detectCollision (
runner_x,
runner_y,
runner_width,
runner_height,
block_x,
block_y,
block_width,
block_height,
collision
);
input [7:0] runner_x, block_x;
input [6:0] runner_y, block_y;
input [1:0] block_width, block_height, runner_width, runner_height;
output reg co... | 6.500244 |
module collision (
input clock,
input reset,
input [7:0] alienX,
input [7:0] alienY,
input [7:0] shotX,
input [7:0] shotY,
input [7:0] cannonX,
input [7:0] cannonY,
output reg [14:0] alive,
output reg cannon_alive,
output reg reset_shot
);
localparam A_WIDTH = 8'd13,
... | 6.640633 |
module checks for "collisions" by looking at X number of bits
* represented by the provided target. The clock controls the updated
* output of the checker.
*
* Input
* -----
*
* iClk: The clock used to update the internal register used to pipe output
* iTarget: Used to indicate the amount of bits to check st... | 7.191385 |
module collision_handler (
enem_grid,
clock,
startGameEn,
current_health_update,
user_x,
user_y,
enemy_x,
enemy_y
);
input [160*120-1:0]enem_grid; // 2D reigster grid representing where the bullets are on the screen
input clock; // default 50mhz clock on de2 board
input startGameE... | 7.752817 |
module collision_table (
address,
MRD_data2
);
input [31:0] address;
output reg [31:0] MRD_data2;
reg [31:0] addr;
always @(*) begin
addr <= address;
case (addr)
32'h00: MRD_data2 = 32'h25; //event triggered associated with unconditional frame 32'h25
32'h01: MRD_data2 = 32'... | 7.409966 |
module colMix_keyAdd (
input clk,
input rst_n,
input [127 : 0] iBlockIn,
input [127 : 0] iKeyValue, //轮密钥
output [127 : 0] oBlockout
);
wire [127 : 0] wColMixOut;
//列混淆
subColMix subColMix_inst0 //列1
(
.iBlockIn (iBlockIn[127 : 96]),
.oBlockout(wColMixOut[127 : 96])
);
s... | 7.923521 |
module color16x_12_ntsc_clockgen (
output wire clk_col16x,
input wire reset,
input wire clk_in12mhz
);
wire clk_col16x_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
w... | 7.690242 |
module color16x_12_pal_clockgen (
output wire clk_col16x,
input wire reset,
input wire clk_in12mhz
);
wire clk_col16x_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wi... | 7.26647 |
module ColorAlien (
hPos,
vPos,
xAlien,
yAlien,
alive,
colorAlien
);
parameter NB_LIN = 2;
parameter NB_COL = 2;
function integer Size(input integer in);
for (Size = 0; in > 0; Size = Size + 1) in = in >> 1;
endfunction
localparam SIZE_I = Size(NB_LIN);
localparam SIZE_J = S... | 8.329287 |
module coloRam (
Address,
DataIN,
DataOUT,
WE
);
parameter AddressSize = 8; // Need addresses for 3 colors per LED
parameter WordSize = 24; // 8 Bits per color
input [AddressSize-1:0] Address;
input [WordSize-1:0] DataIN;
output [WordSize-1:0] DataOUT;
input WE;
reg [WordSize-1:0] Mem... | 9.016742 |
module colorBarDVI (
input wire clk_i,
output wire TMDS_0_clk_p,
output wire TMDS_0_clk_n,
output wire [2:0] TMDS_0_data_p,
output wire [2:0] TMDS_0_data_n
);
wire TMDS_0_clk;
wire [2:0] TMDS_0_data;
CC_LVDS_OBUF lvds_obuf_inst[3:0] (
.A ({TMDS_0_clk, TMDS_0_data}),
... | 7.255907 |
module colorbars (
input clk,
output [3:0] LED,
output [3:0] red,
output [3:0] green,
output [3:0] blue,
output reg hsync,
output reg vsync
);
wire clk160;
wire locked;
assign LED = {3'bzzz, locked};
// Generate 160MHz
pll160 pll (
.clock_in(clk),
.clock_out(clk160),... | 6.6263 |
module colorBarVGA (
input wire clk_i,
input wire rstn_i,
output wire [3:0] o_r,
output wire [3:0] o_g,
output wire [3:0] o_b,
output wire o_vsync,
output wire o_hsync,
output wire o_clk,
output wire o_rst,
output wire [7:0] o_led
);
wire ... | 7.093065 |
module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <dtysky@outlook.com>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (... | 7.135037 |
module ColorBreathLED (
LEDr,
LEDg,
LEDb,
CLK
);
input CLK;
output LEDr, LEDg, LEDb;
wire UP;
wire DW;
wire STT0;
wire STT1;
PWM up (
CLK,
1,
STT0,
UP
);
PWM dw (
CLK,
0,
STT1,
DW
);
reg [1:0] flag0 = 2'b00;
always @(posedge STT0... | 6.886962 |
module PWM (
input CLK,
input FLAG, //标志位,控制输出的PWM是升还是降(1升0降)
output STT, //监视信号(脉冲)
output PWM
);
reg [24:0] cnt1;
reg [24:0] cnt2;
parameter freq = 2400; //控制PWM的周期
reg stt; //监视状态
always @(posedge CLK)
if (cnt2 == freq - 1) //cnt2满,则状态为1(只持续一个时钟周期)
stt <= 1'b1;
else... | 8.78102 |
module anfFl_tex_colorDecoder
(
input [127:0] data,
input [4:0] format,
output reg [7:0] R,
output reg [7:0] G,
output reg [7:0] B,
output reg [7:0] A,
input reg [1:0] texelX,
input reg [1:0] texelY
);
localparam fmt_RGB_24 = 5'b000_00;
localparam fmt_ARGB_32 = 5'b001_00;
localparam fmt_RGB... | 7.78703 |
module ColorDetect (
input clk,
input rst,
input hsv_hs,
input hsv_vs,
input hsv_de,
input [23:0] hsv,
output color_hs,
output color_vs,
output color_de,
output color
);
parameter S_THRESHOLD = 80;
parameter V_THRESHOLD = 180;
wire [7:0] hue, saturation, value;
assign h... | 7.675964 |
module ColorDreams #(
parameter MIRRORING_VERTICAL = 1
) (
output led,
input m2,
input romsel,
input cpu_rw_in,
output [18:12] cpu_addr_out,
input [14:0] cpu_addr_in,
input [7:0] cpu_data_in,
output cpu_wr_out,
output cpu_rd_out,
output cpu_flash_ce,
output cpu_sram_ce,
... | 7.376808 |
module colorful_breath_led (
clk,
key,
led,
digit_seg,
digit_cath,
swx,
swy,
real_rst,
R_N5,
G_R3,
B_R4,
R_T5,
G_T6,
B_T4
);
input clk;
input key;
output [7:0] led;
output [7:0] digit_seg;
output [1:0] digit_cath;
input [3:0] swx;
input [3:0] swy;
... | 6.52799 |
module colorful_breath_led_pro (
clk,
key,
led,
digit_seg,
digit_cath,
swx,
swy,
real_rst,
R_N5,
G_R3,
B_R4,
R_T5,
G_T6,
B_T4
);
input clk;
input key;
output [7:0] led;
output [7:0] digit_seg;
output [1:0] digit_cath;
input [3:0] swx;
input [3:0] sw... | 6.52799 |
module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <dtysky@outlook.com>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (... | 7.135037 |
module colorHandler (
reset,
select,
rgbEn,
charRGB,
bgRGB
);
input reset;
input [2:0] rgbEn; /* Defines the color to be modified {Blue,Green,Red} */
input select; /* Defines the buss to be modified, charRGB(low) or bgRGB(high) */
output [8:0] charRGB; /* Transfers the output color of t... | 9.725926 |
module coloriser (
reset,
fpga_clk,
vga_clk,
display_area,
shifter_output,
Rin,
Gin,
Bin,
Redout,
Greenout,
Blueout
);
input reset, Rin, Gin, Bin, vga_clk, display_area, fpga_clk;
input shifter_output;
output reg [2:0] Redout, Greenout, Blueout;
reg [2:0] Red, Green, ... | 7.924192 |
module colorizer (
input video_on,
input [11 :0] op_pixel,
input blank_disp,
input [2:0] superimpose_pixel,
input [3:0] top_left_r,
input [3:0] top_left_g,
input [3:0] top_left_b,
input [3:0] top_right_r,
input [3:0] top_right_g,
input [3:0] top_right_b,
input ... | 7.488232 |
module colorizer_v2 (
input [11:0] icon,
input [11:0] map_color,
input [11:0] title_color,
input video_on,
output reg [ 3:0] VGA_R,
output reg [ 3:0] VGA_G,
output reg [ 3:0] VGA_B
);
// determine between icon color or world color
always @(*) begin
if (~vi... | 9.234365 |
module Apb3Gpio (
input [ 3:0] io_apb_PADDR,
input [ 0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
i... | 6.706229 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input i_clk
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge i_clk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.82712 |
module StreamArbiter_4 (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [19:0] io_inputs_0_payload_addr,
input [ 3:0] io_inputs_0_payload_id,
input [ 7:0] io_inputs_0_payload_len,
input [ 2:0] io_inputs_0_payload_size,
input [ 1:0] io_inputs_0_payload_burst,
... | 6.929245 |
module StreamFifoLowLatency_1 (
input io_push_valid,
output io_push_ready,
output reg io_pop_valid,
input io_pop_ready,
input io_flush,
output [2:0] io_occupancy,
input axiClk,
input resetCtrl_axiReset
);
wire ... | 7.046487 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [31:0] io_axi_arw_payload_addr,
input [ 7:0] io_axi_arw_payload_len,
input [ 2:0] io_axi_arw_payload_size,
input [ 3:0] io_axi_arw_payload_cache,
input [ 2:0] io_axi_arw_payload_prot,
... | 6.942764 |
module Axi4ReadOnlyErrorSlave (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 1:0] io_axi_ar_payload_burst,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
out... | 7.858199 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input axiClk,
... | 7.790686 |
module InterruptCtrl (
input [3:0] io_inputs,
input [3:0] io_clears,
input [3:0] io_masks,
output [3:0] io_pendings,
input axiClk,
input resetCtrl_axiReset
);
reg [3:0] pendings;
assign io_pendings = (pendings & io_masks);
always @(posedge axiClk or posedge resetCtrl_axi... | 7.510624 |
module Timer (
input io_tick,
input io_clear,
input [31:0] io_limit,
output io_full,
output [31:0] io_value,
input axiClk,
input resetCtrl_axiReset
);
wire [31:0] _zz_counter;
wire [ 0:0] _zz_counter_1;
reg [31:0] counter;
wire limitHi... | 6.729771 |
module BufferCC_4 (
input [15:0] io_dataIn,
output [15:0] io_dataOut,
input axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg [15:0] buffers_0;
(* async_reg = "true" *)reg [15:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge axiClk) begin
buffers... | 6.634474 |
module BufferCC_3 (
input io_dataIn,
output io_dataOut,
input axiClk,
input resetCtrl_systemReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffe... | 6.792516 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiRe... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiRese... | 6.712921 |
module Apb3Gpio (
input [ 3:0] io_apb_PADDR,
input [ 0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
i... | 6.706229 |
module PipelinedMemoryBusRam (
input io_bus_cmd_valid,
output io_bus_cmd_ready,
input io_bus_cmd_payload_write,
input [31:0] io_bus_cmd_payload_address,
input [31:0] io_bus_cmd_payload_data,
input [ 3:0] io_bus_cmd_payload_mask,
output io_bus_rsp_valid,
o... | 7.802955 |
module MuraxMasterArbiter (
input io_iBus_cmd_valid,
output reg io_iBus_cmd_ready,
input [31:0] io_iBus_cmd_payload_pc,
output io_iBus_rsp_valid,
output io_iBus_rsp_payload_error,
output [31:0] io_iBus_rsp_payload_inst,
input io_d... | 7.748629 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input io_mainClk
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.82712 |
module InterruptCtrl (
input [1:0] io_inputs,
input [1:0] io_clears,
input [1:0] io_masks,
output [1:0] io_pendings,
input io_mainClk,
input resetCtrl_systemReset
);
reg [1:0] pendings;
assign io_pendings = (pendings & io_masks);
always @(posedge io_mainClk or posedge res... | 7.510624 |
module Timer (
input io_tick,
input io_clear,
input [15:0] io_limit,
output io_full,
output [15:0] io_value,
input io_mainClk,
input resetCtrl_systemReset
);
wire [15:0] _zz_counter;
wire [ 0:0] _zz_counter_1;
reg [15:0] counter;
wire l... | 6.729771 |
module BufferCC_4 (
input [15:0] io_dataIn,
output [15:0] io_dataOut,
input io_mainClk,
input resetCtrl_systemReset
);
(* async_reg = "true" *)reg [15:0] buffers_0;
(* async_reg = "true" *)reg [15:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk) begin
... | 6.634474 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input io_mainClk,
... | 7.790686 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output ... | 7.046487 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_mainClkReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 ... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_systemReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (rese... | 6.712921 |
module colormap (
// {{{
// (i_clk, i_map, i_pixel, o_r, o_g, o_b);
input wire i_clk,
input wire [2:0] i_map,
input wire [7:0] i_pixel,
output reg [7:0] o_r,
o_g,
o_b
// }}}
);
// Local declarations
// {{{
wire [7:0] bw_r, bw_g, bw_b,
md_r, md_g, md_b,
mr_r, mr_g, mr_b,
... | 7.687786 |
module colorMapper (
input [9:0] xDraw,
input [9:0] yDraw,
input blank, //active low
output red,
output green,
output blue
);
reg red_int;
reg green_int;
reg blue_int;
always @(*)
if (xDraw < 64 && yDraw < 128) begin
red_int = 1;
green_int = 1;
blue_int = 1;
... | 7.466126 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001... | 7.584821 |
module ColorMemory (
input clk,
ce5,
input CRAMn,
input [7:0] BD,
input [5:0] BA,
input MPI,
input [2:0] MV,
input [3:0] BIT,
output [8:0] o
);
wire sel = (~MV[2] & ~MV[1] & ~MV[0]) | (~MV[2] & ~MPI) | (~MV[2] & ~BIT[3]) | (~MV[1] & ~MPI) | (~MV[1] & ~BIT[3]) | (~MV[0] & ~MPI) ... | 6.61789 |
module anfFl_tex_colorNorm
(
input[7:0] channel,
output [31:0] normalized
);
assign normalized = {16'b0, 2{channel}};
endmodule
| 7.78703 |
module coloroutput (
input clk,
input pixelclk,
input rst,
input [7:0] color_input,
input blanking,
input c0,
input c1,
output dout
);
wire [9:0] color_output;
tsdm tsdm (
.clk(pixelclk),
.rst(rst),
.din(color_input),
.dout(color_output),
.blanking(bla... | 7.561833 |
module colorReduce (
input [23:0] RGB,
input clk,
input reset,
input select,
input [1:0] selector,
input [2:0] inputVal,
output [23:0] uptRGB,
input brighter //brightness switch
);
wire [7:0] R;
wire [7:0] G;
wire [7:0] B;
assign R = RGB[23:16];
assign G = RGB[15:8];
assig... | 7.106617 |
module colorReduction (
input [23:0] HSV,
input clk,
input [7:0] hThreshold,
input [7:0] sThreshold,
input [7:0] vThreshold,
output [23:0] tHSV
);
wire [7:0] H;
wire [7:0] S;
wire [7:0] V;
assign H = HSV[23:16];
assign S = HSV[15:8];
assign V = HSV[7:0];
reg [7:0] tH;
reg [7:0... | 7.039299 |
module COLOR_REGS #(
parameter addr_width = 4,
data_width = 24
) (
input wire clk_a,
input wire we_a,
input wire [addr_width-1:0] addr_a,
input wire [data_width-1:0] din_a,
output reg [data_width-1:0] dout_a,
input wire we_b,
input wire clk_b,
input wire [addr_width-1:0] addr_b,
... | 7.779321 |
module
:Version
1.0
:Modified
2015-05-16
Copyright (C) 2015 Tianyu Dai (dtysky) <dtysky@outlook.com>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (a... | 7.135037 |
module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <dtysky@outlook.com>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (... | 7.135037 |
module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <dtysky@outlook.com>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (... | 7.135037 |
module colors (
input clk,
input clk100,
input button,
input wire data_in,
input wire [2:0] cnt,
output data,
output [7:0] q
);
wire [15:0] w_num;
wire w_req;
wire w_sync;
reg [23:0] rgb = 0;
reg [2:0] sss;
always @(posedge clk) sss <= {sss[1:0], w_sync};
wire sync_edge;
a... | 6.854604 |
module colorspace (
clk,
din0,
din1,
din2,
dout0,
dout1,
dout2,
rstn
);
input rstn;
input clk;
input [12-1:0] din0;
input [12-1:0] din1;
input [12-1:0] din2;
output [12-1:0] dout0;
output [12-1:0] dout1;
output [12-1:0] dout2;
endmodule
| 6.59054 |
module colorspace (
clk,
din0,
din1,
din2,
dout0,
dout1,
dout2,
rstn
);
input rstn;
input clk;
input [12-1:0] din0;
input [12-1:0] din1;
input [12-1:0] din2;
output [12-1:0] dout0;
output [12-1:0] dout1;
output [12-1:0] dout2;
csc_core_colorspace #(
.CORETYPE (0)... | 6.59054 |
module colorspace_top (
clk,
din0,
din1,
din2,
dout0,
dout1,
dout2,
rstn
);
input rstn;
input clk;
input [12-1:0] din0;
input [12-1:0] din1;
input [12-1:0] din2;
output [12-1:0] dout0;
output [12-1:0] dout1;
output [12-1:0] dout2;
colorspace u1_colorspace (
.clk... | 6.875017 |
module colorsRGB (
input clk,
input wire [7:0] clr_red,
input wire [7:0] clr_green,
input wire [7:0] clr_blue,
output data
);
wire [15:0] w_num;
wire w_req;
wire w_sync;
wire [7:0] red;
wire [7:0] green;
wire [7:0] blue;
mod_bit_reverse #(
.NUM_BITS(8)
) my_reverse_module1 (
... | 6.808389 |
module color_3b_12b_decoder (
input wire [ 2:0] color_3bit, /// 3-bit RGB signal
output wire [11:0] color_12bit /// 12-bit RGB signal
);
one_to_four_decoder decoder_1b_4b_red (
.in (color_3bit[2])
, .out(color_12bit[11:8])
);
one_to_four_decoder decoder_1b_4b_green (
.in (color_... | 8.405655 |
module color_bars #(
parameter START_Y = 9'd0
) (
input wire [9:0] x,
input wire [8:0] y,
input wire active_video,
output wire [7:0] rgb
);
// CONSTANTS ///////////////////////////////////////////////////////////////////
localparam BLACK = 8'b0000_0000,
RED = 8'b0000_01... | 7.90344 |
module tb_color_bar (
//////////////////////// SYS Input ////////////////////////
input wire CLOCK_50, // 50 MHz
input wire RST_N,
//////////////////////// VGA ////////////////////////////
output wire VGA_HS, // VGA H_SYNC
output wire VGA_VS, // VGA V_SYNC
... | 8.995337 |
module color_blink (
input [7:0] i_attr, // Color attribute. irgb back (8b), irgb fore (8b)
input i_fg, // pixel active (foreground color) or background color
input i_blink, // blinking line
input i_ble, // blink enable
output [4:0] o_red,
output [5:0] o_green,
... | 7.75743 |
module color_blob (
input wire clk,
input wire [9:0] hcount,
input wire [9:0] vcount,
input wire [9:0] x_loc,
input wire [9:0] y_loc,
input wire enable,
input wire [8:0] color,
output reg [8:0] pixel
);
parameter blob_size = 8;
always @(posedge clk) begin
if( (hcount>=x_loc)&... | 7.140628 |
module color_change (
input clk,
input rst,
input btnCHGCOLOR,
input mode,
input keyPressed,
output reg [7:0] VGA_NOTE,
output reg [7:0] VGA_PLAYER,
output reg [7:0] VGA_MENU
);
reg [1:0] color_opt;
initial begin
color_opt = 0;
end
always @(posedge clk) begin
if (rst) be... | 7.987933 |
module color_circlizer (
input [4:0] x_position,
input [4:0] y_position,
input [7:0] color_in,
input [7:0] color_blank,
output [7:0] color_out
);
parameter BLOCK_SIZE = 20;
// 32 / 2 = 16
wire [3:0] x = x_position > BLOCK_SIZE / 2 ? x_position - BLOCK_SIZE / 2 : BLOCK_SIZE / 2 - x_positi... | 7.279607 |
module color_clock (
clk_50,
h_sync,
v_sync,
R_out,
G_out,
B_out,
clk,
sw
);
input clk_50;
input wire [2:0] sw;
output h_sync, v_sync, R_out, G_out, B_out, clk;
reg R, G, B;
// generate 25MHz clock signal
reg clk;
always @(posedge clk_50) clk = ~clk;
wire onscreen;
hv... | 7.184599 |
module color_comparator_rgb555 (
input wire [15:0] in_color,
input wire [4:0] in_value,
output reg r,
g,
b
);
always @(in_color or in_value) begin
r = in_color[14:10] > in_value;
g = in_color[9:5] > in_value;
b = in_color[4:0] > in_value;
end
endmodule
| 6.705572 |
module color_comparator_rgb565 (
input wire [15:0] in_color,
input wire [5:0] in_value,
output reg r,
g,
b
);
always @(in_color or in_value) begin
r = in_color[15:11] > in_value[5:1];
g = in_color[10:5] > in_value;
b = in_color[4:0] > in_value[5:1];
end
endmodule
| 6.705572 |
module color_decode (
input [2:0] code,
output reg [11:0] hex
);
reg [11:0] BLACK = 12'h000;
reg [11:0] GREY = 12'h888;
// reg [11:0] BLUE = 12'hxxx;
// reg [11:0] LIGHT_BLUE = 12'hxxx;
reg [11:0] ORANGE = 12'hf82;
reg [11:0] GREEN = 12'h083;
reg [11:0] YELLOW = 12'hff3;
reg [11:0] RED = ... | 7.94123 |
module color_encoder(
input [2:0]code,
output reg[23:0]color_rgb
);
//RGB色彩编码
parameter WHITE = 24'hFFFFFF;
parameter GREEN = 24'h008000;
parameter ORANGE= 24'hFFA500;
parameter BLUE = 24'h0000FF;
parameter RED = 24'hFF0000;
parameter YELLOW= 24'hFFFF00;
parameter BLACK = ... | 8.359747 |
module Color_Extract (
input i_clk,
input i_rst,
input i_select,
input i_rgb_vde,
input i_rgb_hsync,
input i_rgb_vsync,
input [23:0] i_rgb_data,
input [10:0] i_set_x,
input [9:0] i_set_y,
output [23:0] o_rgb_data,
output o_rgb_vde,
output o_rgb_hsync,
output o_rgb_vsy... | 7.971574 |
module color_gen (
Ball_X,
Ball_Y,
VGA_X,
VGA_Y,
Ball_S,
VGA_R,
VGA_G,
VGA_B
);
input [9:0] Ball_X; // the x cordinate of the ball
input [9:0] Ball_Y; // the y cordinate of the ball
input [9:0] VGA_X; // the vga current scan x cordinate
input [9:0] VGA_Y; // the vga current ... | 7.411998 |
module converts the `show` output (when high) to a color, and changes this color at the rate of the FSM clock.
*
* Author: Malcolm Watt
*/
module color_map(fsm_clock, show, red, green, blue);
input fsm_clock;
input show;
output reg [3:0] red;
output reg [3:0] green;
output reg [3:0] blue;
always @ (fsm_cloc... | 6.747013 |
module color_pallette1 (
output [7:0] R,
output [7:0] G,
output [7:0] B,
input [3:0] fg,
input [3:0] bg
);
//Different Color Palettes
//https://www.fountainware.com/EXPL/vga_color_palettes.htm
//Standard pallette:
wire [11:0] pallette[15:0]; //Array of RGB values so we can do multiplexi... | 6.809852 |
module color_pallette2 (
output [7:0] R,
output [7:0] G,
output [7:0] B,
input [3:0] fg,
input [3:0] bg
);
//Different Color Palettes
//https://www.fountainware.com/EXPL/vga_color_palettes.htm
//Standard pallette:
wire [11:0] pallette[15:0]; //Array of RGB values so we can do multiplexi... | 6.809852 |
module color_pallette3 (
output [7:0] R,
output [7:0] G,
output [7:0] B,
input [3:0] fg,
input [3:0] bg
);
//Different Color Palettes
//https://www.fountainware.com/EXPL/vga_color_palettes.htm
//Standard pallette:
wire [11:0] pallette[15:0]; //Array of RGB values so we can do multiplexi... | 6.809852 |
module color_pallette4 (
output [7:0] R,
output [7:0] G,
output [7:0] B,
input [3:0] fg,
input [3:0] bg
);
//Different Color Palettes
//https://www.fountainware.com/EXPL/vga_color_palettes.htm
//Standard pallette:
wire [11:0] pallette[15:0]; //Array of RGB values so we can do multiplexi... | 6.809852 |
module color_ram (
input clk_a,
input clk_b,
input reset,
input [3:0] addr_a,
output [3:0] dout_a,
input [3:0] din_a,
input we_n_a,
input [3:0] addr_b,
output [3:0] dout_b
);
reg [3:0] ram[0:15];
reg [3:0] d_a, d_b;
`ifdef SIMULATION
integer j... | 6.648811 |
module color_rec (
input clk_100MHz,
input Clk_Rx_Data_N,
input Clk_Rx_Data_P,
input [1:0] Rx_Data_N,
input [1:0] Rx_Data_P,
input Data_N,
input Data_P,
inout Camera_IIC_SDA,
output Camera_IIC_SCL,
output Camera_GPIO,
output reg LED_R,
output reg LED_G,
output RGB_LED... | 6.795498 |
module color_renderer (
output reg [3:0] red,
output reg [3:0] green,
output reg [3:0] blue,
input is_paddle,
input is_square,
input [9:0] draw_x,
input [9:0] draw_y,
input clk
);
localparam HPERIOD = 10'd800;
localparam HFRONT = 10'd16;
localparam HWIDTH = 10'd96;
localparam HB... | 7.39947 |
module. Saves the frequency found to the
corresponding register of color. (R,G,B,C). Then changes the diode being read on
the color sensor.
Once data saved, performs percentage operation for each filter diode over clear
using the calc_perc module.
Once the percentage is found, it will be compared to values found thro... | 6.977759 |
module color_sq #(
parameter x_off = 0,
parameter y_off = 0,
parameter w = 100,
parameter h = 100,
parameter color1 = 6'b000000,
parameter color2 = 6'b111111
) (
input wire clk, // System clock.
input wire [9:0] x_px, // X position actual pixel.
input wire [9:0] y... | 8.465284 |
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