code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module color_square
# (
parameter HPOS_WIDTH = 10,
VPOS_WIDTH = 10,
// Display constants
H_DISPLAY = 640, // Horizontal display width
V_DISPLAY = 480 // Vertical display height
)
(
input c... | 7.713418 |
module color_strip (
input clk,
rst_n,
input [10:0] h_cnt,
input [10:0] v_cnt,
input [10:0] H_VISIBLE,
input [10:0] H_BACK_PORCH,
input [10:0] V_VISIBLE,
input [10:0] V_BACK_PORCH,
output [3:0] o_r,
output [3:0] o_g,
output [3:0] o_b
);
parameter BLACK = 12'b0000_0000_0000;... | 8.085314 |
module to choose colours based on x/y coordinate
module colourful(
input wire clk,
input wire [9:0]x,
input wire [9:0]y,
output reg [3:0]red,
output reg [3:0]green,
output reg [3:0]blue
);
always @(posedge clk)
begin
red <= x[4:1];
green <= y[4:1];
blue[1:0] <= x[6:5];
blue[3:2] <= y[6:5];
end
endmodule
| 8.448113 |
module ColourMux (
input CLK_n,
input [4 : 0] BORDER,
input [15 : 0] INKR0,
input [15 : 0] INKR1,
input [15 : 0] INKR2,
input [15 : 0] INKR3,
input [15 : 0] INKR4,
input COLOUR_KEEP,
input INK_SEL,
input BORDER_SEL,
input MODE_IS_0,
input MODE_IS_2,
input [3 : 0] CIDX... | 6.916828 |
module ColourMuxBit (
input CLK_n,
input COLOUR_KEEP,
input BORDER_SEL,
input BORDER,
input INK_SEL,
input [15 : 0] INKR,
input [3 : 0] CIDX,
input MODE_IS_0,
input MODE_IS_2,
output reg INK
);
// Note: component numbers relate to ColourMuxBit0 on the schematics
wire u1701, u... | 7.872608 |
module colour_bar (
input clk,
output reg [7:0] red,
output reg [7:0] green,
output reg [7:0] blue,
input [15:0] sx
);
reg [3:0] bar;
always @(posedge clk) begin
if (sx < 128) bar <= 4'd0;
else if (sx < 256) bar <= 4'd1;
else if (sx < 384) bar <= 4'd2;
else if (sx < 512) bar <=... | 6.840558 |
module colour_boxes (
input [11:0] VGA_HORZ_COORD,
input [11:0] VGA_VERT_COORD,
output reg [3:0] VGA_CBOXR,
output reg [3:0] VGA_CBOXG,
output reg [3:0] VGA_CBOXB
);
parameter sep = 40;
parameter x_left = 40;
parameter redrow = 410 + sep * 6;
parameter greenrow = 410 + sep * 7;
parameter ... | 7.103596 |
module Colour_control (
input [8:0] vert_address,
input [9:0] horz_address,
input [11:0] COLOUR_IN,
input [1:0] M_STATE,
input CLK,
output [11:0] COLOUR_OUT
);
// Final output colour
reg [11:0] out_col;
// Variables for creating interesting animation in the last state
reg [15:0] FrameC... | 7.656144 |
module Colour_wrapper (
input CLK,
input [1:0] M_STATE,
input [11:0] COLOUR_IN,
output [11:0] COLOUR_OUT,
output HS,
output VS,
output [8:0] ADDR_V,
output [9:0] ADDR_H
);
wire [11:0] control_colour_out;
wire [ 9:0] horz_address;
wire [ 8:0] vert_address;
VGA_Interface vga (
... | 7.7685 |
module rowbuffer #(
parameter dataWidth = 32, // the data bit width
parameter pvadd = 256, // the parallesim in feature adder
parameter k = 1024 // define k as the block size
) (
clk,
rst,
enableA,
enableB,
writeEnableA1,
writeEnableA2,
writeEnableB1,
writeEnableB2,
re... | 9.491926 |
module column_counter (
input reset,
input clk,
input push_in,
output push_out,
input [31:0] in_col_index,
output [31:0] out_col_index,
output [4:0] out_count
);
//TODO: fix counter bug
reg r_push_out;
reg [31:0] col_index;
reg [4:0] counter;
reg [5:0] timer;
reg [4:0] r_out_coun... | 6.609248 |
module column_decoder (
input [1:0] in,
output reg [2:0] column
);
always @(*) begin
case (in)
2'd0: column <= 3'b100; // Col 1
2'd1: column <= 3'b010; // Col 2
2'd2: column <= 3'b001; // Col 3
default: column <= 3'b000;
endcase
end
endmodule
| 7.004054 |
module column_reg_file (
output reg [7:0] out1,
out2,
out3,
out4,
input wire [7:0] in,
in1,
in2,
in3,
in4,
input wire enable,
enable2,
input wire [1:0] index,
input wire clk,
input wire rst
);
integer i;
localparam COLUMN1 = 2'b00, CO... | 6.865787 |
module column_reg_file2 (
output reg [7:0] out1,
out2,
out3,
out4,
input wire [7:0] in,
input wire [1:0] index,
input wire enable,
input wire clk,
input wire rst
);
integer i;
localparam COLUMN1 = 2'b00, COLUMN2 = 2'b01, COLUMN3 = 2'b10, COLUMN4 = 2'b11;... | 6.865787 |
module Column_State_Machine_Test (
CLOCK_50,
SW,
LEDG,
BUTTON,
VGA_R,
VGA_G,
VGA_HS,
VGA_VS
);
input CLOCK_50;
input [9:0] SW;
input [2:0] BUTTON;
output [3:0] VGA_R, VGA_G;
output [9:0] LEDG;
output VGA_HS, VGA_VS;
wire [1199:0] framebuffer;
wire [4:0] ypos_wire;
wire... | 6.662981 |
module com (
input nRESET,
input CLK_48M,
input nPORTOEL,
input nPORTOEU,
input nPORTWEL,
output [15:0] M68K_DIN
);
reg nPORTWEL_PREV, TOGGLE_BIT;
assign M68K_DIN[15:8] = nPORTOEU ? 8'bzzzzzzzz : {4'b0000, TOGGLE_BIT, 3'b000};
assign M68K_DIN[7:0] = nPORTOEL ? 8'bzzzzzzzz : 8'h00;
al... | 8.049527 |
module comb #(
parameter I_BW = 8,
parameter O_BW = 9
) (
// clock and reset
input clk_i,
input rst_n_i,
input en_i,
// streaming input
input signed [I_BW - 1 : 0] data_i,
input valid_i,
// streaming output
output signed [O_BW - 1 : 0] data_o,
outp... | 7.300399 |
modules from simplecircuitA.v and simplecircuitB.v
module top_module (input x, input y, output z);
wire[3:0] z0;
cktA A1(x, y, z0[0]);
cktB B1(x, y, z0[1]);
cktA A2(x, y, z0[2]);
cktB B2(x, y, z0[3]);
assign z = (|z0[1:0]) ^ (&z0[3:2]);
endmodule
| 7.186589 |
module cktA (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 8.479482 |
module cktB (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 8.476737 |
module ADD4 (
A,
Cout,
Cin,
B,
S
);
//: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>A[3:0](16/64) Li1>B[3:0](41/64) Bo0<Cout(32/64) Ro0<S[3:0](27/64) ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
input [3:0] B; //: /sn:0 {0}(#:35,285)(#:49,285){1}
input [3:0] A; //: /sn:0 {0}(#:48,156)(#:79,156){1}
o... | 6.526487 |
module ADD4 (
A,
Cout,
Cin,
B,
S
);
//: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>B[3:0](41/64) Li1>A[3:0](16/64) Bo0<Cout(32/64) Ro0<S[3:0](27/64) ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
input [3:0] B; //: /sn:0 {0}(#:35,285)(#:49,285){1}
input [3:0] A; //: /sn:0 {0}(#:48,156)(#:79,156){1}
o... | 6.526487 |
module giveOutput (
input store[31:0],
input amt1 [31:0],
input amt0 [31:0],
output out1 [31:0],
output out0 [31:0]
);
for (i = 0; i < 32; i = i + 1) begin
if (store[i] == 1) begin
assign out0[i] = amt0[i];
assign out1[i] = amt1[i];
end else begin
assign out0[i] = 1'b... | 6.695413 |
module CombinationalROMModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire [7:0] ReadAddress1,
input wire [7:0] ReadAddress2,
output wire [7:0] Value1,
output wire [7:0] Value2
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam ... | 6.712343 |
module top_module (
input a,
input b,
output q
); //
assign q = a & b;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = ~(a ^ b ^ c ^ d);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (a | b) & (c | d);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b | c;
endmodule
| 7.203305 |
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q
);
always @(*) begin
case (c)
0: q <= b;
1: q <= e;
2: q <= a;
3: q <= d;
default: q <= 4'b1111;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [ 2:0] a,
output [15:0] q
);
always @(*) begin
case (a)
0: q <= 16'h1232;
1: q <= 16'haee0;
2: q <= 16'h27d4;
3: q <= 16'h5a0e;
4: q <= 16'h2066;
5: q <= 16'h64ce;
6: q <= 16'hc526;
7: q <= 16'h2f19;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [99:0] in,
output [99:0] out
);
always @(*) begin
for (int i = 0; i <= 99; i++) begin
out[i] = in[99-i];
end
end
endmodule
| 7.203305 |
module clk_divider (
clk,
rst,
led
);
input clk, rst;
output led;
reg led;
reg [26:0] counter;
always @(posedge rst or posedge clk) begin
if (rst) begin
led <= 0;
counter <= 0;
end else if (counter >= 50000000) begin
counter <= 0;
led <= ~led;
end else begin
... | 6.620262 |
module four_bit_counter (
clk,
rst,
a0,
a1,
a2,
a3
);
input clk, rst;
output reg a0, a1, a2, a3;
always @(posedge clk or posedge rst) begin
if (rst) begin
a0 <= 1'b0;
a1 <= 1'b0;
a2 <= 1'b0;
a3 <= 1'b0;
end else begin
a3 <= a3 ^ (a0 & a1 & a2);
... | 6.701443 |
module four_bit_counter_tb; // No inputs for a testbench!
// Inputs in the module to be tested will be port mapped to register variables
wire a0, a1, a2, a3;
// Outputs in the module to be tested will be port mapped to wire variables
reg clk, rst;
// Instantiation of the design module to be verified by th... | 6.701443 |
module Combinational_Logic_LZA #(
parameter SWR = 26
) (
input wire [SWR-1:0] P_i,
input wire [SWR-1:1] C_i,
input wire A_S_i,
output wire [SWR-1:0] S_o
);
genvar j;
generate
for (j = 0; j < SWR; j = j + 1) begin
case (j)
0: begin
assign S_o[0] = ~(A_S_i ^ P_i[0]);
... | 6.712343 |
module COMBINATOR (
input [BRAM_WIDTH*2-1:0] bramOut,
input [DATA_PATH_WIDTH-1:0] adderOut,
input [BRAM_PARALLELISM_BITS-1:0] addr,
output reg [BRAM_WIDTH*2-1:0] out
);
parameter COMPLEX = 2;
parameter PRECISION = 32;
parameter PARALLELISM = 15;
parameter BRAM_PARALLELISM_BITS = 4;
parameter ... | 6.954267 |
module CombinatoricRowByCol (
y,
a,
b
); // Note size be a power of 2. // not tested
parameter WIDTH = 32; // wordlength
parameter SIZE = 4; // SIZE of vector
input [WIDTH*SIZE-1:0] a, b; // Arow Bcol
wire [WIDTH*(2*SIZE-1)-1:0] partials; // [A1*B1, A2*B2,...A3*B3 ... A1*B1+A2*B2, A1*B1+A2*... | 6.844317 |
module ALU1 (
input [3:0] inA,
input [3:0] inB,
input [1:0] inC,
input [1:0] op,
output [3:0] ans
);
assign ans = (op == 2'b00) ? $signed(
$signed(inA) >>> inC
) : (op == 2'b01) ? (inA >> inC) : (op == 2'b10) ? (inA - inB) : (inA + inB);
endmodule
| 6.906507 |
module top_module (
input x,
input y,
output z
);
wire o1, o2, o3, o4;
A a1 (
x,
y,
o1
);
B b1 (
x,
y,
o2
);
A a2 (
x,
y,
o3
);
B b2 (
x,
y,
o4
);
assign z = (o1 | o2) ^ (o3 & o4);
endmodule
| 7.203305 |
module A (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 8.429663 |
module B (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 9.609894 |
module combine;
task passTest; // Test passed
input [31:0] actualOut, expectedOut; // actualout= actual output, expected output = correct output
input [`STRLEN*8:0] testType; //string that describes test
inout [256:0] passed; // number of tests that passed
if (actualOut === expectedOut) begin
... | 6.993116 |
module with lower priority,
* chain_out outputs chain_in signals if there is no valid match on action
* inputs.
*/
`include "parameters.v"
module combinechain(
input[C_OUT_PORT_WIDTH-1:0] action_port,
input[C_OUT_PORT_WIDTH-1:0] action_vport,
input action_match,
input[C_MATCH_ADDR_WIDTH-1:0] action_... | 6.906185 |
module DPWM (
CLOCK_50,
resetn,
EN,
maxcount,
adjDutyCycle,
C_1,
C_2
);
input CLOCK_50;
input resetn;
input EN;
input [9:0] maxcount;
input [9:0] adjDutyCycle;
reg [9:0] counter; //counter for DPWM sawtooth
output reg C_1;
output reg C_2;
always @(posedge CLOCK_50, neg... | 6.500193 |
module DutyCycleConverter (
duty_8b,
CLOCK_50,
frequency,
dutyCount
);
input CLOCK_50;
input [3:0] frequency;
input [7:0] duty_8b;
output reg [9:0] dutyCount;
always @(*)
case (frequency) /// TO DO: saturate duty to maxCount (duty = duty_8b...>maxCount ? maxCount : duty_8b...)
4'b0... | 7.085519 |
module FreqConverter (
freq_4b,
CLOCK_50,
maxcount
);
input CLOCK_50;
input [3:0] freq_4b;
output reg [9:0] maxcount;
always @(*)
case (freq_4b)
4'b0000: maxcount = 10'b1111101000; //1000 and freq = 50khz
4'b0001: maxcount = 10'b1100000001; //769 and freq = 65khz
4'b0010: m... | 6.608449 |
module shiftn (
binary,
w,
Clock,
bit_value
);
input [2:0] binary;
input w, Clock;
output reg bit_value;
integer n;
always @(binary)
case (binary)
3'b001: n = 0;
3'b010: n = 1;
3'b011: n = 2;
3'b100: n = 3;
3'b101: n = 4;
default: n = 0;
endca... | 7.844199 |
module LCD_display (
input CLOCK_50, // 50 MHz clock
input [0:0] KEY, // Pushbutton[0]
input [1:0] SW, //Using 2 switches
output [6:0] HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7, // Seven Segment Digits
input [3:0] VinH,
VinL,
Vo... | 7.355324 |
module LCD_display_string (
index,
out,
hex0,
hex1,
hex2,
hex3,
hex4,
hex5,
hex6,
hex7
);
input [4:0] index;
input [3:0] hex0, hex1, hex2, hex3, hex4, hex5, hex6, hex7;
output [7:0] out;
reg [7:0] out;
// ASCII hex values for LCD Display
// Enter Live Hex Data Values ... | 8.592639 |
module Reset_Delay (
iCLK,
oRESET
);
input iCLK;
output reg oRESET;
reg [19:0] Cont;
always @(posedge iCLK) begin
if (Cont != 20'hFFFFF) begin
Cont <= Cont + 1'b1;
oRESET <= 1'b0;
end else oRESET <= 1'b1;
end
endmodule
| 6.570866 |
module MUX2A (
A,
B,
S,
O
);
//Parameters
parameter WORD = 10;
//Input Definitions
input [(WORD-1):0] A, B;
input [1:0] S;
//Output Definitions
output [(WORD-1):0] O;
//n Parallel MUXs
genvar i;
generate
for (i = 0; i < WORD; i = i + 1) begin : MUX2
MUX2 U1 (
... | 7.036631 |
module MUX3 (
A,
B,
C,
S,
O
);
//Input Definitions
input A, B, C;
input [2:0] S;
//Output Defintions
output O;
//Clocked Logic
reg O;
always @(A or B or C or S) begin
case (S)
3'b100: O = A;
3'b010: O = B;
3'b001: O = C;
default: O = 1'b0;
endca... | 6.629323 |
module MUX3A (
A,
B,
C,
S,
O
);
//Parameters
parameter WORD = 10;
//Input Definitions
input [(WORD-1):0] A, B, C;
input [2:0] S;
//Output Definitions
output [(WORD-1):0] O;
//n Parallel MUXs
genvar i;
generate
for (i = 0; i < WORD; i = i + 1) begin : MUX3
MUX3 U1 (... | 7.470504 |
module MUX4 (
A,
B,
C,
D,
S,
O
);
//Input Definitions
input A, B, C, D;
input [3:0] S;
//Output Defintions
output O;
//Clocked Logic
reg O;
always @(A or B or C or D or S) begin
case (S)
4'b1000: O = A;
4'b0100: O = B;
4'b0010: O = C;
4'b0001: O = ... | 7.900747 |
module MUX4A (
A,
B,
C,
D,
S,
O
);
//Parameters
parameter WORD = 10;
//Input Definitions
input [(WORD-1):0] A, B, C, D;
input [3:0] S;
//Output Definitions
output [(WORD-1):0] O;
//n Parallel MUXs
genvar i;
generate
for (i = 0; i < WORD; i = i + 1) begin : MUX4
... | 7.642102 |
module MUX5 (
A,
B,
C,
D,
E,
S,
O
);
//Input Defintions
input A, B, C, D, E;
input [4:0] S;
//Output Definitions
output O;
//Clocked Logic
reg O;
always @(A or B or C or D or E or S) begin
case (S)
5'b10000: O = A;
5'b01000: O = B;
5'b00100: O = C;
... | 6.917526 |
module MUX5A (
A,
B,
C,
D,
E,
S,
O
);
//Parameters
parameter WORD = 10;
//Input definitions
input [(WORD-1):0] A, B, C, D, E;
input [4:0] S;
//Output defintions
output [(WORD-1):0] O;
//n Parallel MUXs
genvar i;
generate
for (i = 0; i < WORD; i = i + 1) begin : MU... | 7.184636 |
module DFFS (
CLK,
R,
D,
Q
);
//Input definitions
input CLK, R, D;
//Output defintions
output Q;
//Clocked Logic
reg Q;
always @(posedge CLK or negedge R) begin
if (~R) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 6.707713 |
module DFFSN (
CLK,
R,
D,
Q
);
//Input definitions
input CLK, R, D;
//Output defintions
output Q;
//Clocked Logic
reg Q;
always @(negedge CLK or negedge R) begin
if (~R) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 6.693195 |
module DFFA (
CLK,
R,
D,
Q
);
//Parameters
parameter WORD = 10;
//Input defintions
input CLK, R;
input [(WORD-1):0] D;
//Output Defintions
output [(WORD-1):0] Q;
//n Parallel DFFs
genvar i;
generate
for (i = 0; i < WORD; i = i + 1) begin : DFF
DFFS U1 (
.CLK(C... | 7.798529 |
module DFFAN (
CLK,
R,
D,
Q
);
//Parameters
parameter WORD = 10;
//Input defintions
input CLK, R;
input [(WORD-1):0] D;
//Output Defintions
output [(WORD-1):0] Q;
//n Parallel DFFs
genvar i;
generate
for (i = 0; i < WORD; i = i + 1) begin : dff
DFFSN U1 (
.CLK... | 8.089701 |
module Combiner #(
parameter WIDTH0 = 32
, parameter WIDTH1 = 32
) (
input iValid_AS0
, output oReady_AS0
, input [ WIDTH0-1:0] iData_AS0
, input iValid_AS1
, output oReady_AS1
, input [ W... | 7.230559 |
module CombinerN #(
parameter SIZE = 8
, parameter WIDTH = 32
) (
input [ SIZE-1:0] iValid_AS
, output [ SIZE-1:0] oReady_AS
, input [SIZE*WIDTH-1:0] iData_AS
, output oValid_BM
, input iReady_BM
, output [SIZE*WIDTH-1:0] oData_BM
);
... | 7.796902 |
module CombinerTest #(
parameter BURST = "yes"
);
ClockDomain c ();
reg iValid_AM0;
wire oReady_AM0;
reg [3:0] iData_AM0;
reg iValid_AM1;
wire oReady_AM1;
reg [3:0] iData_AM1;
wire oValid_BM;
reg iReady_BM;
wire [7:0] oData_BM;
wire wvld0;
wi... | 7.039629 |
module onepulse (
pb_debounced,
clock,
pb_one_pulse
);
input pb_debounced;
input clock;
output reg pb_one_pulse;
reg pb_debounced_delay;
always @(posedge clock) begin
pb_one_pulse <= pb_debounced & (!pb_debounced_delay);
pb_debounced_delay <= pb_debounced;
end
endmodule
| 7.208433 |
module master_control (
clk,
rst_n,
request,
ack,
data_in,
notice,
data,
valid,
request2s
);
input clk;
input rst_n;
input request;
input ack;
input [3-1:0] data_in;
output reg request2s;
output reg notice;
output reg [3-1:0] data;
output reg valid;
parameter sta... | 7.524136 |
module decoder (
in,
out
);
input [3-1:0] in;
output reg [7:0] out;
always @(*) begin
case (in)
3'b000: out = 8'b0000_0001;
3'b001: out = 8'b0000_0010;
3'b010: out = 8'b0000_0100;
3'b011: out = 8'b0000_1000;
3'b100: out = 8'b0001_0000;
3'b101: out = 8'b0010_0000;
... | 7.018254 |
module onepulse (
pb_debounced,
clock,
pb_one_pulse
);
input pb_debounced;
input clock;
output reg pb_one_pulse;
reg pb_debounced_delay;
always @(posedge clock) begin
pb_one_pulse <= pb_debounced & (!pb_debounced_delay);
pb_debounced_delay <= pb_debounced;
end
endmodule
| 7.208433 |
module decoder (
in,
out
);
input [3-1:0] in;
output reg [7:0] out;
always @(*) begin
case (in)
3'b000: out = 8'b0000_0001;
3'b001: out = 8'b0000_0010;
3'b010: out = 8'b0000_0100;
3'b011: out = 8'b0000_1000;
3'b100: out = 8'b0001_0000;
3'b101: out = 8'b0010_0000;
... | 7.018254 |
module slave_control (
clk,
rst_n,
request,
ack,
data_in,
notice,
valid,
data
);
input clk;
input rst_n;
input request;
input [3-1:0] data_in;
input valid;
output reg ack;
output reg notice;
output reg [3-1:0] data;
parameter state_wait_rqst = 2'b00;
parameter state_... | 7.868824 |
module seout (
input wire clk,
input wire rst,
input wire [63:0] input_update0,
input wire [63:0] input_update1,
input wire [63:0] input_update2,
input wire [63:0] input_update3,
input wire [63:0] input_update4,
input wire [63:0] input_update5,
input wire [63:0] input_update6,
in... | 7.596749 |
module combine_unit (
input wire clk,
input wire [31:0] update_A,
input wire [31:0] update_B,
output wire [31:0] combined_update
);
fp_add adder (
.aclk(clk),
.s_axis_a_tvalid(1'b1),
.s_axis_a_tdata(update_A),
.s_axis_b_tvalid(1'b1),
.s_axis_b_tdata(update_B),
.m_a... | 7.696525 |
module COMBLOGFETCH (
input [2:0] in,
output out
);
assign out = ~in[0] & ~in[1] & ~in[2];
endmodule
| 8.145752 |
module combLogic (
input wire IN_0,
input wire IN_1,
output wire OUT_0,
output wire OUT_1
);
wire net0;
AND_2_1 AND_2_1_inst_1 (
.IN_1(IN_1),
.IN_0(IN_0),
.OUT (OUT_0)
);
INV INV_inst (
.IN (IN_1),
.OUT(net0)
);
AND_2_1 AND_2_1_inst_2 (
.IN_1(IN_0),
... | 6.63935 |
module COMBLOGSTATE (
input [2:0] in,
input extra,
output [2:0] out
);
assign out[0] = ~in[0] & ~in[1] & ~in[2];
assign out[1] = extra & ~in[2] & ~in[1] & in[0];
assign out[2] = 0;
endmodule
| 6.576787 |
module Combo_CA (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
reg Y;
always @(A or B or C or D) begin
Y = (~(A | D)) & (B & C & ~D);
end
endmodule
| 7.179366 |
module combTb ();
reg clk, rst, start;
wire Done;
reg [3:0] N;
wire [14:0] answer;
combToplevel comb_tb (
clk,
rst,
start,
N,
Done,
answer
);
always repeat (5000) #30 clk = ~clk;
initial begin
clk = 1'b0;
start = 1'b1;
//ex 1
#95 N = 4'b0101; /... | 6.794759 |
module comb_behavior (
output reg Y,
input A,
B,
C,
D
);
always @(*) begin
Y <= (~(A | D)) & (B & C & (~D));
end
endmodule
| 7.546985 |
module comb_block_nonblock (
input a,
b,
c,
output reg x
);
// Blocking assignments
// always @(a, b, c)
// begin
// x = a;
// x = x ^ b;
// x = x | c;
// end
// Nonblocking assignments
// always @(a, b, c)
// begin
// x <= a;
// ... | 7.890423 |
module comb_dataflow (
output Y,
input A,
B,
C,
D
);
assign Y = (~(A | D)) & (B & C & (~D));
endmodule
| 8.663629 |
module top_module (
input [254:0] in,
output [ 7:0] out
);
always @(*) begin
out = 0;
for (int i = 0; i < 255; i++) out = out + in[i];
end
endmodule
| 7.203305 |
module comb_logic (
KEY0,
KEY1,
LED0
);
input wire KEY0;
input wire KEY1;
output wire LED0;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_2 = SYNTHESIZED_WIRE_0 & KEY1;
assign SYNTHESIZED_WIRE_1 = KEY0 & KEY1;
assign SYNTHESIZED... | 6.690498 |
module top (
input sys_clk,
output a,
output b,
output reg c
);
initial begin
c = 1'd0;
end
assign a = (~sys_clk);
assign b = c;
always @(*) begin
c = 1'd0;
if (a) begin
c = 1'd0;
end else begin
c = 1'd1;
end
end
endmodule
| 7.233807 |
module implements a comb filter using a RAM block and
// a single DSP48A core.
//
//
/*****************************************************************************/
module comb_M256_N1_iw5_0
(
input clk,
input sync_reset,
input [8:0] msetting,
input s_axis_tvalid,
input [47:0] s_axis_tdata,
output ... | 6.904081 |
module b1_mux_2_1_comb (
input d0,
input d1,
input sel,
output y
);
assign y = (sel & d1) | (~sel & d0);
endmodule
| 7.358998 |
module b1_mux_2_1_sel (
input d0,
input d1,
input sel,
output y
);
assign y = sel ? d1 : d0;
endmodule
| 6.765827 |
module b1_mux_2_1_index (
input [1:0] d,
input sel,
output y
);
assign y = d[sel];
endmodule
| 7.004677 |
module swa_input_port_arbiter #(
parameter ARBITER_WIDTH = 4,
parameter EXT_P_EN = 1,
parameter ARBITER_TYPE = "WRRA" // RRA, WRRA
) (
ext_pr_en_i, // it is used only if the EXT_P_EN is 1
clk,
reset,
request,
grant,
any_grant,
vc_weight_is_consumed, // only for WRRA
winne... | 8.676035 |
module swa_output_port_arbiter #(
parameter ARBITER_WIDTH = 4,
parameter ARBITER_TYPE = "WRRA" // RRA, WRRA
) (
weight_consumed, // only used for WRRA
clk,
reset,
request,
grant,
any_grant
);
input [ARBITER_WIDTH-1 : 0] request;
output [ARBITER_WIDTH-1 : 0] grant;
output an... | 8.153043 |
module comb_shift (
input [21:0] exp_in,
input ui_shift,
input [1:0] ui,
output [21:0] exp_out
);
assign exp_out = (!ui_shift) ? {exp_out} :
(ui == 2'b01) ? (exp_in << 1) :
(ui == 2'b10) ? (exp_in << 2) :
(ui == 2'b11) ? (exp_in << 3) : {exp_in};
endmodule
| 6.631678 |
module comb_simple (
input [1:0] KEY, // KEYs
output [9:0] LED // LEDs
);
wire a = ~KEY[0];
wire b = ~KEY[1];
// Basic gates AND, OR and NOT
assign LED[0] = a & b;
assign LED[1] = a | b;
assign LED[2] = ~a;
// XOR gates (useful for adders, comparisons,
// parity and control sum calculatio... | 8.095419 |
module mux (
output y,
input sel,
in0,
in1
);
wire tmp1, tmp0;
and (tmp1, sel, in1);
and (tmp0, ~sel, in0);
or (y, tmp1, tmp0);
endmodule
| 7.812393 |
module comb_Y1 (
output Y,
input A,
B,
C
);
assign Y = ((~A) & (~B) & C) | ((~A) & B & (~C)) | (A & (~B));
endmodule
| 7.057421 |
module comb_Y2 (
output Y,
input A,
B,
C,
D
);
assign Y = (~A) | (A & (~B) & C & D) | (A & B & (~C));
endmodule
| 7.59737 |
module COMIO1 (
input clk,
input rst_n,
input uart_rx,
output uart_tx
);
parameter CLK_FRE = 50; //MHz
localparam IDLE = 0;
localparam SEND = 1; //send the imformation
localparam WAIT = 2; //wait 1 second and send uart received data
reg [7:0] tx_data;
reg [7:0] tx_str;
reg tx_data_v... | 9.573689 |
module combo (
input a,
b,
c,
d,
e,
output reg z
);
always @(a or b or c or d or e) begin
z = ((a & b) | (c ^ d) & ~e);
end
endmodule
| 7.731128 |
module commandSelector (
input FPGA_CLK1_50,
input KEY,
input write,
input uart_data,
output reg LED,
output reg [7:0] command
);
always @(posedge FPGA_CLK1_50 or negedge KEY) begin
if (!KEY) LED <= 0;
else if (KEY & write) begin
case (uart_data)
10'h30: command <= 8... | 6.588938 |
module CommandShip draws the ships (current and spare) in the
// indicated position and direction. It also detects when an asteroid
// has hit the ship. The oActive signals is sent to the main module
// to indicate that the ship has been distroyed
//
//****************************************************************... | 7.252539 |
module command_buffer (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [39:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [39:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALT... | 6.994387 |
module command_control (
CBCLK,
CLRCLK,
CC,
PTT_out,
ATTEN,
TX_relay,
Rout,
RX_relay,
frequency_HZ,
ATTRLY,
RAND,
DITHER,
ref_ext,
source_122MHZ,
ADDRESS
);
input CBCLK;
input CLRCLK;
input CC; // Command & Control data in
output reg PTT_out;
outpu... | 8.167022 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.