code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module is the sub level RTL code of SDRAM Controller ASIC verilog
code. It will decode the uProcessor command, its a command interface block.
It will instantiate the following blocks in the ASIC:
1) Command Decoder
2) Internal Register
3) Command Acknowledge
4) Refresh Timer
Hossein Amidi
(C) April 2002
*... | 6.572195 |
module command_interface #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add... | 7.50016 |
module command_line ();
initial begin
if ($test$plusargs("CASE_1")) $display("Run by selectig case 1");
if ($test$plusargs("CASE_2")) $display("Run by selectig case 2");
end
endmodule
| 6.60445 |
module: command_parser
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module command_parser_tb;
// Inputs
reg drive_line;
reg [7:0] data_in;
// Outputs
wire [2:0] key_val;
wire pre... | 7.403306 |
module command_register (
input clk,
input rst_n,
input en,
input [7:0] data,
output [2:0] operation,
output [12:0] ir_addr
);
reg [15:0] cmd_reg, state;
assign operation = cmd_reg[15:13];
assign ir_addr = cmd_reg[12:0];
always @(posedge clk or negedge rst_n) begin
if (!rst_n) b... | 7.161234 |
module command_register_tb;
reg [3:0] IO;
reg CE;
reg WE;
reg CLE;
wire [3:0] command;
wire command_register_ready;
command_register U1 (
.IO(IO),
.CE(CE),
.WE(WE),
.CLE(CLE),
.command(command),
.command_register_ready(command_register_ready)
);
initial begin
CE... | 7.161234 |
module command_rom
#(
parameter SOURCE = "../rom_data/data.txt",
parameter ADDRESS_WIDTH = 8;
parameter COMMAND_WIDTH = 4,
parameter DEVICE_DATA_WIDTH = 8
)
(
input clk, reset_n,
input [ ADDRESS_WIDTH - 1: 0 ] address,
output [ COMMAND_... | 9.088897 |
module comma_edge_example ();
reg clk, reset, d;
reg q, q95;
// Verilog 2k example for usage of comma
always @(posedge clk, posedge reset) begin : V2K
if (reset) q <= 0;
else q <= d;
end
// Verilog 95 example for above code
always @(posedge clk or posedge reset) begin : V95
if (reset) q95 <... | 6.635108 |
module comma_example ();
reg a, b, c, d, e;
reg [2:0] sum, sum95;
// Verilog 2k example for usage of comma
always @(a, b, c, d, e) begin : SUM_V2K
sum = a + b + c + d + e;
end
// Verilog 95 example for above code
always @(a or b or c or d or e) begin : SUM_V95
sum95 = a + b + c + d + e;
end
... | 7.040673 |
module addbit (
a,
b,
ci,
sum,
co
);
// Input Ports Single line comment
input a;
input b;
input ci;
// Output ports
output sum;
output co;
// Data Types
wire a;
wire b;
wire ci;
wire sum;
wire co;
endmodule
| 7.120785 |
module configuration_memory #(
parameter NREG = 1,
parameter NBYTES = 4,
parameter [6:0] BASEADDR = 0
) (
input wire fx2Clk,
input wire reset,
input wire [6:0] chanAddr,
input wire [7:0] h2fData,
input wire h2fValid,
output wire h2fReady,
output wire [7:0] f2hData,
input wi... | 7.163412 |
module CommFPGA_FIFOwrapper8 (
input wire fx2Clk,
input wire reset,
// input wire [6:0] chanAddr,
input wire [7:0] h2fData,
input wire h2fValid,
output wire h2fReady,
output wire [7:0] f2hData,
output wire f2hValid,
input wire f2hReady,
input wire rd,
input wire wr,
in... | 6.630029 |
module commFPGA_fx2wrapper (
input wire fx2Clk, // externally buffered 48MHz clock from FX2
// FX2 interface -----------------------------------------------------------------------------
output wire [1:0] fx2Addr_out, // select FIFO: "10" for EP6OUT, "11" for EP8IN
inout wire [7:0] fx2Data_io, // ... | 7.216882 |
module.
// .mux input of 0 disconnects the commFPGA module from all output modules. While .mux = 0, any reads will return 0, any writes will not block.
//
// Dependencies:
//
// Instantiation template
// commFPGA_mux #(.NMUX(3)) FPGALink_mux (
// .mux (muxAddr),
// //input from commFPGA module
// .chanAddr ... | 7.841957 |
module commline_control;
localparam CHAR_LENGTH = 8;
//Length of one char
reg [8:0] comm_value_int;
real comm_value_real;
reg [CHAR_LENGTH*32 - 1:0] comm_value_str;
//Values inputted by command line
initial begin
if ($test$plusargs("HELLO")) begin
$display("HELLO inputted");
end else begin
... | 7.347133 |
module Debouncer (
output E,
input pb, // Push button
input clk
);
// Delay Parameter
parameter DELAY_7ms = 20'd350_000;
reg [19:0] SDC; // Signal Delay Counter
reg dpb; // Q of first flip flop
reg spb; // Q of second flip flop
reg [2:0] currentState;
initial begin
currentState = ... | 6.808208 |
module EightBitBinaryToBCD (
output reg [3:0] BCDDigitHundreds,
output reg [3:0] BCDDigitTens,
output reg [3:0] BCDDigitOnes,
output reg Done,
input [7:0] BinaryInput,
input Enable,
input clk
);
reg Enabled;
reg [7:0] Binary;
initial Enabled = 0;
always @(posedge clk) begin
if... | 7.025531 |
module DFF (
clk,
en,
d,
q
);
parameter WIDTH = 1;
input clk;
input en;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q; //={WIDTH{1'b0}};
always @(posedge clk) begin
if (en) q <= d;
end
endmodule
| 8.191977 |
module DFF2 (
clk,
rst,
en,
d,
q
);
parameter WIDTH = 1;
input clk;
input rst;
input en;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q; //={WIDTH{1'b0}};
always @(posedge clk) begin
if (rst) q <= {WIDTH{1'B0}};
else if (en) q <= d;
end
endmodule
| 6.772305 |
module muxx3 (
out,
hitA,
wf,
inA,
inB,
inF
);
parameter WIDTH = 1;
output [WIDTH-1:0] out;
input hitA;
input wf;
input [WIDTH-1:0] inA;
input [WIDTH-1:0] inB;
input [WIDTH-1:0] inF;
assign out = (hitA & ~wf) ? inA : 'z;
assign out = (~hitA & ~wf) ? inB : 'z;
assign out = ... | 7.866584 |
module optional_register (
clk,
dataIn,
dataOut
);
parameter WIDTH = 32;
parameter CNT = 0;
input clk;
input [WIDTH-1:0] dataIn;
output [WIDTH-1:0] dataOut;
reg [WIDTH-1:0] first;
reg [WIDTH-1:0] second;
always @(posedge clk) begin
first <= dataIn;
second <= first;
end
gener... | 8.000042 |
module FullAdder (
InputA,
InputB,
C,
Carry,
Sum
);
input InputA;
input InputB;
input C;
output Carry;
output Sum;
reg Carry;
reg Sum;
always @(*) begin
// the equations below can be derived from the truth table of a full adder
Sum = InputA ^ InputB ^ C;
Carry = ((Inpu... | 7.610141 |
module SixteenBitFullAdder (
InputA,
InputB,
C,
Carry,
Sum
);
input [15:0] InputA;
input [15:0] InputB;
input C;
output Carry;
output [15:0] Sum;
wire [14:0] carryWires;
generate
for (genvar i = 0; i < 16; i = i + 1) begin
case (i)
0: FullAdder FA0 (InputA[i], Inp... | 6.937409 |
module SixteenBitAddSub (
InputA,
InputB,
Mode,
Result,
Carry,
Overflow
);
input [15:0] InputA;
input [15:0] InputB;
input Mode;
output Carry;
output Overflow;
output [31:0] Result;
// XOR Interfaces: wires b0,b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15
wire [15:0] xorWi... | 6.781625 |
module SixteenBitModulus (
InputA,
InputB,
Result,
Error
);
input [15:0] InputA;
input [15:0] InputB;
output [31:0] Result;
wire [15:0] InputA;
wire [15:0] InputB;
reg [31:0] Result;
output Error;
reg Error;
integer i;
always @(InputA, InputB) begin
Result = InputA % InputB... | 6.626873 |
module SixteenBitDivision (
InputA,
InputB,
Result,
Error
);
input [15:0] InputA;
input [15:0] InputB;
output [31:0] Result;
wire [15:0] InputA;
wire [15:0] InputB;
reg [31:0] Result;
output Error;
reg Error;
integer i;
always @(InputA, InputB) begin
Result = InputA / Input... | 6.743996 |
module Mux16x1 (
channels,
select,
selected
);
input [15:0][31:0] channels; // 16 channels where each of the channels contain 32 bit number
input [15:0] select;
output [31:0] selected;
// A x 1 = A or A x 0 = 0
assign selected = ({32{select[15]}} & channels[15]) |
({32... | 6.918836 |
module Dec4x16 (
binary,
onehot
);
input [3:0] binary; // opcode
output [15:0] onehot; // 16 bit hot select being fed into a 16:1 MUX
assign onehot[0] = ~binary[3] & ~binary[2] & ~binary[1] & ~binary[0];
assign onehot[1] = ~binary[3] & ~binary[2] & ~binary[1] & binary[0];
assign onehot[2] = ~bi... | 7.711221 |
module breadboard (
InputA,
InputB,
Result,
OpCode,
Error
);
input [15:0] InputA;
input [15:0] InputB;
input [3:0] OpCode;
wire [15:0] InputA;
wire [15:0] InputB;
wire [ 3:0] OpCode;
output [1:0] Error;
reg [1:0] Error;
output [31:0] Result;
reg [31:0] Result;
// Control
... | 6.534342 |
module FullAdder (
InputA,
FeedBack,
C,
Carry,
Sum
);
input InputA;
input FeedBack;
input C;
output Carry;
output Sum;
reg Carry;
reg Sum;
always @(*) begin
// the equations below can be derived from the truth table of a full adder
Sum = InputA ^ FeedBack ^ C;
Carry = ... | 7.610141 |
module SixteenBitFullAdder (
InputA,
FeedBack,
C,
Carry,
Sum
);
input [15:0] InputA;
input [15:0] FeedBack;
input C;
output Carry;
output [15:0] Sum;
wire [14:0] carryWires;
generate
for (genvar i = 0; i < 16; i = i + 1) begin
case (i)
0: FullAdder FA0 (InputA[i],... | 6.937409 |
module SixteenBitAddSub (
InputA,
FeedBack,
modeSUB,
outputADDSUB,
Carry,
ADDerror
);
input [15:0] InputA;
input [15:0] FeedBack;
input modeSUB;
output Carry;
output ADDerror;
output [31:0] outputADDSUB;
// XOR Interfaces: wires b0,b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b... | 6.781625 |
module SixteenBitModulus (
InputA,
FeedBack,
outputMOD,
MODerror
);
input [15:0] InputA;
input [15:0] FeedBack;
output [31:0] outputMOD;
wire [15:0] InputA;
wire [15:0] FeedBack;
reg [31:0] outputMOD;
output MODerror;
reg MODerror;
integer i;
always @(InputA, FeedBack) begin
... | 6.626873 |
module SixteenBitDivision (
InputA,
FeedBack,
outputDIV,
DIVerror
);
input [15:0] InputA;
input [15:0] FeedBack;
output [31:0] outputDIV;
wire [15:0] InputA;
wire [15:0] FeedBack;
reg [31:0] outputDIV;
output DIVerror;
reg DIVerror;
integer i;
always @(InputA, FeedBack) begin
... | 6.743996 |
module NORER (
InputA,
FeedBack,
outputNOR
);
input [15:0] InputA;
input [15:0] FeedBack;
output [31:0] outputNOR;
wire [15:0] InputA;
wire [15:0] FeedBack;
reg [31:0] outputNOR;
always @(*) begin
outputNOR[15:0] = ~(InputA | FeedBack);
outputNOR[31:16] = 16'b0000000000000000;
e... | 6.612467 |
module NOTER (
Current,
outputNOT
);
input [31:0] Current;
output [31:0] outputNOT;
wire [31:0] Current;
reg [31:0] outputNOT;
always @(*) begin
outputNOT = ~(Current);
end
endmodule
| 7.420342 |
module DFF (
Clk,
In,
Out
);
input Clk;
input In;
output Out;
reg Out;
// posedge means the transition from 0 to 1
always @(posedge Clk) Out = In;
endmodule
| 8.102343 |
module Mux16x1 (
channels,
onehot,
selected
);
input [15:0][31:0] channels; // 16 channels where each of the channels contain 32 bit number
input [15:0] onehot;
output [31:0] selected;
// A x 1 = A or A x 0 = 0
assign selected = ({32{onehot[15]}} & channels[15]) |
({32... | 6.918836 |
module Dec4x16 (
Opcode,
onehot
);
input [3:0] Opcode; // opcode
output [15:0] onehot; // 16 bit hot select being fed into a 16:1 MUX
assign onehot[0] = ~Opcode[3] & ~Opcode[2] & ~Opcode[1] & ~Opcode[0];
assign onehot[1] = ~Opcode[3] & ~Opcode[2] & ~Opcode[1] & Opcode[0];
assign onehot[2] = ~Op... | 7.711221 |
module breadboard (
Clk,
InputA,
Result,
OpCode,
Error
);
input [15:0] InputA;
input [3:0] OpCode;
wire [15:0] InputA;
wire [ 3:0] OpCode;
output [1:0] Error;
reg [1:0] Error;
output [31:0] Result;
reg [31:0] Result;
// Control
wire [15:0][31:0] channels;
wire [15:0] oneho... | 6.534342 |
module commonloop #(
parameter KEY_SIZE = 128,
parameter BLOCK_SIZE = 128,
parameter NROUND = 16
) (
input wire [BLOCK_SIZE-1:0] a_in,
input wire [BLOCK_SIZE/16-1:0] rc1_in,
input wire [BLOCK_SIZE/16-1:0] rc2_in,
input wire [KEY_SIZE-1:0] k_in,
input mode,
output wire [BLOCK_SIZE-1:0... | 7.422667 |
module DFF #(
parameter data_width = 14
) (
input clk,
rst,
input [data_width-1:0] d,
output reg [data_width-1:0] q
);
always @(posedge clk or posedge rst) begin
if (rst) q <= 0;
else q <= d;
end
endmodule
| 9.250563 |
module shift_7 #(
parameter data_width = 14
) (
input [data_width-1:0] din,
input rst,
clk,
output wire [data_width-1:0] dout
);
reg [data_width-1:0] t0, t1, t2, t3, t4, t5, t6;
always @(posedge clk or posedge rst) begin
if (rst) begin
t0 <= 0;
t1 <= 0;
t2 <= 0;
t3 ... | 7.917369 |
module shift_3 #(
parameter data_width = 14
) (
input [data_width-1:0] din,
input rst,
clk,
output wire [data_width-1:0] dout
);
reg [data_width-1:0] t0, t1, t2;
always @(posedge clk or posedge rst) begin
if (rst) begin
t0 <= 0;
t1 <= 0;
t2 <= 0;
end else begin
... | 8.388976 |
module shift_4 #(
parameter data_width = 14
) (
input [data_width-1:0] din,
input rst,
clk,
output wire [data_width-1:0] dout
);
reg [data_width-1:0] t0, t1, t2, t3;
always @(posedge clk or posedge rst) begin
if (rst) begin
t0 <= 0;
t1 <= 0;
t2 <= 0;
t3 <= 0;
en... | 8.08761 |
module shift_13 #(
parameter data_width = 14
) (
input [data_width-1:0] din,
input rst,
clk,
output wire [data_width-1:0] dout
);
reg [data_width-1:0] t0, t1, t2, t3, t4, t5, t6;
reg [data_width-1:0] t7, t8, t9, t10, t11, t12;
always @(posedge clk or posedge rst) begin
if (rst) begin
... | 7.453494 |
module shift_14 #(
parameter data_width = 14
) (
input [data_width-1:0] din,
input rst,
clk,
output wire [data_width-1:0] dout
);
reg [data_width-1:0] t0, t1, t2, t3, t4, t5, t6;
reg [data_width-1:0] t7, t8, t9, t10, t11, t12, t13;
always @(posedge clk or posedge rst) begin
if (rst) begi... | 7.708539 |
modules used //
// by higher level modules in RS Decoder //
//******************************************************//
//*************************//
// Multiplexer 2 to 1 5bit //
//*************************//
module mux2_to_1(in1, in2 , out, sel);
input [4:0] in1, in2;
input sel;
output [4:0] out;
reg ... | 7.262409 |
module node #(
parameter DATA_WIDTH = 8,
parameter LOW_MUX = 1, // disable low output
parameter HI_MUX = 1 // disable hight output
) (
input [DATA_WIDTH-1:0] data_a,
input [DATA_WIDTH-1:0] data_b,
output reg [DATA_WIDTH-1:0] data_hi,
output reg [DATA_WIDTH-1:0] data_lo
);
reg sel0;
... | 8.085994 |
module common_sub (
output reg y,
z,
input a,
b,
c,
d
);
always @(*) begin
y = (a & d) | c;
z = (a & d) ^ b;
end
endmodule
| 7.267968 |
module rs232_loopback #(
parameter integer PERIOD = 10
) (
input clk,
input rx,
input rx_hold,
output tx,
output diag
);
wire rx_ready;
reg [7:0] sync_tx_data;
wire [7:0] sync_rx_data;
reg [7:0] pipe_tracker = 8'b0;
rs232_comms #(
.PERIOD(PERIOD)
) comms (
.clk(clk),
... | 7.040352 |
module rs232_comms #(
parameter integer PERIOD = 10
) (
input clk,
input rx,
input rx_hold,
output tx,
output reg diag = 1'b0,
input [7:0] tx_byte,
input tx_ready,
output [7:0] rx_byte,
output rx_ready
);
wire rx_stb;
wire [7:0] rx_data;
wire tx_stb;
wire [7:0] tx_data;... | 6.882264 |
module comms_master_testbench;
reg r_clock = 0;
always #1 r_clock <= !r_clock;
reg r_setup = 0;
comms_master COMM_MASTER_INST (
//Clock
.i_clock(r_clock),
//Control signals
.i_setup(r_setup),
/*,
input i_activate,
input i_shutdown,
*/
//SPI (Named to match with H... | 7.237372 |
module commul_tb ();
reg rst, clk;
reg [35:0] dir, dii;
reg [6:0] twsel;
wire [35:0] dor, doi;
commul a (
rst,
clk,
dir,
dii,
twsel,
dor,
doi
);
initial begin
$dumpfile("commul.vcd");
$dumpvars(0, commul_tb);
end
initial begin
clk = 0;
rst ... | 7.256628 |
module commutation1 (
clock,
reset,
halla,
hallb,
hallc,
ha,
hb,
hc,
la,
lb,
lc,
toggle
);
parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100, F = 3'b101;
input clock;
input reset;
input halla;
input hallb;
input hallc;
output ha;
outpu... | 6.660575 |
module commutatore_2vie_nbit (
z,
x,
y,
alpha
);
parameter N = 32;
output reg [N-1:0] z;
input [N-1:0] x;
input [N-1:0] y;
input alpha;
always @(alpha or x or y) begin
case (alpha)
1'b0: z <= #2 x;
1'b1: z <= #2 y;
endcase
end
endmodule
| 7.262991 |
module commutatore_3vie_nbit (
z,
x,
y,
w,
alpha
);
parameter N = 32;
output reg [N-1:0] z;
input [N-1:0] x;
input [N-1:0] y;
input [N-1:0] w;
input [1:0] alpha;
always @(alpha or x or y or w) begin
case (alpha)
2'b00: z <= #2 x;
2'b01: z <= #2 y;
2'b10: z <= ... | 6.847691 |
module commutatore_8vie_nbit (
z,
x1,
x2,
x3,
x4,
x5,
x6,
x7,
x8,
alpha
);
parameter N = 20;
output reg [N-1:0] z;
input [N-1:0] x1;
input [N-1:0] x2;
input [N-1:0] x3;
input [N-1:0] x4;
input [N-1:0] x5;
input [N-1:0] x6;
input [N-1:0] x7;
input [N-1:0] x8;
... | 7.199577 |
module commutStage2 (
input wire clk,
input wire reset,
input wire [1:0] mux_1_out,
input wire signed [31:0] data_in_0,
input wire signed [31:0] data_in_1,
input wire signed [31:0] data_in_2,
input wire signed [31:0] data_in_3,
output reg signed [31:0] output_0,
output reg signed ... | 6.562458 |
module comm_coordinator_bkb_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 6.893636 |
module comm_coordinator_bkb (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.893636 |
module comm_coordinator_dEe_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 6.893636 |
module comm_coordinator_dEe (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.893636 |
module comm_interface #(
parameter OUTPUT_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire rxd,
output wire txd,
output reg wr_enable,
output reg [11:0] wr_addr,
output wire [OUTPUT_WIDTH-1:0] wr_data,
output wire [11:0] step,
output wire [11:0] range
);
// TODO: Up... | 7.33648 |
module comm_recv #(
parameter modtype = 1
) (
input CLK,
input RST,
output wr_en,
output [127:0] dout,
input full,
input [7:0] ad1,
input [7:0] ad2,
input ad_valid,
output valid_raw,
output [5:0] raw
);
localparam width = 11;
wire ce3 = 1'... | 7.137554 |
module comm_temperature_measurement (
input clk,
output reg [15:0] tx_temp
);
wire drdy;
wire [15:0] do;
xadc_wiz_0 xadc_blk (
.daddr_in (7'd0),
.dclk_in (clk),
.den_in (1'b1),
.di_in (16'd0),
.dwe_in (1'b0),
.vp_in (),
.vn_in (),
.busy_out (),
.channel_out (),
.do_out (do),
.drdy_out (drdy... | 7.411306 |
module COMM_VH (
input clk,
input rst,
input enable,
output VSYNC,
output HSYNC
);
parameter FRM = 3;
parameter VBLK = 100;
parameter HBLK = 20;
parameter V_BP = 5;
parameter V_FP = 5;
parameter H_BP = 0;
parameter H_FP = 0;
parameter H_WIDTH = 2448;
parameter V_WIDTH = 2048;
... | 7.230166 |
module comm_writer_bufs_bkb_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 512;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" ... | 6.533984 |
module comm_writer_bufs_bkb (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd512;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - ... | 6.533984 |
module Comp0 (
input [63:0] B,
output Zero
);
assign Zero = (B == 0);
endmodule
| 6.913603 |
module COMP0_8 (
input [7:0] a,
output reg z
);
always @(*) begin
if (a == 0) z = 1;
else z = 0;
end
endmodule
| 7.150727 |
module comp1 (
input wire i0,
input wire i1,
output reg out
);
reg p0, p1;
always @(i0, i1) begin
p0 = ~i0 & ~i1;
p1 = i0 & i1;
out = p0 | p1;
end
endmodule
| 6.986199 |
module implements a compressor for rectangular signals. The input
// magnitude is estimated and the required gain is obtained from a ROM and
// applied to multipliers for the X and Y paths. The ROM is loaded via the
// CIN input and consists of 64 8-bit entries formatted as follows:
//
// 7 6 5 4 3 2 1 ... | 6.904081 |
module implements a compressor for rectangular signals. The input
// magnitude is estimated and the required gain is obtained from a ROM and
// applied to multipliers for the X and Y paths. The ROM is loaded via the
// CIN input and consists of 128 8-bit entries formatted as follows:
//
// 7 6 5 4 3 2 1... | 6.904081 |
module comp1_tb;
reg x;
reg y;
wire z;
comp1 circuit1 (
.i0 (x),
.i1 (y),
.out(z)
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, comp1_tb);
x = 0;
y = 0;
#20;
x = 1;
#20;
y = 1;
#20;
x = 0;
#40;
end
initial begin
$monitor("x=%d... | 6.593946 |
module Comp2s #(
////////////////////////////////////////////////////
// Parameters
parameter width = 4 //input bit width
) (
////////////////////////////////////////////////////
// Ports
input [width-1:0] IN,
output [width-1:0] OUT
);
//////////////////////////////////////////////////... | 6.510285 |
module HA (
input A,
B,
output S,
Co
);
assign S = A ^ B;
assign Co = A & B;
endmodule
| 9.138493 |
module
// Module Name: comp3
// Revision 0.01 - File Created
//////////////////////////////////////////////////////////////////////////////////
module comp3(a0,a1,a2,b0,b1,b2,l,e,g);
input a0,a1,a2,b0,b1,b2;
output l,e,g;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w... | 6.999332 |
module
// Module Name: comp3
// Revision 0.01 - File Created
//////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module comp3_tb;
// Inputs
reg a0;
reg a1;
reg a2;
reg b0;
reg b1;
reg b2;
// Ou... | 6.999332 |
module COMP4to2 (
X1,
X2,
X3,
X4,
Cin,
Cout,
Sum,
Carry
);
input X1, X2, X3, X4, Cin;
output Cout, Sum, Carry;
assign Sum = X1 ^ X2 ^ X3 ^ X4 ^ Cin;
assign Carry = ((X1 ^ X2 ^ X3 ^ X4) & Cin) | (~(X1 ^ X2 ^ X3 ^ X4) & X4);
assign Cout = ((X1 ^ X2) & X3) | (~(X1 ^ X2) & X1... | 6.548867 |
module comparator_4_to_1 (
input [13:0] min_distance_1,
input [13:0] min_distance_2,
input [13:0] min_distance_3,
input [13:0] min_distance_4,
input [ 8:0] new_1,
input [ 8:0] new_2,
input [ 8:0] new_3,
input [ 8:0] new_4,
output reg [13:0] min_distance,
output reg [ 8:0] New
);... | 7.051026 |
module comp8 (
a,
b,
e,
l,
g
);
input [7:0] a, b;
output e, l, g;
wire [7:0] temp, sum;
wire cout;
assign temp = (a & b) | (~a & ~b);
assign e = &temp;
//cla8(cout,s,a,b,cin);
cla8 c0 (
cout,
sum,
a,
~b,
1
);
assign g = cout & 1;
assign l = (~e)... | 6.61929 |
module compact (
a1,
b1,
a2,
b2,
A_out,
B_out
);
input a1, b1, a2, b2;
output A_out, B_out;
wire g2 = a2 & b2;
wire p2 = a2 ^ b2;
assign A_out = g2 | (p2 & a1);
assign B_out = g2 | (p2 & b1);
endmodule
| 6.969285 |
module CompactGeneticAlgorithm #(
parameter IndividualWidth = 32,
parameter FitnessWidth = 16,
parameter Resolution = 10,
parameter TaxWidth = 1
) (
input clk,
input rst,
input fitness_end,
input [FitnessWidth-1:0] fitness,
input [IndividualWidth*Resolution-1:0] seed,
output reg ... | 6.740922 |
module CompactGeneticAlgorithmTest;
parameter IndividualWidth = 32;
parameter FitnessWidth = 16;
parameter Resolution = 10;
parameter TaxWidth = 1;
reg clk;
reg rst;
reg fitness_end;
reg [FitnessWidth-1:0] fitness;
reg [IndividualWidth*Resolution-1:0] seed;
wire [IndividualWidth-1:0] individual;
... | 6.740922 |
module compact_cnn (
clk,
resetn,
o_rd_rdy,
i_start,
i_we,
i_waddr,
i_din,
o_we,
o_dout,
o_cycles,
o_commands,
o_fc_cycles,
i_debug_rdy,
o_debug_vld,
o_fill,
i_fifo_empty,
i_fifo_low,
o_fifo_rd,
i_fifo_dout,
o_status
);
input clk;
input... | 7.072308 |
module compact_cnn (
clk,
resetn,
o_rd_rdy,
i_start,
i_we,
i_waddr,
i_din,
o_we,
o_dout,
o_cycles,
o_commands,
o_fc_cycles,
i_debug_rdy,
o_debug_vld,
o_fill,
i_fifo_empty,
i_fifo_low,
o_fifo_rd,
i_fifo_dout,
o_status
) /* synthesis syn_bla... | 7.072308 |
module COMPADC (
clk,
rst,
ramp_ref,
dpwm_duty,
dpwm
);
input clk; // input reference clock
input rst; // master reset
input unsigned [10:0] ramp_ref; // reference ramp
input unsigned [10:0] dpwm_duty; // dpwm phase duty
output dpwm; // dpwm
reg dpwm_toggle; // temp register for... | 6.622599 |
module sumador_4bits_ripple (
input [3:0] A,
input [3:0] B,
input Ci,
output [3:0] S,
output Co
);
wire C1, C2, C3;
sumador_completo sc0 (
A[0],
B[0],
Ci,
S[0],
C1
);
sumador_completo sc1 (
A[1],
B[1],
C1,
S[1],
C2
);
sumador_co... | 6.746912 |
module sumador_4bits_CLA (
input [3:0] A,
input [3:0] B,
input Ci,
output [3:0] S,
output Co
);
wire [3:0] P, G;
wire [4:1] C;
wire temp;
medio_sumador ms0 (
A[0],
B[0],
P[0],
G[0]
);
medio_sumador ms1 (
A[1],
B[1],
P[1],
G[1]
);
medio_... | 6.746912 |
module comparador (
diff,
sinal,
igual,
ate3,
errada
);
// Define as entradas
input [3:0] diff;
input sinal; // 1 == NEGATIVO
// Define as saídas
output igual, ate3, errada;
// Define os fios
wire SINAL_AND_DIFF3_AND_DIFF2_AND_DIFF1, SINAL_AND_DIFF3_AND_DIFF2_AND_DIFF0, NOT_SINAL_AN... | 7.425908 |
module comparador (
syncmulti,
sync
);
output wire sync;
output wire syncmulti;
integer aux;
reg synctrama;
reg syncmultitrama;
clockdemux4M clkd ();
shift_register_SIPO srSIPO ();
aligndemux algnd ();
cnt8demux cnt8 ();
assign sync = synctrama;
assign syncmulti = syncmultitrama;
in... | 7.425908 |
module Comparador4bits (
//declaracion de los vectores
input [3:0] input1,
input2,
//salidas representando que operacion logica se cumple
output reg [2:0] output_comparador
);
/*assign output_comparador[0] = input1 > input2;
assign output_comparador[1] = input1 == input2;
assign output_compara... | 7.21223 |
module Comparador4bits_tb ();
reg [3:0] input1_reg, input2_reg;
wire [2:0] output_comparador_wire;
Comparador4bits test (
.input1(input1_reg),
.input2(input2_reg),
.output_comparador(output_comparador_wire)
);
initial begin
input1_reg = 15;
input2_reg = 0;
#20 input1_reg = ... | 7.21223 |
module ComparadorTest (
input clk,
input btnl,
input btnd,
input btnr,
input btnp,
input [3:0] speed,
output [7:3] led,
output [6:0] seg,
output [3:0] an
);
wire [3:0] bebida;
wire [3:0] total;
wire [3:0] cambio;
reg [3:0] display;
wire cancel_wire;
wire hundred_wire;
... | 6.863298 |
module comparador_4bits (
A,
B,
out
);
input [3:0] A, B;
output out;
wire xnor1, xnor2, xnor3, xnor4;
wire and1, and2;
// so e verdade quando os bits sao iguais
assign xnor1 = ~(A[3] ^ B[3]);
assign xnor2 = ~(A[2] ^ B[2]);
assign xnor3 = ~(A[1] ^ B[1]);
assign xnor4 = ~(A[0] ^ B[0]);
... | 8.919392 |
module Comparador_Mayor (
input wire CLK,
input wire [7:0] A,
input wire [7:0] B,
output reg Out
);
always @(posedge CLK)
if (A > B) Out <= 1'b1;
else Out <= 1'b0;
endmodule
| 8.872056 |
module: Comparador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Comparador_TB;
// Inputs
reg [7:0] A;
reg [7:0] B;
reg [7:0] C;
reg [7:0] D;
reg [7:0] E;
// Outputs
wire... | 6.835169 |
module ComparaExponenti (
exponenti,
valoare,
exponenti_out
);
input wire [9:0] exponenti;
output reg [5:0] valoare;
output reg [9:0] exponenti_out;
reg [4:0] exp1, exp2;
always @(exponenti) begin
exp1 = exponenti[9:5];
exp2 = exponenti[4:0];
valoare = 5'b0;
exponenti_out = 10'b0... | 6.892416 |
module comparator1bit (
input a,
input b,
output g,
output e,
output s
);
assign g = a & (~b);
assign e = a ~^ b;
assign s = (~a) & b;
endmodule
| 7.319785 |
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