code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module comparator2 (
input [15:0] ip1,
input [15:0] ip2,
output [15:0] mux_out
);
assign mux_out = ($signed(ip1) >= $signed(ip2)) ? ip1 : ip2;
endmodule
| 8.336752 |
module comparator32 (
A,
B,
Gt,
Eq,
Lt
);
input [31:0] A, B;
output Gt, Eq, Lt;
wire gto1,gto2,gto3,gto4,gto5,gto6,gto7,gto8,gto9,gto10,gto11,gto12,gto13,gto14,gto15,gto16,
gto17,gto18,gto19,gto20,gto21,gto22,gto23,gto24,gto25,gto26,gto27,gto28,gto29,gto30,gto31;
wire eqo1,eqo2,eqo3,eq... | 7.118538 |
module Comparator32b (
input wire [31:0] A,
input wire [31:0] B,
output wire ZF,
output reg SLTu,
SLT
);
wire [7:0] zf;
wire [7:0] sltu;
wire [7:0] slt;
Comparator4b c0 (
.A(A[3:0]),
.B(B[3:0]),
.ZF(zf[0]),
.SLTu(sltu[0]),
.SLT(slt[0])
);
Comparator4b c1 (... | 6.533766 |
module Comparator3Bit (
input [2:0] A,
input [2:0] B,
input L,
input E,
input G,
output LT,
output EQ,
output Gt
);
wire notA[2:0], notB[2:0];
not n0 (
notA[0], A[0]
), n1 (
notA[1], A[1]
), n2 (
notA[2], A[2]
), n3 (
notB[0], B[0]
), n4 (
notB[... | 7.11458 |
module Comparator4b (
input wire [3:0] A,
input wire [3:0] B,
output wire ZF,
SLTu,
SLT
);
wire a_xor_b_bar0;
wire a_xor_b_bar1;
wire a_xor_b_bar2;
wire a_xor_b_bar3;
wire a_bar_and_b0;
wire a_bar_and_b1;
wire a_bar_and_b2;
wire a_bar_and_b3;
assign a_xor_b_bar0 = ~(A[0] ^ B[0]);... | 6.664239 |
module Comparator4bits (
inA,
inB,
x,
y,
z
);
input [3:0] inA, inB;
output reg x, y, z;
always @(inA, inB) begin
if (inA > inB) begin
x = 1;
y = 0;
z = 0;
end else if (inA < inB) begin
y = 1;
x = 0;
z = 0;
end else begin
z = 1;
x = ... | 7.53827 |
module Comparator4bits_tb;
// set input as register and output as wires
register [3:0] inA, inB;
wire x, y, z;
//instantiate design code
Comparator4bits testing (
inA,
inB,
x,
y,
z
);
//Test vectors start here
initial begin
//initialize all inputs
#0 inA = 4'b00;... | 7.53827 |
module Comparator8Bit (
inputP,
inputQ,
pLessThanQ,
pEqualToQ,
pGraterGreaterThanQ
);
input [7:0] inputP;
input [7:0] inputQ;
output pLessThanQ;
output pEqualToQ;
output pGraterGreaterThanQ;
wire lt0, eq0, gt0, lt1, eq1, gt1;
wire [2:0] endA;
buf (endA[2], 1'b0);
buf (endA[1], in... | 6.801579 |
module ComparatorEQ (
input wire [31:0] S, // Subtração de A por B
output wire EQ // Saída resultado
);
assign EQ = ~(|S); // NOR de 32 entradas, realizada com cada um dos bits
// Caso um único bit seja 1, a saída já será 0.
endmodule
| 8.245862 |
module ComparatorEQ_TB ();
reg [31:0] S; // Subtração A - B
reg correct; // Valor correto
wire EQ; // Valor entregue pelo módulo
integer i, errors; // Contadores
task Check;
input xpectEQ;
if (EQ != xpectEQ) begin
$display("Error S: %32b, xpect: %b", S, EQ);
errors = errors + 1;
e... | 7.005171 |
module comparatorgen_st #(
parameter NBITS = 16
) (
output r,
input [NBITS-1:0] a,
input [NBITS-1:0] b
);
wire [NBITS-1:0] iresult;
genvar k;
generate
for (k = 0; k < NBITS; k = k + 1) begin : blk
xor c1 (iresult[k], a[k], b[k]);
end
endgenerate
// Reduction plus negation
as... | 6.805788 |
module ComparatorLTSigned (
input wire A_S,
B_S,
S_S,
EQ, // Entradas de sinal e igualdade
output wire R // Saída
);
assign R = (A_S & ~B_S) | (~EQ & S_S) & (~B_S | A_S); // Expressão lógica derivada de tabela verdade
endmodule
| 7.489244 |
module ComparatorLTSigned_TB ();
reg signed [31:0] A, B; // A, B
wire [31:0] S; // subtração A - B
reg correct; // Valor correto
wire EQ, COUT, LESS; // Valores entregues por módulos, igualdade, Carry out e Resultado
integer i, j, errors; // Contadores
task Check;
input xpectLESS;
if (LESS != ... | 7.489244 |
module ComparatorLTUnsigned (
input wire COUT,
EQ, // Entradas COUT e igualdade
output wire R // Saída
);
assign R = ~(COUT | EQ); // Expressão lógica derivada de tabela verdade
endmodule
| 7.67118 |
module ComparatorLTUnsigned_TB ();
reg [31:0] A, B; // A, B
wire [31:0] S; // Subtração A - B
reg correct; // Valor correto
wire EQ, COUT, LESS; // Valores entregues por módulos, igualdade, Carry out e Resultado
integer i, j, errors; // Contadores
task Check;
input xpectLESS;
if (LESS != xpect... | 7.67118 |
module comparators (
input module_clk, //系统时钟
input module_rst_n, //系统服务信号
input din_val, //输入数据有效标志
input din_a, //输入的数据a
input din_b, //输入的数据b
output reg [7:0] dout_min, //输出最小值
output reg [7:0] dout_max //输出最大值
);
//有效数据滞后于请求信号一个时钟周期,所以数据有效信号在此延时一拍
always @(posedg... | 7.578044 |
module comparator_16bit (
X,
Y,
lt,
gt,
eq
); //Cascading 4-bit comparators to make 16-bit
input [15:0] X;
input [15:0] Y;
output wire lt, gt, eq;
//Initialize 16 bits from 4-bit comparator
wire [2:0] lt_gt_eq1, lt_gt_eq2, lt_gt_eq3, lt_gt_eq4;
wire [5:0] out;
// lt = [2] | gt = [1] ... | 6.546858 |
module comparator_18 (
input z,
input n,
input v,
input [1:0] alufn,
output reg out
);
reg i;
reg j;
always @* begin
i = n ^ v;
j = i | z;
out = 1'h0;
case (alufn)
2'h2: begin
out = i;
end
2'h1: begin
out = z;
end
2'h3: beg... | 6.589086 |
module comparator_1b (
input i_A,
i_B,
output o_more,
o_less,
o_equal
);
wire i_A_bar, i_B_bar;
not_1b not1 (
i_A,
i_A_bar
);
not_1b not2 (
i_B,
i_B_bar
);
and_1b and1 (
i_A,
i_B_bar,
o_more
);
and_1b and2 (
i_A_bar,
i_B,
... | 7.344561 |
module comparator_1bit (
in1,
in2,
greater,
less,
equal
);
input in1, in2;
output greater, less, equal;
wire in1, in2, greater, less, equal;
xnor x1 (equal, in1, in2);
and g1 (greater, in1, ~in2);
and l1 (less, ~in1, in2);
endmodule
| 7.344561 |
module comparator_1_bit (
enable,
in1,
in2,
in1_greater,
in2_greater,
equal
);
input enable, in1, in2;
output in1_greater, in2_greater, equal;
wire enable, in1, in2, in1_greater, in2_greater, equal;
wire out_xnor;
and a1 (in1_greater, in1, ~in2, enable);
and a2 (in2_greater, ~in1,... | 6.727229 |
module comparator_1_bit_tb ();
reg input1, input2, enable;
wire in1_gr8, in2_gr8, equality;
//comparator_1_bit c1(.in1(input1),.in2(input2),.enable(enable),.in1_greater(in1_gr8),.in2_greater(in2_gr8),.equal(equality));
comparator_1_bit c1 (
enable,
input1,
input2,
in1_gr8,
in2_gr8... | 6.727229 |
module OneDigitComparator (
input A,
B,
output F1,
F2,
F3 //F1 for A>B, F2 for A==B and F3 for A<B
);
//reg G1,G2,G3;
and n1 (F1, A, ~B);
and n2 (F3, ~A, B);
nor n3 (F2, F1, F3);
endmodule
| 6.968363 |
module comparator_24 (
input z,
input n,
input v,
input [1:0] alufn,
output reg out
);
reg i;
reg j;
always @* begin
i = n ^ v;
j = i | z;
out = 1'h0;
case (alufn)
2'h2: begin
out = i;
end
2'h1: begin
out = z;
end
2'h3: beg... | 6.643892 |
module comparator_2cen_16bit (
b,
index,
a_0,
a_1
);
output signed [15:0] b;
output index;
input signed [15:0] a_0;
input signed [15:0] a_1;
assign l = (a_0 > a_1) ? a_0 : a_1;
assign index = (a_0 > a_1) ? 0 : 1;
endmodule
| 7.506919 |
module TwoDigitComparator (
input A1,
A2,
B1,
B2,
output F1,
F2,
F3
);
wire G1, G2;
OneDigitComparator OneDigitComparator_1 (
A1,
B1,
F11,
F12,
F13
);
OneDigitComparator OneDigitComparator_2 (
A2,
B2,
F21,
F22,
F23
);
... | 7.106503 |
module comparator_30 (
output reg out,
input [5:0] alufn,
input z,
input v,
input n
);
always @* begin
case (alufn[1+1-:2])
2'h1: begin
out = z;
end
2'h2: begin
out = n ^ v;
end
2'h3: begin
out = z | (n ^ v);
end
default: be... | 6.701284 |
module comparator32 (
input [31:0] a,
b,
output reg o
);
always @(*) o = a == b ? 1 : 0;
endmodule
| 7.118538 |
module comp_32_bit_v2 (
A,
B,
gt,
eq,
lt
);
input [31:0] A, B;
output gt, eq, lt;
wire [1:0] gtmp, etmp, ltmp;
comp_16_bit cp16A (
A[31:16],
B[31:16],
gtmp[1],
etmp[1],
ltmp[1]
);
comp_16_bit cp16B (
A[15:0],
B[15:0],
gtmp[0],
etmp[0]... | 6.561314 |
module comparator_35 (
input [7:0] a,
input [7:0] b,
input [2:0] alufn,
output reg [7:0] out
);
reg z;
reg n;
reg v;
wire [8-1:0] M_adddd_out;
wire [1-1:0] M_adddd_z;
wire [1-1:0] M_adddd_v;
wire [1-1:0] M_adddd_n;
adder_34 adddd (
.alufn(alufn[0+0-:1]),
.a(a[0+7-:8]),
... | 6.511118 |
module: Comparator_3_bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module comparator_3bits_tb;
// Inputs
reg [2:0] A;
reg [2:0] B;
reg l;
reg e;
reg g;
// Outputs
wire lt;
... | 7.72212 |
module Comparator_3_bits (
input [2:0] A,
input [2:0] B,
input l,
input e,
input g,
output lt,
output eq,
output gt
);
wire pre_eq, pre_lt, pre_gt;
wire [2:0] xnors;
// The three xnors of each two bits
xnor x0 (xnors[0], A[0], B[0]), x1 (xnors[1], A[1], B[1]), x2 (xnors[2], A[2]... | 6.524598 |
module: magnitude_3bit_comparator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module comparator_3_tb;
// Inputs
reg [2:0] A;
reg [2:0] B;
// Outputs
wire L;
wire E;
wire G;
/... | 7.349349 |
module comparator_4bit (
output agtb,
output altb,
output aeqb,
input [3:0] a,
input [3:0] b
);
wire signa, signb;
reg agtb, altb, aeqb;
sign sa (
signa,
a
);
sign sb (
signb,
b
);
always @(a or b or signa or signb) begin
if ((signa == 1) && (signb == 0)... | 7.372345 |
module comparator_4bit_tb ();
reg LTin, EQIn, GTin;
wire LTout, EQout, GTout;
reg [3:0] A, B;
comparator_4bit uut (
LTin,
EQIn,
GTin,
LTout,
EQout,
GTout,
A,
B
);
initial begin // A == B
$dumpfile("testbench.vcd");
$dumpvars(0, comparator_4bit_tb);
... | 7.372345 |
module comparator_4cen_16bit (
arg,
c,
a_00,
a_01,
a_10,
a_11
);
output [1:0] arg;
output [15:0] c;
input [15:0] a_00;
input [15:0] a_01;
input [15:0] a_10;
input [15:0] a_11;
wire [15:0] b_0;
wire [15:0] b_1;
wire index_0;
wire index_1;
wire index;
assign arg[1] = inde... | 7.689739 |
module comparator_4cen_test ();
wire signed [15:0] quotient;
wire cordic_div_flag;
reg signed [15:0] dividend;
reg signed [15:0] division;
reg clk;
reg rst;
reg cordic_div_en;
cordic_div_smaller div_exam (
.cordic_div_flag(cordic_div_flag),
.quotient(quotient),
.dividend(dividend),
... | 7.689739 |
module comparator_4_bit (
input [3:0] a_i, // Input A
input [3:0] b_i, // Input B
output reg eq_o, // A == B
output reg gr_o, // A > B
output reg le_o // A < B
);
// Combinational Logic
always @(*) begin
if (a_i > b_i) begin
// A greater than B
... | 7.051026 |
module comparator_4_bit_tb ();
// Signal Decleration
reg [3:0] a_i;
reg [3:0] b_i;
wire eq_o, gr_o, le_o;
// Instantiation
comparator_4_bit dut (
.a_i (a_i),
.b_i (b_i),
.eq_o(eq_o),
.gr_o(gr_o),
.le_o(le_o)
);
// Logic to drive inputs and check outputs
initial begin
... | 7.051026 |
module COMPARATOR_51 (
min,
i0,
i1,
i2,
i3,
i4
);
//DO NOT CHANGE!
output [2:0] min;
input [5:0] i0, i1, i2, i3, i4;
//---------------------------------------------------
//Write your design here
endmodule
| 7.738331 |
module comparator_512 (
in,
out
);
input [40:0] in;
output [0:0] out;
assign out = (in[40]) ? {1'b0} : {1'b1};
endmodule
| 6.940318 |
module comparator_8 ( //8位比较器
input [7:0] A,
input [7:0] B,
input rst,
input clk,
output reg equal,
output reg larger,
output reg smaller
);
always @(posedge clk or negedge rst) begin
if (rst == 0) begin
equal = 0;
larger = 0;
smaller = 0;
end else if (A > B... | 7.209328 |
module Comparator_8bit (
output lt,
eq,
gt,
input [7:0] A,
B,
input l,
e,
g
);
wire l1, e1, g1;
comparator_3bit c1 (
l1,
e1,
g1,
A[2:0],
B[2:0],
l,
e,
g
);
wire l2, e2, g2;
comparator_3bit c2 (
l2,
e2,
g2,
... | 6.831849 |
module comparator_8bit_tb ();
reg LTin, EQin, GTin;
wire LTout, EQout, GTout;
reg [7:0] A, B;
comparator_8bit uut (
LTin,
EQin,
GTin,
LTout,
EQout,
GTout,
A,
B
);
initial begin // A == B
$dumpfile("testbench.vcd");
$dumpvars(0, comparator_8bit_tb);
... | 7.146696 |
module comparator_8cen_16bit (
d,
arg,
a_000,
a_001,
a_010,
a_011,
a_100,
a_101,
a_110,
a_111
);
output [15:0] d;
output [2:0] arg;
input [15:0] a_000;
input [15:0] a_001;
input [15:0] a_010;
input [15:0] a_011;
input [15:0] a_100;
input [15:0] a_101;
input [15:... | 8.170791 |
module Comparator_8_bits (
input [7:0] A,
input [7:0] B,
input l,
input e,
input g,
output lt,
output gt,
output eq
);
wire [2:0] extra_A, extra_B;
assign extra_A = {A[7], A[7:6]};
assign extra_B = {B[7], B[7:6]};
wire [2:0] c1, c2;
Comparator_3_bits
first_3_bits (
... | 7.417334 |
module: Comparator_8_bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Comparator_8_bits_tb;
// Inputs
reg [7:0] A;
reg [7:0] B;
reg l;
reg e;
reg g;
// Outputs
wire lt;... | 7.082126 |
module Comparator_9bits (
A,
B,
AltB,
AeqB,
AgtB
);
input [8:0] A, B;
output AltB, AeqB, AgtB;
assign AltB = A < B;
assign AeqB = A == B;
assign AgtB = A > B;
endmodule
| 7.560436 |
module comparator_efficient #(
parameter width = 8
) (
input [width-1:0] a,
input [width-1:0] b,
input mode,
output agtb // a is greater than b then agtb =1
);
wire a1_b0; // for signed comparison
wire agtb_mag; // when the unsigned comparison
assign a1_b0 = ((a[width-1]) == 1'b1 && (b[... | 7.587352 |
module Comparator_Equal
//It needs to be adjustable because it's used in two modules,
//but this parameter is not a function of the width of the format
#(
parameter S = 1
) (
input wire [S-1:0] Data_A,
input wire [S-1:0] Data_B,
output wire equal_sgn
);
assign equal_sgn = (Data_A == Data_B) ? 1'b1 :... | 8.839558 |
module comparator_FF (
in,
out
);
input wire [8:0] in;
output reg [7:0] out;
always @(*) begin
if (in > 8'hFF) out <= in - 8'hFF;
else out <= in[7:0];
end
endmodule
| 6.977931 |
module Comparator_Less #(
parameter W = 8
) (
input wire [W-1:0] Data_A,
input wire [W-1:0] Data_B,
output wire less
);
assign less = (Data_A < Data_B) ? 1'b1 : 1'b0;
endmodule
| 8.445656 |
module Comparator_lv1 (
a,
b,
gt,
eq,
lt
);
input [3:0] a;
input [3:0] b;
//Add delays gt,eq,lt #3 #5 #4
output gt;
output eq;
output lt;
reg gt, eq, lt; // Ouput must be regs
//reg[3:0] i1;
//reg[3:0] i2;
always @(*) begin
if (a > b) begin
gt <= #3 1;
eq <... | 6.563623 |
module Comparator_lv2 (
gt,
lt,
a_gt_b,
a_eq_b,
a_lt_b
);
input [3:0] gt;
input [3:0] lt;
output a_gt_b;
output a_eq_b;
output a_lt_b;
reg a_gt_b, a_eq_b, a_lt_b;
always @(*) begin
if( gt > lt) // Note assign should be be used in if_else
begin //Every reg must be assigned s... | 6.563623 |
module comparator_mask #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0... | 8.809028 |
module comparator_mask_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire ... | 8.809028 |
module Comparator (
input wire A_S,
B_S,
COUT, // Bit de sinal de A e B, e o bit COUT
input wire [31:0] S, // Valor da subtração A - B
output wire EQ,
LU,
LS // Saídas das comparações
);
// Utilização dos módulos previamente criados
ComparatorEQ E0 (
.S (S),
.EQ(EQ)
);
... | 8.939213 |
module comparator_nb (
A,
B,
EQ,
LT,
GT
);
parameter n = 32;
input [n-1:0] A, B;
output reg EQ, LT, GT;
always @(A, B) begin
if (A > B) begin
EQ = 0;
LT = 0;
GT = 1;
end else if (A < B) begin
EQ = 0;
LT = 1;
GT = 0;
end else begin
EQ =... | 8.88308 |
module comparator_nbit
// Parameters section
#(
parameter N = 4
)
// Ports section
(
input [N-1:0] a,
input [N-1:0] b,
output reg smaller,
output reg equal,
output reg greater
);
// Wildcard operator is best for the procedure's
// sensitivity list (control list)
always @(*) begin
smal... | 8.88308 |
module tb_comparator_nbit ();
parameter CMP_WIDTH = 12;
reg [CMP_WIDTH-1:0] a;
reg [CMP_WIDTH-1:0] b;
wire smaller;
wire equal;
wire greater;
// Instantiate the parameterized DUT
comparator_nbit #(
.N(CMP_WIDTH)
) CMP1 (
.a (a),
.b (b),
.smaller(smaller),
.equ... | 6.843472 |
module comparator_n_bit (
a,
b,
L,
G,
E
);
parameter n = 32;
input [n-1:0] a, b;
output L, G, E;
reg L = 0, G = 0, E = 0;
always @(a, b) begin
if (a > b) begin
L = 0;
E = 0;
G = 1;
end else if (a < b) begin
L = 1;
E = 0;
G = 0;
end else begin... | 7.150759 |
module comparator_sel #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0]... | 8.908014 |
module comparator_sel_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire ... | 8.908014 |
module comparator_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire ... | 9.707625 |
module: comparator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module comparator_tb;
// Inputs
reg [1:0] A;
reg [1:0] B;
// Outputs
wire L;
wire E;
wire G;
// Instantiate the... | 7.106284 |
module comparator_top (
input wire clk,
input wire btnC,
input wire [15:0] sw,
output wire led
);
// internal signals
wire [7:0] a, b;
wire out, out_unsigned, out_signed;
wire toggle_mode;
reg mode;
// inputs
assign a = sw[7:0];
assign b = sw[15:8];
// ou... | 7.239849 |
module comparator #(
// INPUT PARAMETERS
parameter DATA_WIDTH = 16
) (
// PORTS
input wire CLK,
input wire RESET,
input wire [DATA_WIDTH -1 : 0] DATA_IN_0,
input wire [DATA_WIDTH -1 : 0] DATA_IN_1,
output reg [DATA_WIDTH -1 : 0] COMP... | 7.565129 |
module COMPARATOR_VAR #(parameter bits = 4) (
input [bits-1:0] a, b,
output gt,lt,eq
);
//for every 2 bits there is one comparator
wire [bits/2-1:0] gt_in;
wire [bits/2-1:0] lt_in;
wire [bits/2-1:0] eq_in;
//for every two comparators there is one glue ===
//for every 4 bits there is one glue
//dont use MSB
wire [... | 6.966001 |
module CompArchReg (
R,
DIn,
Clk,
Reset,
EnW
);
input Clk, Reset, EnW;
input [31:0] DIn;
output reg [31:0] R;
always @(posedge Clk) begin
if (Reset == 1) begin
R = 0;
end else if (EnW == 1) begin
R = DIn;
end else begin
R = R;
end
end
endmodule
| 7.159109 |
module Compare12 (
input wire iClock,
input wire iEnable,
input wire [27:0] iIn0,
input wire [27:0] iIn1,
input wire [27:0] iIn2,
input wire [27:0] iIn3,
input wire [27:0] iIn4,
input wire [27:0] iIn5,
input wire [27:0] iIn6,
input wire [27:0] iIn7,
input wire [27:0... | 7.89803 |
module Compare12TB;
reg clk, ena, rst;
integer i;
integer cycles;
reg [31:0] in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11;
wire [3:0] min;
Compare12 c12 (
.iClock(clk),
.iEnable(ena),
.iIn0(in0),
.iIn1(in1),
.iIn2(in2),
.iIn3(in3),
.iIn4(in4),
... | 6.523018 |
module Compare15 (
input wire iClock,
input wire iEnable,
input wire [30:0] iIn0,
input wire [30:0] iIn1,
input wire [30:0] iIn2,
input wire [30:0] iIn3,
input wire [30:0] iIn4,
input wire [30:0] iIn5,
input wire [30:0] iIn6,
input wire [30:0] iIn7,
input wire [30:0... | 7.753259 |
module compare3m_tb;
parameter tck = 10, program_cycles = `TEST_CYCLES;
defparam glbl.ROC_WIDTH = 0;
reg clk, rst, irq; // clock, reset, interrupt req
wire [`code_depth-1:0] addr_0, addr_1; // instruction address
reg [`operand_width-1:0] port_0[0:`port_size-1], port_1[0:`port_size-1];
wire [`operand_wi... | 7.108585 |
module compare4_10 (
input [5:0] alufn,
input z,
input v,
input n,
output reg [31:0] out
);
always @* begin
out[1+30-:31] = 1'h0;
case (alufn[1+1-:2])
2'h1: begin
out[0+0-:1] = z;
end
2'h2: begin
out[0+0-:1] = n ^ v;
end
2'h3: begin
... | 6.668597 |
module compare8 (
input wire [7:0] a,
b, // a and b are the two 2-bit numbers to compare
output wire a_geq_b // single bit output. Should be high if a > b
);
// internal signal declaration
// g0 - g3 represent the greater than output for each two bits starting with MSB
// e0 - e3 represnt the equa... | 7.974235 |
module compare8_10 (
input [5:0] alufn,
input z,
input v,
input n,
output reg [7:0] out
);
always @* begin
case (alufn[1+1-:2])
2'h1: begin
out = z;
end
2'h2: begin
out = n ^ v;
end
2'h3: begin
out = z | (n ^ v);
end
default... | 6.613775 |
module compareEq #(
// =============================================================================
// ** Parameters
// =============================================================================
// Size of word (parent should over-write this if needeD)
parameter N = 10
) (
// ==============... | 7.239219 |
module Comparer (
input [31:0] D1,
input [31:0] D2,
input CmpOp,
output Zero,
output LZero
);
wire [31:0] CmpRst = (CmpOp == 0) ? D1 : // 0Ƚ
(CmpOp == 1) ? D1 - D2 : // Ƚ
32'dz;
assign Zero = (CmpRst == 0);
assign LZero = CmpRst[31];
endmodule
| 8.19955 |
module CompareRecFN (
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output io_gt,
output [ 4:0] io_exceptionFlags
);
wire rawA_isZero = io_a[63:61] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
wire _T_4 = io_a[63:62]... | 6.787862 |
module compareRecFN #(
parameter expWidth = 3,
parameter sigWidth = 3
) (
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input signaling,
output lt,
output eq,
output gt,
output unordered,
output [4:0] exceptionFlags
);
/*--------------------------------... | 7.391353 |
module compareRecFN_Fp16 (
a,
b,
signaling,
lt,
eq,
gt,
unordered,
exceptionFlags
);
//parameter expWidth = 5;
//parameter sigWidth = 11;
input [(5 + 11):0] a;
input [(5 + 11):0] b;
input signaling;
output lt;
output eq;
output gt;
output unordered;
output [4:0] exce... | 6.688019 |
module compareRecF16 (
input [16:0] a,
input [16:0] b,
input signaling,
output lt,
output eq,
output gt,
output unordered,
output [4:0] exceptionFlags
);
compareRecFN #(5, 11) compareRecFN (
a,
b,
signaling,
lt,
eq,
gt,
unordered,
except... | 7.105435 |
module compareRecF32 (
input [32:0] a,
input [32:0] b,
input signaling,
output lt,
output eq,
output gt,
output unordered,
output [4:0] exceptionFlags
);
compareRecFN #(8, 24) compareRecFN (
a,
b,
signaling,
lt,
eq,
gt,
unordered,
except... | 7.583566 |
module compareRecF64 (
input [64:0] a,
input [64:0] b,
input signaling,
output lt,
output eq,
output gt,
output unordered,
output [4:0] exceptionFlags
);
compareRecFN #(11, 53) compareRecFN (
a,
b,
signaling,
lt,
eq,
gt,
unordered,
excep... | 7.025648 |
module compareSwap #(
parameter Width = 32
) (
req,
fin,
a,
b,
smaller,
bigger
);
input [Width-1:0] a, b;
output wire [Width-1:0] smaller, bigger;
input req;
output wire fin;
wire compareFin, biggerSign, equalSign, smallerSign;
wire biggerFin, smallerFin;
comparator #(Width) ... | 7.244849 |
module compareTemp (
input inputTemp,
currentTemp,
output reg heatChange
);
always @(inputTemp) begin
if (inputTemp < currentTemp) begin
heatChange = 1;
end else begin
heatChange = 0;
end
end
endmodule
| 7.858784 |
module compareTest (
input clk,
input [31:0] a_in,
input [31:0] b_in,
input req_in,
output wire fin,
output wire [2:0] resultNormal,
output wire [2:0] resultKarin
);
reg req = 1'b0;
reg [31:0] a = 0;
reg [31:0] b = 0;
always @(posedge clk) begin
if (req_in) begin
req <= 1'b... | 7.928164 |
module compare_11 (
input z,
input v,
input n,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn)
default: begin
out[0+0-:1] = 1'h0;
end
6'h33: begin
out[0+0-:1] = z;
end
6'h35: begin
out[0+0-:1... | 7.452934 |
module compare_12 (
input [7:0] a,
input [7:0] b,
input [5:0] alufn,
output reg [7:0] out
);
always @* begin
out = 1'h0;
case (alufn)
6'h33: begin
out[0+0-:1] = a == b;
end
6'h35: begin
out[0+0-:1] = a < b;
end
6'h37: begin
out[0+0-:1] ... | 6.624798 |
module compare_14 (
input z,
input v,
input n,
input [2:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn)
2'h3: begin
out = {15'h0000, z};
end
3'h5: begin
out = {15'h0000, n ^ v};
end
3'h7: begin
out = {15'h0000, z + (n ^ ... | 7.931476 |
module compare_16_11 (
input z,
input v,
input n,
input [0:0] sim_error,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn[0+3-:4])
default: begin
out[0+0-:1] = 1'h0;
end
4'h3: begin
if (sim_error == 1'h0) begi... | 7.65312 |
module compare_16_12 (
input z,
input v,
input n,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn[0+2-:3])
default: begin
out[0+0-:1] = 1'h0;
end
3'h3: begin
out[0+0-:1] = z;
end
3'h5: begin
o... | 7.74034 |
module compare_16_14 (
input z,
input v,
input n,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn[0+2-:3])
default: begin
out[0+0-:1] = 1'h0;
end
3'h3: begin
out[0+0-:1] = z;
end
3'h5: begin
o... | 7.958992 |
module compare_16_19 (
input z,
input v,
input n,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn[0+2-:3])
default: begin
out[0+0-:1] = 1'h0;
end
3'h3: begin
out[0+0-:1] = z;
end
3'h5: begin
o... | 7.57504 |
module compare_17 (
input z,
input v,
input n,
input [5:0] alufn,
output reg [15:0] s
);
always @* begin
case (alufn)
6'h33: begin
s = z;
end
6'h35: begin
s = n ^ v;
end
6'h37: begin
s = z | (n ^ v);
end
default: begin
... | 7.652826 |
module compare_18 (
input z,
input v,
input n,
input [5:0] alufn_signal,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn_signal)
default: begin
out[0+0-:1] = 1'h0;
end
6'h33: begin
out[0+0-:1] = z;
end
6'h35: begin
... | 8.35913 |
module compare_19 (
input z,
input v,
input n,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn)
default: begin
out[0+0-:1] = 1'h0;
end
6'h33: begin
out[0+0-:1] = z;
end
6'h35: begin
out[0+0-:1... | 7.694541 |
module compare_rule (
input [7:0] rule,
input [7:0] addr,
output wire result
);
wire [7:0] kt;
DontCare_z dontcare[7:0] (
.addr(addr[7:0]),
.rule(rule[7:0]),
.cout(kt[7:0])
);
assign result = (kt == 8'b11111111) ? 1 : 0;
endmodule
| 8.146482 |
module compare_21 (
input z,
input v,
input n,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn)
default: begin
out[0+0-:1] = 1'h0;
end
6'h33: begin
out[0+0-:1] = z;
end
6'h35: begin
out[0+0-:1... | 8.168098 |
module compare_22 (
input z,
input v,
input n,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn)
default: begin
out[0+0-:1] = 1'h0;
end
6'h33: begin
out[0+0-:1] = z;
end
6'h35: begin
out[0+0-:1... | 8.436353 |
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