code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module compare_28 (
input [5:0] alufn,
input v,
input z,
input n,
output reg [15:0] out
);
reg tempCmp;
always @* begin
out = 16'h0000;
case (alufn[1+1-:2])
2'h0: begin
tempCmp = 1'h0;
end
2'h1: begin
tempCmp = z;
end
2'h2: begin
... | 7.511056 |
module comparator_2in #(
parameter p_width = 21
) (
input i_clk,
input i_rst_n,
input [p_width-1:0] i_a,
input [p_width-1:0] i_b,
output [p_width-1:0] o_result,
output [ 1:0] o_index
);
// wire w_t1, w_t2;
// assign w_t1 = (i_a >= i_b) ? 1:0;
... | 7.932455 |
module compare_30 (
input [5:0] alufn,
input v,
input z,
input n,
output reg [15:0] cmp1
);
reg cmp;
always @* begin
case (alufn[1+1-:2])
2'h1: begin
cmp = z;
end
2'h2: begin
cmp = n ^ v;
end
2'h3: begin
cmp = z | (n ^ v);
end
... | 7.166019 |
module compare_4bit (
igual,
maior,
menor,
A,
B
);
input [3:0] A, B; //vetor de 4 bits com o menos significativo à direita
output igual, maior, menor;
wire [3:0] aux_ig, aux_ma, aux_me; //conexão de 4 bits, variáveis auxiliares
compare_1bit BL3 (
aux_ig[3],
aux_ma[3],
au... | 8.031462 |
module comparator_4in #(
parameter p_width = 19
) (
input i_clk,
input i_rst_n,
input [p_width-1:0] i_a,
input [p_width-1:0] i_b,
input [p_width-1:0] i_c,
input [p_width-1:0] i_d,
output [p_width-1:0] o_result,
output [ 3:0] o_index
);
wire... | 8.178017 |
module compare_75 (
input [5:0] alufn,
input v,
input z,
input n,
output reg [15:0] out
);
reg tempCmp;
always @* begin
out = 16'h0000;
case (alufn[1+1-:2])
2'h0: begin
tempCmp = 1'h0;
end
2'h1: begin
tempCmp = z;
end
2'h2: begin
... | 6.64467 |
module compare_76 (
input [5:0] alufn,
input v,
input z,
input n,
output reg [15:0] out
);
reg tempCmp;
always @* begin
out = 16'h0000;
case (alufn[1+1-:2])
2'h0: begin
tempCmp = 1'h0;
end
2'h1: begin
tempCmp = z;
end
2'h2: begin
... | 6.993903 |
module compare_8 (
input [4:0] in1,
input [4:0] in2,
output reg out
);
always @* begin
if (in1 == in2) begin
out = 1'h1;
end else begin
out = 1'h0;
end
end
endmodule
| 6.763507 |
module compare_8bit (
in1,
in2,
nshift,
in1_ST_in2,
checktoobig
);
input [7:0] in1, in2;
output [4:0] nshift;
output in1_ST_in2, checktoobig;
wire [8:0] temp1, temp2, temp3, temp4;
wire [7:0] temp5, temp6;
assign temp1 = {1'b0, in1};
assign temp2 = {1'b0, in2};
compliment2_9bit c... | 7.016558 |
module compare_and_shift (
int8,
mantissa_10,
mantissa_20,
ein_a,
ein_b,
exponent_res,
mantissa_11,
mantissa_21
);
input [9:0] mantissa_10, mantissa_20;
input [7:0] ein_a, ein_b;
input int8;
output reg [7:0] exponent_res;
output reg [9:0] mantissa_11, mantissa_21;
always @(... | 6.728648 |
module compare_and_status_logic (
input [3:0] wrt_ptr, // Stack pointer
output reg full, // Full
output reg empty
); // Empty
parameter depth = 4'b1111; // Depth of the FIFO
// HOW MUCH MEMORY USED
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(*... | 6.728648 |
module compare_cla #(
parameter N = 7,
parameter [N-1:0] CONST = 0,
parameter EQ = 1,
parameter W = 1 /* Number of LUT bits needed per input */
) (
input [N-1:0] in,
output out
);
if (!`CONFIG_HAS_CARRY4 || N * W <= `CONFIG_LUT_MAX_SZ)
assign out = (in != CONST) ^ EQ;
else begin
localparam OPTIM = (CONST[0... | 8.277234 |
module eq_cla #(
parameter N = 7,
parameter [N-1:0] CONST = 0,
parameter W = 1
) (
input [N-1:0] in,
output out
);
compare_cla #(N, CONST, 1, W) u_cla (
in,
out
);
endmodule
| 7.249961 |
module neq_cla #(
parameter N = 7,
parameter [N-1:0] CONST = 0,
parameter W = 1
) (
input [N-1:0] in,
output out
);
compare_cla #(N, CONST, 0, W) u_cla (
in,
out
);
endmodule
| 7.250389 |
module zero_cla #(
parameter N = 7,
parameter W = 1
) (
input [N-1:0] in,
output out
);
eq_cla #(N, 0, W) u_cla (
in,
out
);
endmodule
| 8.057316 |
module nonzero_cla #(
parameter N = 7,
parameter W = 1
) (
input [N-1:0] in,
output out
);
neq_cla #(N, 0, W) u_cla (
in,
out
);
endmodule
| 7.813228 |
module compare_coords (
input wire [9:0] x1,
input wire [9:0] y1,
input wire [9:0] x2,
input wire [9:0] y2,
output wire match
);
assign match = (x1 == x2 && y1 == y2);
endmodule
| 7.542417 |
module Compare_Logic(
clock,
reset,
write_Pointer,
read_Pointer,
write_Enable,
read_Enable,
sig_Full,
sig_Empty,
counter,
);
parameter BUFFER_WIDTH = 3;
parameter BUFFER_SIZE = 8;
input clock;
input reset;
input [BUFFER_WIDTH-1:0] write_Pointer;
inout [BUFFER_WIDTH-1:0] read_Pointer;
... | 7.022077 |
module cmp_n #(
parameter N = 8
) (
input wire [N-1:0] A,
B,
output wire Go,
Eo,
Lo
);
//*********<中间信号>*************
wire [N:0] Gi, Ei;
assign Gi[0] = 1'b0;
assign Ei[0] = 1'b1;
assign Go = Gi[N];
assign Eo = Ei[N];
assign Lo = (~Go) && (~Eo);
//*********<模块例化>*********... | 7.432107 |
module compare_nbit_tb;
parameter N = 8;
reg [N-1:0] A, B;
wire Go, Eo, Lo;
//*********<模块例化>*************
cmp_n #(
.N(N)
) cmp_8 (
.A(A),
.B(B),
.Go(Go),
.Eo(Eo),
.Lo(Lo)
);
initial begin
$dumpfile("cmp_n.vcd");
$dumpvars;
A = 'b0;
B = 'b0;
repea... | 7.130142 |
module compare_result;
integer file, r;
reg a, b, expect_v, clock;
//reg [`MAX_LINE_LENGTH*8:1];
wire out;
parameter cycle = 20;
always #(cycle / 2) clock = !clock; // Clock generator
initial begin : file_block
clock = 0;
file = $fopen("compare.pat");
if (file == `NULL) disable file_block;
... | 6.651171 |
module compare_select (
p0_0,
p2_0,
p0_1,
p2_1,
p1_2,
p3_2,
p1_3,
p3_3,
out0,
out1,
out2,
out3,
ACS0,
ACS1,
ACS2,
ACS3
);
input [4:0] p0_0;
input [4:0] p2_0;
input [4:0] p0_1;
input [4:0] p2_1;
input [4:0] p1_2;
input [4:0] p3_2;
input [4:0] ... | 7.097953 |
module compare_storage_elements (
input D,
clk,
output Qa,
Qb,
Qc
);
D_latch L0 (
.D (D),
.clk(clk),
.Q (Qa),
.Q_b()
);
D_FF_pos FF0 (
.D (D),
.clk(clk),
.Q (Qb)
);
D_FF_neg FF1 (
.D (D),
.clk(clk),
.Q (Qc)
);
endmodul... | 7.888877 |
module compare_storage_elements_tb ();
// Declare local reg and wire
reg clk, D;
wire Q_latch, Q_ff_pos, Q_ff_neg;
// Instantiate unit under test
compare_storage_elements uut (
.D (D),
.clk(clk),
.Qa (Q_latch),
.Qb (Q_ff_pos),
.Qc (Q_ff_neg)
);
// Generate stimuli, using ... | 7.888877 |
module compare_unit #(
parameter SIGNED = 2'b00,
parameter UNSIGNED = 2'b01,
parameter OTHERS = 32'h0,
parameter SIGNED_LT = 32'h1,
parameter UNSIGNED_LT = 32'h1,
parameter UNKNOWN_OPCODE_RESULT = 32'h0
) (
input [31:0] op... | 7.938845 |
module compare_usage (
inp1,
inp2,
my_res
);
parameter my_compare_width = 4;
input [my_compare_width:1] inp1, inp2;
output my_res;
compare #(
.W(my_compare_width)
) DUT (
.a(inp1),
.b(inp2),
.result(my_res)
);
endmodule
| 6.820402 |
module compare_ws (
input wire clock,
input wire reset_n,
input wire [13:0] ws1,
input wire [13:0] ws2,
input wire [13:0] ws3,
input wire [13:0] ws4,
input wire [5:0] disp_1,
input wire [5:0] disp_2,
input wire [5:0] disp_3,
input wire [5:0] disp_4,
output wire [ 5:0] dispar... | 7.26379 |
module Comparing (
qzt_clk,
Vin,
Thr,
overthr
);
input qzt_clk;
input [19:0] Vin;
input [19:0] Thr; //threashold
output overthr;
reg overthr;
always @(posedge qzt_clk) begin
overthr = (Vin > Thr) ? 1 : 0;
end
endmodule
| 6.646026 |
module comparison_unit #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input [ 2:0] sel,
output reg flag
);
always @(*)
case (sel)
0: flag <= (a == b);
1: flag <= (a != b);
2: flag <= (a < b);
3: flag <= ($signed(a... | 9.20738 |
module Comparitor (
Arr0,
Arr1,
Arr2,
Arr3,
Arr4,
Arr5,
Arr6,
Arr7,
Arr8,
Arr9,
clk,
done,
result,
enable,
reset
);
input [15:0] Arr0;
input [15:0] Arr1;
input [15:0] Arr2;
input [15:0] Arr3;
input [15:0] Arr4;
input [15:0] Arr5;
input [15:0] Arr... | 6.925746 |
module MUXCY (
output O,
input CI,
input DI,
input S
);
assign O = S ? CI : DI;
endmodule
| 7.016891 |
module MUXCY_D (
output LO,
output O,
input CI,
input DI,
input S
);
assign LO = S ? CI : DI;
assign O = LO;
endmodule
| 6.747696 |
module XORCY (
output O,
input CI,
input LI
);
assign O = CI ^ LI;
endmodule
| 7.449523 |
module XOR2 (
output O,
input I0,
input I1
);
assign O = I0 ^ I1;
endmodule
| 8.085352 |
module compctl #(
parameter P_WIDTH = 32
) (
input [P_WIDTH-1:0] a,
input [P_WIDTH-1:0] b,
input [2-1:0] op,
output reg cres
);
always @(a or b or op) begin
case (op)
2'b00: cres = (a == b);
2'b01: cres = (a >= b);
2'b10: cres = a[0];
default: cres = 1'bx;
en... | 7.290184 |
module compdata #(
parameter P_WIDTH = 32
) (
input [P_WIDTH-1:0] a,
b,
output reg [P_WIDTH-1:0] dres,
input [2-1:0] op
);
always @(op, a, b) begin
case (op)
2'b00: dres = (a >> 1);
2'b01: dres = (a - b);
default: dres = {P_WIDTH{1'bx}};
endcase
end
endmodule
| 8.213131 |
module:
* this module is combinatorical. it comperes 2 given inputs and returns
* the one with greater or smaller value (c_data and corresponding index) accorging
* to great_n_small signal.
* comperation region is scalable and can be chosen using lo and hi parameters.
*
* PARAMETERS:
* data_wd: width of input ... | 7.293413 |
module:
* compare 3 inputs and forward to output samllest element and it's index
* this module is combinatorical.
*
* INPUTS:
* d0,d1,d2: are the data inputs
* great_n_small:
* operation to be performed. '1' - greater index will be returned
* '0' - smaller index will be returned
* OUTPUT:
* c_dat: ch... | 7.531483 |
module comperator_axi_ip_v1_0_block_reader #(
BLOCK_SIZE = 8
) (
aclk,
aresetn,
// First input frame
s_axis_tdata,
s_axis_tlast,
s_axis_tready,
s_axis_tuser,
s_axis_tvalid,
go,
done,
block,
count
);
localparam DATA_WIDTH = 24;
localparam BLOCK_WIDTH = BLOCK_SIZE... | 8.255757 |
module comperator_axi_ip_v1_0_controller #(
BLOCK_SIZE = 8
) (
aclk,
aresetn,
go,
go1,
go2,
done1,
done2,
eol1,
eol2,
sof1,
sof2,
cmp_go,
video_go,
video_done,
count
);
input aclk;
input aresetn;
input go;
output go1;
output go2;
input done1;
... | 8.255757 |
module comperator_axi_ip_v1_0_eol_detector (
aclk,
aresetn,
// First input frame
s_axis_tdata,
s_axis_tlast,
s_axis_tuser,
s_axis_tvalid,
go,
eol
);
localparam DATA_WIDTH = 24;
input aclk;
input aresetn;
input [DATA_WIDTH-1:0] s_axis_tdata;
input s_axis_tlast;
input s... | 8.255757 |
module comperator_axi_ip_v1_0_line_reader #(
FRAME_WIDTH = 320
) (
aclk,
aresetn,
// First input frame
s_axis_tdata,
s_axis_tlast,
s_axis_tready,
s_axis_tuser,
s_axis_tvalid,
go,
done,
line
);
localparam DATA_WIDTH = 24;
localparam LINE_WIDTH = FRAME_WIDTH * DATA_WI... | 8.255757 |
module comperator_axi_ip_v1_0_simple_controller (
aclk,
aresetn,
go,
go0,
go1,
done0,
done1,
running
);
input wire aclk;
input wire aresetn;
input wire go;
output reg go0;
output reg go1;
input wire done0;
input wire done1;
output reg running;
localparam STATE_RESET = ... | 8.255757 |
module comperator_axi_ip_v1_0_sof_detector (
aclk,
aresetn,
// First input frame
s_axis_tdata,
s_axis_tlast,
s_axis_tuser,
s_axis_tvalid,
go,
sof
);
localparam DATA_WIDTH = 24;
input aclk;
input aresetn;
input [DATA_WIDTH-1:0] s_axis_tdata;
input s_axis_tlast;
input s... | 8.255757 |
module comperator_main (
A,
B,
C,
D
);
input [7:0] A;
input [7:0] B;
output C, D;
wire [7:0] A;
wire [7:0] B;
reg C, D;
always @(A | B) begin
if (A > B) begin
C <= 1'b1;
D <= 1'b0;
end else if (A == B) begin
C <= 1'b0;
D <= 1'b1;
end else begin
C... | 7.134912 |
module comperator_testbench ();
reg [7:0] A;
reg [7:0] B;
wire C, D;
comperator_main UUt (
.A(A),
.B(B),
.C(C),
.D(D)
);
initial begin
A <= 8'b00000001;
B <= 8'b00000000;
#10;
A <= 8'b00000010;
#10;
B <= 8'b00000010;
#10;
A <= 8'b00000110;
#10;
... | 6.507249 |
module CI_mux (
input wire [1:0] selectionlines,
input [31:0] A,
B,
output [31:0] C
);
assign C = (selectionlines == 2'b11) ? A : B;
endmodule
| 8.527042 |
module complement (
dataout,
datain,
enable
);
output [`REG_SIZE:0] dataout;
input [`REG_SIZE:0] datain;
input enable;
reg [`REG_SIZE:0] Co, dataout, Enable;
reg Cin;
integer i, j;
always @(enable) begin
for (j = 0; j < `REG_SIZE + 1; j = j + 1) Enable[j] = enable;
end
wire [`REG_S... | 7.736521 |
module compl1 (
output wire [3:0] Out,
input wire [3:0] Inp,
input wire cpl
);
//si cpl = 1, Out = cpl1(Inp) y cuando cpl = 0 la salida Out = Inp
assign Out = cpl ? (~Inp) : Inp;
endmodule
| 7.8856 |
module compl1_tb;
//declaracion de se�ales
reg [3:0] test_a;
reg test_s;
wire [3:0] test_out;
//instancia del modulo a testear, con notaci�n de posiciones de argumentos y con notaci�n de nombres
compl1 complementador_1 (
test_out,
test_a,
test_s
);
initial begin
$monitor("tiempo=... | 7.387706 |
module compl2 (
i,
o
);
parameter WIDTH = 1;
input [WIDTH-1:0] i;
output [WIDTH-1:0] o;
assign o = ~i + 1'b1;
endmodule
| 7.511779 |
module complement32 (
input sign, //
input [31:0] x, //Դ
output [31:0] y //
);
assign y = sign ? ((~x) + 1) : x;
endmodule
| 7.994302 |
module complement64 (
input sign,
input [63:0] x,
output [63:0] y
);
assign y = sign ? ((~x) + 1) : x;
endmodule
| 6.906152 |
module Complement2s (
input [7:0] A,
output [7:0] Out
);
wire [7:0] w;
genvar j;
generate
begin
for (j = 0; j < 8; j = j + 1) begin
Mux M (
1'b1,
1'b0,
A[j],
w[j]
);
end
end
endgenerate
wire [7:0] c;
HalfAdder H1... | 6.992132 |
module Complement2s_11Bit (
a,
b
);
input [11:1] a;
output [11:1] b;
wire [11:1] comp1s;
assign comp1s[1] = !a[1];
assign comp1s[2] = !a[2];
assign comp1s[3] = !a[3];
assign comp1s[4] = !a[4];
assign comp1s[5] = !a[5];
assign comp1s[6] = !a[6];
assign comp1s[7] = !a[7];
assign comp... | 7.630614 |
module Complement2s_5Bit (
a,
b
);
input [5:1] a;
output [5:1] b;
wire [5:1] comp1s;
wire c;
assign comp1s[1] = !a[1];
assign comp1s[2] = !a[2];
assign comp1s[3] = !a[3];
assign comp1s[4] = !a[4];
assign comp1s[5] = !a[5];
Bit5Adder addr (
comp1s,
5'b00001,
b,
c
)... | 7.630614 |
module fulladder (
resto,
vai1,
vem1,
a,
b
);
output resto, vai1;
input vem1, a, b;
wire w1, w2, w3;
xor XOR1 (w1, a, b);
and AND1 (w2, a, b);
xor XOR2 (resto, w1, vem1);
and AND2 (w3, w1, vem1);
or OR1 (vai1, w2, w3);
endmodule
| 7.454465 |
module completeadder (
s4,
s3,
s2,
s1,
s0,
a3,
a2,
a1,
a0
);
output s4, s3, s2, s1, s0;
input a3, a2, a1, a0;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9;
halfadder HALF1 (
s0,
w1,
a0,
1
);
fulladder FULL1 (
s1,
w2,
w1,
a1,
... | 6.600283 |
module halfAdder (
s0,
c0,
a,
b
);
input a, b;
output s0, c0;
xor (s0, a, b);
and (c0, a, b);
endmodule
| 7.256462 |
module adder_4bits (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
input a0, a1, a2, a3, b0, b1, b2, b3;
output s0, s1, s2, s3, c0, c1, c2;
halfAdder HA1 (
s0,
c0,
a0,
b0
);
fullAdder FA1 (
s1,
c1,
c0,
a1,
... | 8.00499 |
module complemento_2 (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
a3
);
input a0, a1, a2, a3;
output s0, s1, s2, s3, c0, c1, c2, c3;
not NOT1 (c0, a0);
not NOT1 (c1, a1);
not NOT1 (c2, a2);
not NOT1 (c3, a3);
adder_4bits ADD1 (
s0,
s1,
s2,
s3,
c0,
c1,... | 6.625481 |
module complement (
output s,
input a
);
//propriedades
assign s = ~a + 1'b1;
endmodule
| 7.736521 |
module test_complement;
//Dados locais
reg [3:0] a;
wire [3:0] s;
//Instancia
complement C2 (
s,
a
);
//execucao
initial begin : main
a = 2'b01;
$display("Complements - Author: Eduardo Botelho");
$display("s = %d = %b", s, s);
a = 2'b10;
$display("s = %d = %b", s, s);... | 6.590267 |
module
module complement_converter_fsm_tb;
// Initialise inputs and outputs
reg clk, inp, reset;
reg [7:0]inp_array; // Array from which we will read bit wise input
integer i;
wire out;
// Instantiate the Unit Under Test (UUT)
complement_converter_fsm FSM(.clk(cl... | 6.843944 |
module complement_encoder #(
parameter Width = 26
) (
input [Width - 1 : 0] DataIn,
input Enable,
output [Width - 1 : 0] DataOut
);
wire [Width - 1 : 0] DataTmp;
assign DataTmp = ~DataIn;
assign DataOut = Enable ? (DataTmp + 1'b1) : DataIn;
endmodule
| 6.569841 |
module com_c (
c,
c_com
);
`include "parameters.v"
input [2*(SIG_WIDTH+1)-1:0] c;
output [2*(SIG_WIDTH+1)-1:0] c_com;
wire [2*(SIG_WIDTH+1)-1:0] temp;
assign temp = ~c + 1;
assign c_com = temp[2*(SIG_WIDTH+1)-1:0]; //48bits
endmodule
| 7.910954 |
module complete (
clk,
rst,
complete_en,
result_bram_douta,
result_bram_ena,
result_bram_addra,
result,
complete_finish
);
input clk;
input rst;
input complete_en;
input [`DATA_SIZE-1:0] result_bram_douta;
output reg result_bram_ena;
output reg [14:0] result_bram_addra;
out... | 6.802279 |
module CompleteInstructionDecoder (
a,
decode,
execute,
ip,
op,
load,
add,
jump,
jumpz,
jumpnz,
jumpc,
jumpnc,
sub,
bitand
);
input [7:0] a;
input decode, execute;
output ip, op, load, add, jump, jumpz, jumpnz, jumpc, jumpnc, sub, bitand;
wire enable, wip,... | 7.207579 |
module CompleteInstructionDecoder_t ();
reg [7:0] input_a;
reg clock, input_clock_enable, input_clear, fetch, decode, execute, increment;
reg
output_ip,
output_op,
output_load,
output_add,
output_jump,
output_jumpz,
output_jumpnz,
output_jumpc,
output_jumpnc,
... | 7.207579 |
module*/
module topModule_group10(input[15:0] sw1,input [15:0] sw2,output[15:0] Z,input clk1,output over,output[4:0] state
);
integer count=0;
reg clk=0;
integer counter=0;
always @(posedge clk1)
begin
if(counter==1) begin
clk=~clk;
counter=0;
end
else
counter=counter+1;
end
reg go=0;
always@(posedge clk) begin
c... | 6.508162 |
module register_1bit (
output reg [15:0] rg,
input [15:0] in,
output reg [15:0] out,
input t,
input ld
);
initial rg = 0;
always @* begin
if (t == 1) out = rg;
else out = 0;
if (ld == 1) rg = in;
end
endmodule
| 6.5297 |
module register_3bit (
input [15:0] in,
output reg [15:0] out,
input t,
input ld
);
reg [15:0] rg = 0;
always @* begin
if (t == 1) out = rg;
else out = 0;
if (ld == 1) rg = in;
end
endmodule
| 6.937966 |
module register_16bit (
input [15:0] in,
output reg [15:0] out,
input t,
input ld
);
reg [15:0] rg = 0;
always @* begin
if (t == 1) out = rg;
else out = 0;
if (ld == 1) rg = in;
end
endmodule
| 7.062933 |
module CHIP (
clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wdata_I,
mem_rdata_I,
mem_ready_I,
... | 8.331638 |
module Hazard_dection_Unit (
rs1,
rs2,
equal,
rd_Ex,
reg_write_Ex,
jal,
jalr,
beq,
bneq,
mem_read_,
pc_mux,
IF_mux,
control_mux
); //variable ending with '_' means next stage value
input [4:0] rs1, rs2, rd_Ex;
input equal, jal, jalr, beq, bneq, mem_read_, reg_wri... | 8.37264 |
module Forward_Unit (
regwrite_1,
rd_1,
regwrite_2,
rd_2,
rs1,
rs2,
muxA,
muxB
); //EX|1(MEM)|2(WB)
input regwrite_1, regwrite_2;
input [4:0] rs1, rs2, rd_1, rd_2;
output reg [1:0] muxA, muxB;
always @(*) begin
if ((regwrite_1) && (rd_1 == rs1)) muxA = 2'b10;
else if ((r... | 7.314655 |
module Control_Unit (
in,
rd,
RegWrite,
DataToReg,
jal,
jalr,
MemRead,
MemWrite,
Alusrc,
beq,
bneq
); //
input [7:0] in;
input [4:0] rd;
output reg RegWrite, jal, jalr, MemRead, MemWrite, Alusrc, beq, bneq;
output reg [1:0] DataToReg;
always @(*) begin
beq = ({... | 8.640647 |
module ImmGen (
in,
out
);
input [31:0] in;
output reg [31:0] out;
reg t1, t2, garbage;
always @(*) begin
t1 = ((!in[5]) & (!in[3])) | in[2];
t2 = ((!in[6]) | in[2]) & (!in[3]);
case ({
t1, t2
})
2'b00: out = {{20{in[31]}}, in[7], in[30:25], in[11:8], 1'b0}; //beq,bneq
... | 6.657692 |
module Alu (
ctrl,
x,
y,
result
);
input [3:0] ctrl;
input signed [31:0] x;
input signed [31:0] y;
output reg [31:0] result;
always @(*) begin
case (ctrl[2:0])
3'b000: result = (ctrl[3] == 1'b0) ? x + y : x - y;
3'b111: result = x & y;
3'b110: result = x | y;
3'b... | 6.891033 |
module register_file (
Clk,
rst_n,
WEN,
RW,
busW,
RX,
RY,
busX,
busY
);
input Clk, WEN, rst_n;
input [4:0] RW, RX, RY;
input [31:0] busW;
output reg [31:0] busX, busY;
reg [31:0] r[0:31];
always @(*) begin
busX = r[RX];
busY = r[RY];
end
integer i;
alway... | 6.605344 |
module complete_address_decoder (
addr_in,
addr_decoded
);
parameter width = 1;
input [width-1:0] addr_in;
output [(2**width)-1:0] addr_decoded;
reg [(2**width)-1:0] addr_decoded;
parameter stage = width;
reg p [stage:0][2**stage-1:0];
wire [width-1:0] a;
assign a = addr_in;
al... | 7.284759 |
module complete_row (
input wire clk,
input wire pause,
input wire [(`BLOCKS_WIDE*`BLOCKS_HIGH)-1:0] fallen_pieces,
output reg [ `BITS_Y_POS-1:0] row,
output wire enabled
);
in... | 6.549349 |
module complex (
input [7:0] x,
input [7:0] y,
output z
);
wire [7:0] levelFirst;
wire [3:0] levelScond;
wire [1:0] levelThird;
wire levelFourth;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
assign levelFirst[i] = x[i] && y[i];
if (i % 2 == 1) assign levelScond[(i-1)/... | 6.893442 |
module ComplexALU (
input wire [14:0] inst,
input wire clk,
input wire reset, //it will work if the reset is one
output reg [3:0] realAns, //the real part of the answer will be shown here
output reg [3:0] imageAns //the imaginary part of the answer is shown here
);
reg [7:0] mem [15:0];//it is... | 7.05709 |
module takes 2 complex numbers and outputs their complex product
* The two inputs are formated as fixed point numbers with a number of decimal points equal to p_PointPosition
* The input width is specified by p_inputWidth
*
* Module Equation:
* o_ResR + i o_ResI = ( inAr + i inAi ) * ( inBr + i inBi )
*
* The... | 7.23517 |
module complexMultN (
DinAR,
DinAI,
DinBR,
DinBI,
DoutR,
DoutI
);
input [17:0] DinAR, DinAI, DinBR, DinBI;
output [17:0] DoutR, DoutI;
endmodule
| 7.39049 |
module complex_adder_ksa_32b (
A32,
B32,
R32,
COUT_32
);
input [31:0] A32;
input [31:0] B32;
output [31:0] R32;
output [1:0] COUT_32;
wire [31:0] A32;
wire [31:0] B32;
wire [31:0] R32;
wire [ 1:0] COUT_32;
wire [15:0] real_a32;
wire [15:0] imag_a32;
wire [15:0] real_b32;
wir... | 7.310064 |
module complex_add_subtract (
input wire [7:0] a,
input wire [7:0] b,
input wire op,
output wire [7:0] c
);
wire [3:0] a_real, a_imag, b_real, b_imag, c_real, c_imag;
assign a_real = a >> 4;
assign a_imag = a;
assign b_real = b >> 4;
assign b_imag = b;
assign c_real = op ? a_real + b_real ... | 7.906087 |
modules:
-- Function : This module accepts a complex number and returns
the value of imaginary_part/real_part. Acts as a
wrapper file for lpm_divide function.
--------------------------------------------------------------------------
*/
/*
------------------... | 7.517477 |
module Complex_Divide_Top (
input clk,
input rst_n,
input signed [63:0] a,
b,
p,
q,
input start,
output reg signed [63:0] Real,
Imaginary,
output reg finish
);
wire finished, finished_LV1, finished_LV2, finished_CR;
wire [63:0] mozhi;
wire signed [63:0] angle1, angle, Sin... | 6.700154 |
module complex_freq #(
parameter refcnt_w = 17
) (
input clk, // single clock domain
input signed [17:0] sdata,
input sgate, // high for two cycles representing I and Q
output signed [refcnt_w-1:0] freq,
output freq_valid, // Asserted when freq output is valid
output [16:0] amp_max,
output [16:0] amp_min,
ou... | 6.827035 |
module complex_freq_tb;
reg clk;
integer cc;
reg fail = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("complex_freq.vcd");
$dumpvars(5, complex_freq_tb);
end
for (cc = 0; cc < 20000; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#5;
end
if (fail)... | 6.904524 |
module complex_freq_wrap #(
parameter n_chan = 12,
parameter sr_wi = 40, // Conveyor belt data width
parameter shift_base = 4,
parameter refcnt_w = 17
) (
input clk, // single clock domain
input [1:0] channel_sel, // 0 - Field, 1 - Forward, 2 - Reverse, 3 - IQ_Fiber (from PRC)
... | 6.904524 |
module complex_fsm (
input wire sys_clk, //系统时钟50MHz
input wire sys_rst_n, //全局复位
input wire pi_money_one, //投币1元
input wire pi_money_half, //投币0.5元
output reg po_money, //po_money为1时表示找零
//po_money为0时表示不找零
output reg po_cola //po_cola为1时出可乐
... | 8.231603 |
module gate_aoi (
out,
in
);
input [2:0] in;
output out;
wire line;
and and_inst (line, in[0], in[1]);
nor nor_inst (out, line, in[2]);
endmodule
| 7.363156 |
module gate_ao (
out,
in
);
input [2:0] in;
output out;
wire line;
and and_inst (line, in[0], in[1]);
or or_inst (out, line, in[2]);
endmodule
| 7.17597 |
module uses two 18-bit signed hardware multipliers,
// and can clock at over 100 MHz in Spartan-6.
// It's pretty easy to ask for results that would overflow the representable
// numbers; an extreme case is (1+i)*(1-i) = 2. All such results get
// saturated to the maximum representable positive or negative number.
/... | 7.533921 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
sel: for selection, 2 bits
OV: overflow flag
------------------------------------------------------
History:
01-19-2016: First Version by Garfield
****************************************... | 7.206611 |
module complex_multiplier_test;
reg clk; // Semnal de ceas.
reg rst_n; // Reset asincron activ în 0.
// Interfata cu operatorii
reg op_val; // Operanzi valizi.
wire op_rdy; // Este permisă primirea operanzilor.
reg [2 * 2 * 8 -... | 6.610722 |
module: complex_mult_dsp_impl
* file name: complex_mult_dsp_impl.v
* author: Chen Zhongyao
* date: 2017-09-26
* description:
* use 3 DSPs implement
* input signed width 16 bits
* output signed width 33 bits
* output delay 5 clock cycles
*
* Complex Multilier
* The following code implemen... | 7.4105 |
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