code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module complexmulttrial (
input [15:0] a_r,
input [15:0] a_i,
input [15:0] b_r,
input [15:0] b_i,
input [15:0] w_r,
input [15:0] w_i,
output [15:0] x_r,
output [15:0] x_i,
output [15:0] y_r,
output [15:0] y_i
);
wire [32:0] temp_r;
wire [32:0] temp_i;
assign x_r = a... | 6.737632 |
module complexmulttrial2 (
input [15:0] a_r,
input [15:0] a_i,
input [15:0] b_r,
input [15:0] b_i,
input [15:0] w_r,
input [15:0] w_i,
output [15:0] x_r,
output [15:0] x_i,
output [15:0] y_r,
output [15:0] y_i,
output [32:0] temp_r,
output [32:0] temp_i
);
wire ... | 6.737632 |
module complexmulttrial2_tb ();
reg [15:0] a_i;
reg [15:0] a_r;
reg [15:0] b_i;
reg [15:0] b_r;
reg [15:0] w_r;
reg [15:0] w_i;
wire [15:0] x_r;
wire [15:0] x_i;
wire [15:0] y_r;
wire [15:0] y_i;
wire [32:0] temp_r;
wire [32:0] temp_i;
integer i;
complexmulttrial2 cmt2 (
a_r,
... | 6.737632 |
module complexmulttrial_tb ();
reg [15:0] a_i;
reg [15:0] a_r;
reg [15:0] b_i;
reg [15:0] b_r;
reg [15:0] w_r;
reg [15:0] w_i;
wire [15:0] x_r;
wire [15:0] x_i;
wire [15:0] y_r;
wire [15:0] y_i;
integer i;
complexmulttrial cmt (
a_r,
a_i,
b_r,
b_i,
w_r,
w_... | 6.737632 |
module complex_mul_flat (
input clk, // Rising edge clock input; all logic is synchronous in this domain
input gate_in, // Flag marking input data valid
input signed [17:0] x_I, // Multiplicand 1, real
input signed [17:0] x_Q, // Multiplicand 1, imag
input signed [17:0] y_I, // Multiplicand 2, ... | 7.03025 |
module complex_sinusoid_ddfs #(
parameter ROM_DEPTH = 32768,
ROM_WIDTH = 16
) (
input wire i_clk,
input wire i_rst,
input wire [31:0] i_freq_control, //freq will increase as i_freq_control increases
input wire [1:0] i_invert_out,
output reg signed [ROM_WIDTH-1:0] o_real = 0,
output reg... | 6.660952 |
module complex_subst_ksa_32b (
A32,
B32,
R32,
C_OUT32
);
input [31:0] A32;
input [31:0] B32;
output [31:0] R32;
output [1:0] C_OUT32;
wire [31:0] A32;
wire [31:0] B32;
wire [31:0] R32;
wire [ 1:0] C_OUT32;
wire [15:0] REAL_A32;
wire [15:0] REAL_B32;
wire [15:0] REAL_R32;
wire ... | 7.413812 |
module complex_sum (
input wire signed [15 : 0] Re_1,
input wire signed [15 : 0] Im_1,
input wire signed [15 : 0] Re_2,
input wire signed [15 : 0] Im_2,
output wire signed [15 : 0] Re_out,
output wire signed [15 : 0] Im_out
);
wire signed [16 : 0] w_Re = Re_1 + Re_2;
wire signed [16 : 0... | 6.735656 |
module Complex_Sum1 (
In1,
In2,
Out1_re,
Out1_im
);
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2; // sfix37_En22
output signed [36:0] Out1_re; // sfix37_En22
output signed [36:0] Out1_im; // sfix37_En22
wire signed [36:0] Complex_to_Real_Imag1_out1; // sfix37_En22
... | 7.155836 |
module Complex_Sum1_block (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_re... | 7.023238 |
module Complex_Sum1_block1 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.023238 |
module Complex_Sum1_block10 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block11 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block12 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block13 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block15 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block16 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block17 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block18 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block19 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input In1_re; // ufix1
input In1_im; // ufix1
input In2_re; // ufix1
input In2_im; // ufix1
output signed [36:0] Out1_re; // sfix37_En22
output signed [36:0] Out1_im; // sfix37_En22
wire sig... | 7.023238 |
module Complex_Sum1_block2 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.023238 |
module Complex_Sum1_block24 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block25 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block26 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block27 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block28 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block29 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block3 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.023238 |
module Complex_Sum1_block30 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block31 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block32 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block33 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.023238 |
module Complex_Sum1_block4 (
In1,
In2,
Out1_re,
Out1_im
);
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2; // sfix37_En22
output signed [36:0] Out1_re; // sfix37_En22
output signed [36:0] Out1_im; // sfix37_En22
wire signed [36:0] Complex_to_Real_Imag1_out1; // sfix37... | 7.023238 |
module Complex_Sum1_block5 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.023238 |
module Complex_Sum1_block6 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.023238 |
module Complex_Sum1_block7 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.023238 |
module Complex_Sum1_block8 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.023238 |
module Complex_Sum1_block9 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.023238 |
module Complex_Sum2 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_re; // ... | 6.737022 |
module Complex_Sum2_block (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block1 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block10 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block11 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block12 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block13 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block14 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block2 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block20 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block21 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block22 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block23 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block24 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block25 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block26 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block27 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block28 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block29 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block3 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block30 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block31 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block32 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block33 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 7.401262 |
module Complex_Sum2_block4 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.401262 |
module Complex_Sum2_block5 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block6 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block7 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block8 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.401262 |
module Complex_Sum2_block9 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.401262 |
module Complex_Sum3 (
In1_re,
In1_im,
In2,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2; // sfix37_En22
output signed [36:0] Out1_re; // sfix37_En22
output signed [36:0] Out1_im; // sfix37_En22
... | 7.240716 |
module Complex_Sum3_block (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 6.942457 |
module Complex_Sum3_block1 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 6.942457 |
module Complex_Sum3_block10 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block11 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block12 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block13 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block19 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input In2_re; // ufix1
input In2_im; // ufix1
output signed [36:0] Out1_re; // sfix37_En22
output signed [36:... | 6.942457 |
module Complex_Sum3_block2 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 6.942457 |
module Complex_Sum3_block20 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 6.942457 |
module Complex_Sum3_block21 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 6.942457 |
module Complex_Sum3_block22 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block23 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block24 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block25 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block26 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block27 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block28 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block29 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block3 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 6.942457 |
module Complex_Sum3_block30 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block31 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block32 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block33 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_... | 6.942457 |
module Complex_Sum3_block4 (
In1_re,
In1_im,
In2,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2; // sfix37_En22
output signed [36:0] Out1_re; // sfix37_En22
output signed [36:0] Out1_im; // sfix37_En... | 6.942457 |
module Complex_Sum3_block5 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 6.942457 |
module Complex_Sum3_block6 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 6.942457 |
module Complex_Sum3_block7 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 6.942457 |
module Complex_Sum3_block8 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 6.942457 |
module Complex_Sum3_block9 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 6.942457 |
module Complex_Sum_block (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
i... | 7.61236 |
module Complex_Sum_block1 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
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