code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Complex_Sum_block10 (
clk,
reset_x,
enb,
In1,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36... | 7.61236 |
module Complex_Sum_block11 (
clk,
reset_x,
enb,
In1,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36... | 7.61236 |
module Complex_Sum_block12 (
clk,
reset_x,
enb,
In1,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36... | 7.61236 |
module Complex_Sum_block13 (
clk,
reset_x,
enb,
In1,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36... | 7.61236 |
module Complex_Sum_block14 (
In1,
In2,
Out1_re,
Out1_im
);
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2; // sfix37_En22
output signed [36:0] Out1_re; // sfix37_En22
output signed [36:0] Out1_im; // sfix37_En22
wire signed [36:0] Complex_to_Real_Imag1_out1; // sfix37... | 7.61236 |
module Complex_Sum_block15 (
clk,
reset_x,
enb,
In1,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36... | 7.61236 |
module Complex_Sum_block16 (
clk,
reset_x,
enb,
In1,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36... | 7.61236 |
module Complex_Sum_block17 (
clk,
reset_x,
enb,
In1,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36... | 7.61236 |
module Complex_Sum_block18 (
clk,
reset_x,
enb,
In1,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36... | 7.61236 |
module Complex_Sum_block19 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.61236 |
module Complex_Sum_block2 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block20 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block21 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block22 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.61236 |
module Complex_Sum_block23 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block24 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block25 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block26 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block27 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block28 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block29 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block3 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block30 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block31 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block32 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block33 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block34 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block35 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block36 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block37 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block38 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block39 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block4 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block40 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block41 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block42 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block43 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block44 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.61236 |
module Complex_Sum_block45 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block46 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block47 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block48 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block49 (
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
input signed [36:0] In2_im; // sfix37_En22
output signed [36:0] Out1_r... | 7.61236 |
module Complex_Sum_block5 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block50 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block51 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block52 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block53 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block6 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block7 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block8 (
clk,
reset_x,
enb,
In1_re,
In1_im,
In2_re,
In2_im,
Out1_re,
Out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] In1_re; // sfix37_En22
input signed [36:0] In1_im; // sfix37_En22
input signed [36:0] In2_re; // sfix37_En22
... | 7.61236 |
module Complex_Sum_block9 (
In1,
In2,
Out1_re,
Out1_im
);
input signed [36:0] In1; // sfix37_En22
input signed [36:0] In2; // sfix37_En22
output signed [36:0] Out1_re; // sfix37_En22
output signed [36:0] Out1_im; // sfix37_En22
wire signed [36:0] Complex_to_Real_Imag1_out1; // sfix37_... | 7.61236 |
module complex_to_mag #(
parameter DATA_WIDTH = 16
) (
input clock,
input enable,
input reset,
input signed [DATA_WIDTH-1:0] i,
input signed [DATA_WIDTH-1:0] q,
input input_strobe,
output reg [DATA_WIDTH-1:0] mag,
output reg mag_stb
);
reg [DATA_WIDTH-1:0] abs_i;
reg [DATA_WID... | 7.327847 |
module complex_to_magsq #(
parameter WIDTH = 16
) (
input clk,
input reset,
input clear,
input [2*WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [2*WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH-1:0] ii_td... | 7.327847 |
module complex_to_mag_sq (
input clock,
input enable,
input reset,
input signed [15:0] i,
input signed [15:0] q,
input input_strobe,
output [31:0] mag_sq,
output mag_sq_strobe
);
reg valid_in;
reg [15:0] input_i;
reg [15:0] input_q;
reg [15:0] input_q_neg;
complex_mult mult... | 7.327847 |
module cordic_cv (
input clock,
input reset,
input [63:0] io_x,
input [63:0] io_y,
output [63:0] io_theta,
output [63:0] io_r
);
wire cordic_cv_unit_clock; // @[Cordic_CV.scala 104:30]
wire cordic_cv_unit_reset; // @[Cordic_CV.scala 104:30]
wire [63:0] cordic_cv_unit_io... | 7.286598 |
module cordic_divide (
input clock,
input reset,
input [63:0] io_x,
input [63:0] io_y,
output [63:0] io_z
);
wire [63:0] unit_io_x; // @[Cordic_LV.scala 131:22]
wire [63:0] unit_io_out; // @[Cordic_LV.scala 131:22]
wire [5:0] unit_io_cnt; // @[Cordic_LV.scala 131:22]
wir... | 7.37034 |
module for making two's compliment
//////////////////////////////////////////////////////////////////
`timescale 1ns/100ps
module compliment(OUT,IN);
output [7:0] OUT;
input [7:0] IN;
assign #1 OUT= ~IN+1'b1; //making two's compliment of input
endmodule
| 6.63298 |
module compliment2_10bit (
in,
out
);
input [9:0] in;
output [9:0] out;
wire [9:0] not_in;
assign not_in = ~in;
adder_10bit add_1 (
.in1(not_in),
.in2(10'd1),
.S(out),
.Cout()
);
endmodule
| 7.583016 |
module compliment2_9bit (
in,
out
);
input [8:0] in;
output [8:0] out;
wire [8:0] not_in;
assign not_in = ~in;
adder_9bit add_1 (
.in1(not_in),
.in2(9'd1),
.S(out),
.Cout()
);
endmodule
| 7.553209 |
module: compliment2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module compliment2_tb;
// Inputs
reg [3:0] A;
// Outputs
wire [3:0] OUT;
// Instantiate the Unit Under Test (UUT)... | 6.664215 |
module fulladder (
input [3:0] a,
input [3:0] b,
input c_in,
output c_out,
output [3:0] sum
);
assign {c_out, sum} = a + b + c_in;
endmodule
| 7.454465 |
module compl (
input wire [3:0] D_n, // inverted data
input wire BCD_ctrl_n, // 0 - bin, 1-bcd
output wire [3:0] out
);
wire [3:0] a;
assign a = {~BCD_ctrl_n, 1'b0, 1'b0, ~BCD_ctrl_n};
wire [3:0] s;
fulladder cmpl (
.a(a),
.b(D_n),
.c_in(~BCD_ctrl_n),
.sum(s)
);
assi... | 7.33311 |
module compl_collater (
output wire adder_b,
input wire clk,
input wire c2, // A order - add number into accumulator.
input wire c3, // S order - subtract.
input wire c4, // C order - collate with Multiplier and add into accumulator.
input wire c7, // R order - right shift.
input wire c... | 6.916955 |
module compl_fifo_fifo_generator_ramfifo (
empty,
full,
dout,
clk,
srst,
din,
rd_en,
wr_en
);
output empty;
output full;
output [81:0] dout;
input clk;
input srst;
input [81:0] din;
input rd_en;
input wr_en;
wire clk;
wire [81:0] din;
wire [81:0] dout;
wire empty... | 6.928594 |
module compl_fifo_fifo_generator_top (
empty,
full,
dout,
clk,
srst,
din,
rd_en,
wr_en
);
output empty;
output full;
output [81:0] dout;
input clk;
input srst;
input [81:0] din;
input rd_en;
input wr_en;
wire clk;
wire [81:0] din;
wire [81:0] dout;
wire empty;
... | 6.928594 |
module compl_fifo_fifo_generator_v13_2_2_synth (
empty,
full,
dout,
clk,
srst,
din,
rd_en,
wr_en
);
output empty;
output full;
output [81:0] dout;
input clk;
input srst;
input [81:0] din;
input rd_en;
input wr_en;
wire clk;
wire [81:0] din;
wire [81:0] dout;
wire... | 6.928594 |
module regfile (
output wire [7:0] RD1,
RD2, //datos leidos
input wire clk, // Señal de reloj
input wire we3, //señal de habilitación de escritura
input wire [3:0] RA1,
RA2,
WA3, //direcciones de regs leidos y reg a escribir
input wire [7:0] WD3
); //dato a escribir
... | 7.809308 |
module sum (
output wire [9:0] Y, // Salida del sumador
input wire [9:0] A,
B
); // Operandos de la suma
assign Y = A + B;
endmodule
| 7.616818 |
module registro #(
parameter WIDTH = 8
) (
output reg [WIDTH-1:0] Q, // Salida del registro
input wire clk,
reset, // Señales de reloj y reseteo
input wire [WIDTH-1:0] D
); // Entrada al registro
always @(posedge clk, posedge reset)
if (reset) Q <= 0;
else Q <= D;
endm... | 8.119648 |
module mux2 #(
parameter WIDTH = 8
) (
output wire [WIDTH-1:0] Y, // Salida del multiplexor
input wire [WIDTH-1:0] D0,
D1, // Entradas del multiplexor
input wire s
); // Selección
assign Y = s ? D1 : D0;
endmodule
| 9.827805 |
module ff #(
parameter WIDTH = 32
) (
d,
clk,
clrn,
en,
q
);
input [WIDTH-1:0] d;
input clk;
input clrn;
input en;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q_reg;
always @(posedge clk or negedge clrn) begin
if (clrn == 1'b0) begin
q_reg <= 'b0;
end else if (clk == 1'... | 7.525989 |
module ff_sclr #(
parameter WIDTH = 32
) (
d,
clk,
clrn,
sclr,
en,
q
);
input [WIDTH-1:0] d;
input clk;
input clrn;
input sclr;
input en;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q_reg;
always @(posedge clk or negedge clrn) begin
if (clrn == 1'b0) begin
q_reg <= 'b... | 7.289155 |
module pipeline_reg_sclr #(
parameter WIDTH = 32
) (
d,
clk,
clrn,
sclr,
en,
q
);
input [WIDTH-1:0] d;
input clk;
input clrn;
input sclr;
input en;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q_reg;
always @(posedge clk or negedge clrn) begin
if (clrn == 1'b0) begin
q... | 7.452929 |
module muxMto1 #(
parameter N = 8, // number of bits wide
parameter M = 4, // number of inputs
parameter S = 2 // number of select lines
) (
Z,
SEL,
D
);
localparam W = M * N;
`define DTOTAL W-1: 0
`define DWIDTH N-1: 0
`define SELW S-1: 0
`define WORDS M-1: 0
input [`DTOTAL] ... | 8.551769 |
module bufg #(
parameter tphl = 1,
tplh = 1
) (
out,
in
);
input in;
output out;
bufif1 #(tplh, tphl) inst (out, in, 1'b1);
endmodule
| 6.809788 |
module notg #(
parameter tphl = 1,
tplh = 1
) (
out,
in
);
input in;
output out;
not #(tplh, tphl) inst (out, in);
endmodule
| 7.204853 |
module and_n #(
parameter n = 2,
tphl = 1,
tplh = 1
) (
out,
in
);
input [n-1:0] in;
output out;
wire [n-2:0] mwire;
genvar i;
and and_0 (mwire[0], in[0], in[1]);
generate
for (i = 1; i <= n - 2; i = i + 1) begin : AND_N
and inst (mwire[i], mwire[i-1], in[i+1]);
end
en... | 7.888794 |
module or_n #(
parameter n = 2,
tphl = 1,
tplh = 1
) (
out,
in
);
input [n-1:0] in;
output out;
wire [n-2:0] mwire;
genvar i;
or or_0 (mwire[0], in[0], in[1]);
generate
for (i = 1; i <= n - 2; i = i + 1) begin : OR_N
or inst (mwire[i], mwire[i-1], in[i+1]);
end
endgene... | 8.034491 |
module nand_n #(
parameter n = 2,
tphl = 1,
tplh = 1
) (
out,
in
);
input [n-1:0] in;
output out;
wire [n-2:0] mwire;
genvar i;
and and_0 (mwire[0], in[0], in[1]);
generate
for (i = 1; i <= n - 2; i = i + 1) begin : NAND_N
and inst (mwire[i], mwire[i-1], in[i+1]);
end
... | 8.253204 |
module nor_n #(
parameter n = 2,
tphl = 1,
tplh = 1
) (
out,
in
);
input [n-1:0] in;
output out;
wire [n-2:0] mwire;
genvar i;
or nor_0 (mwire[0], in[0], in[1]);
generate
for (i = 1; i <= n - 2; i = i + 1) begin : NOR_N
or inst (mwire[i], mwire[i-1], in[i+1]);
end
endg... | 8.437369 |
module xor_n #(
parameter n = 2,
tphl = 1,
tplh = 1
) (
out,
in
);
input [n-1:0] in;
output out;
wire [n-2:0] mwire;
genvar i;
xor xor_0 (mwire[0], in[0], in[1]);
generate
for (i = 1; i <= n - 2; i = i + 1) begin : XOR_N
xor inst (mwire[i], mwire[i-1], in[i+1]);
end
en... | 7.99212 |
module xnor_n #(
parameter n = 2,
tphl = 1,
tplh = 1
) (
out,
in
);
input [n-1:0] in;
output out;
wire [n-2:0] mwire;
genvar i;
xor xnor_0 (mwire[0], in[0], in[1]);
generate
for (i = 1; i <= n - 2; i = i + 1) begin : XNOR_N
xor inst (mwire[i], mwire[i-1], in[i+1]);
end
... | 8.021331 |
module fanout_n #(
parameter n = 2,
tphl = 3,
tplh = 5
) (
in,
out
);
input in;
output [n-1 : 0] out;
genvar i;
generate
for (i = 0; i < n; i = i + 1) begin : fanout
bufif1 #(tplh, tphl) inst (out[i], in, 1'b1);
end
endgenerate
endmodule
| 7.682997 |
module pin #(
parameter n = 1
) (
in,
out
);
input [n-1:0] in;
output [n-1:0] out;
genvar i;
generate
for (i = 0; i < n; i = i + 1) begin : PI
bufif1 inst (out[i], in[i], 1'b1);
end
endgenerate
endmodule
| 7.764974 |
module pout #(
parameter n = 1
) (
in,
out
);
input [n-1:0] in;
output [n-1:0] out;
genvar i;
generate
for (i = 0; i < n; i = i + 1) begin : PO
bufif1 inst (out[i], in[i], 1'b1);
end
endgenerate
endmodule
| 7.391169 |
module dff #(
parameter tphl = 0,
tplh = 0
) (
Q,
D,
C,
CLR,
PRE,
CE,
NbarT,
Si,
global_reset
);
input D, C, CLR, PRE, CE, NbarT, Si, global_reset;
output reg Q;
reg val;
always @(posedge C or posedge PRE or posedge CLR or posedge global_reset) begin
if (CLR ||... | 7.149811 |
module composecrc (
i_clk,
i_reset,
i_ce,
i_v,
i_d,
o_v,
o_d,
o_err
);
input wire i_clk, i_reset, i_ce;
//
input wire i_v;
input wire [7:0] i_d;
//
output wire o_v;
output wire [7:0] o_d;
output wire o_err;
//
wire txv;
wire [7:0] txd;
addecrc tx (
i_clk,
... | 6.860107 |
module SimpleButtonController ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input io_buttonInput, // @[:@6.4]
output io_click, // @[:@6.4]
output io_longPress // @[:@6.4]
);
reg [31:0] cycleCounter; // @[SimpleButtonController.scala 13:39:@8.4]
reg [31:0] _RAND_0;
reg ... | 6.572208 |
module TestColorImageGenerator ( // @[:@187.2]
input clock, // @[:@188.4]
input reset, // @[:@189.4]
input [7:0] io_signal1, // @[:@190.4]
input [7:0] io_signal2, // @[:@190.4]
input io_button1, // @[:@190.4]
input io_button2, // @[:@190.4]
outp... | 6.88051 |
module PalGenerator ( // @[:@1112.2]
input clock, // @[:@1113.4]
input reset, // @[:@1114.4]
input [ 7:0] io_green, // @[:@1115.4]
output [ 9:0] io_x, // @[:@1115.4]
output [ 9:0] io_y, // @[:@1115.4]
output [11:0] io_millivolts // @[:@11... | 6.6646 |
module CompositeSignalGenerator ( // @[:@1139.2]
input clock, // @[:@1140.4]
input reset, // @[:@1141.4]
input [ 7:0] io_signal, // @[:@1142.4]
input io_button1, // @[:@1142.4]
input io_button2, // @[:@1142.4]
output [ 3:0] io_leds... | 6.640034 |
module composite_note_player (
input clk,
input reset,
input beat,
input play,
input [1:0] state,
input [14:0] next_song_note,
input [5:0] jam_note,
input load_new_note,
input generate_next_sample,
output reg [15:0] sample_out,
output reg available,
o... | 7.006514 |
module composite_note_player_tb ();
`define JAM_SESH 2'b00
`define COMPOSER 2'b01
`define SONG_PLAYER 2'b11
reg clk;
reg reset;
reg generate_next_sample;
reg [5:0] song_note;
reg [5:0] duration;
wire [11:0] next_song_note = {song_note, duration};
reg [5:0] jam_note;
reg [1:0] state;
reg play;
... | 7.006514 |
module Composite_PAL512 (
input CLK36M, // Input frequency 36MHz (carrier 4.43361875MHz)
input [2:0] RED, //
input [2:0] GREEN, //
input [2:0] BLUE, //
input HSYNC, // HSync input (negative polarity)
input VSYNC, // VSync input (negative polarity)
output reg [6:0] COMP_VIDEO //... | 7.672817 |
module CompositionModule_TopLevel_CompositionModule_Emitter (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire BoardSignals_Clock,
input wire BoardSignals_Reset,
input wire BoardSignals_Running,
input wire BoardSignals_Starting,
input wire BoardSignals_Started,
input wire IsEnabled,... | 6.515576 |
module comp (
input [15:0] treg,
input [7:0] y,
output reg TLTY
);
always @(y, treg) begin
if (y > treg) TLTY = 0;
else TLTY = 1;
end
endmodule
| 6.601597 |
module compress3_2 (
in,
s,
c
);
input [2:0] in;
output s, c;
assign s = in[0] ^ in[1] ^ in[2];
assign c = (in[0] & in[1]) | in[2] & (in[0] | in[1]);
endmodule
| 6.583681 |
module compress4_2 (
in,
cin,
cout,
carry,
sum
);
input [3:0] in;
input cin;
output cout, carry, sum;
wire s;
compress3_2 u1 (
in[3:1],
s,
cout
);
compress3_2 u2 (
.in({in[0], s, cin}),
.s (sum),
.c (carry)
);
endmodule
| 6.603119 |
module compress6_2 (
in,
cin,
cout,
carry,
sum
);
input [5:0] in;
input [2:0] cin;
output sum, carry;
output [2:0] cout;
//wire [8:0] in_temp;
//assign in_temp={in,cin};
wire [2:0] s;
//wire [2:0]c;
compress3_2 comp1 (
in[2:0],
s[0],
cout[0]
);
compress3_2 c... | 6.54151 |
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