code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module counter4tb ();
reg reset;
wire clk;
wire [3:0] out;
clock makeclk (clk);
counter4 counter (
.clock(clk),
.reset(reset),
.out (out)
);
initial begin
$display("\t\t reset \t clk \t out");
$monitor("\t\t %b \t %b \t %b %b %b %b", reset, clk, out[3], out[2], out[1], out[0],... | 7.231168 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add4_COUT (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(1'b0),
.O... | 8.082367 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
SB_DFF inst0 (
.C(CLK),
.D(I[0]),
.Q(inst0_Q)
);
SB_DFF inst1 (
.C(CLK),
.D(I[1]),
.Q(inst1_Q)
);
SB_DFF inst2 (
.C(CLK),
.... | 7.403606 |
module Counter4_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst0_COUT;
wire [3:0] inst1_O;
Add4_COUT inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register4 inst1 (
.I (inst0_O),
.O (ins... | 7.925226 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
wire inst4_O;
wire inst5_O;
wire inst6_O;
wire inst7_O;
wire inst8_O;
wire inst9_O;
wire inst10_O;
wire inst11_O;
LUT2 #(
.INIT(4'h6)
... | 7.542776 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
.INIT(1'h0)
)... | 7.403606 |
module Counter4_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst0_COUT;
wire [3:0] inst1_O;
Add4_cout inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register4 inst1 (
.I (inst0_O),
.O (ins... | 7.925226 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire inst0_O5;
wire inst0_O6;
wire inst1_O;
wire inst2_O;
wire inst3_O5;
wire inst3_O6;
wire inst4_O;
wire inst5_O;
wire inst6_O5;
wire inst6_O6;
wire inst7_O;
wire inst8_O;
wire inst9_O5;
wire ... | 7.542776 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
.INIT(1'h0)
)... | 7.403606 |
module Counter4_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst0_COUT;
wire [3:0] inst1_O;
Add4_cout inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register4 inst1 (
.I (inst0_O),
.O (ins... | 7.925226 |
module counter5 (
enable,
clock,
out,
clr
);
input enable, clock, clr;
output [4:0] out;
wire [4:0] nout;
not not0 (nout[0], out[0]);
not not1 (nout[1], out[1]);
not not2 (nout[2], out[2]);
not not3 (nout[3], out[3]);
not not4 (nout[4], out[4]);
dffe_ref bit0 (
.q (out[0]),
... | 6.576632 |
module counter5b (
clock,
cnt_en,
sclr,
q
);
input clock;
input cnt_en;
input sclr;
output [4:0] q;
wire [4:0] sub_wire0;
wire [4:0] q = sub_wire0[4:0];
lpm_counter lpm_counter_component (
.sclr(sclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
.aclr(1'... | 6.666737 |
module Counter6 (
input CP,
nCR,
En,
output reg [3:0] Q
);
initial begin
Q <= 4'b0000;
end
always @(posedge CP or negedge nCR) begin
if (~nCR) Q <= 4'b0000;
else if (~En) Q <= Q;
else if (Q == 4'b0101) Q <= 4'b0000;
else Q <= Q + 1'b1;
end
endmodule
| 6.527939 |
module Counter60 (
input clk,
input en,
input rst,
input [7:0] cin,
output [3:0] ten,
output [3:0] one,
output rco
);
wire rco1;
Counter c1 (
clk,
en,
rst,
cin[3:0],
10,
one,
rco1
);
Counter c2 (
rco1,
en,
rst,
cin[7... | 6.860348 |
module counter6bdown (
clock,
cnt_en,
sclr,
sset,
q
);
input clock;
input cnt_en;
input sclr;
input sset;
output [5:0] q;
wire [5:0] sub_wire0;
wire [5:0] q = sub_wire0[5:0];
lpm_counter lpm_counter_component (
.sclr(sclr),
.clock(clock),
.sset(sset),
.cnt_... | 6.83029 |
module counter6bit_cgrundey (
clock,
clear,
enable,
count
);
input clock;
input clear;
input enable;
output [5:0] count;
reg [5:0] count;
parameter CLRDEL = 10;
parameter CLKDEL = 15;
parameter MAXVAL = 6'd63;
always @(posedge clock or posedge clear) begin
if (clear) count <= #CLR... | 6.911365 |
module counter74x161 (
CEP,
CET,
PE,
CLK,
CR,
D,
TC,
Q
);
parameter N = 4;
parameter M = 16;
input CEP, CET, PE, CLK, CR; //控制信号输入
input [N-1:0] D; // 并行数据输入
output reg TC; //进位输出
output reg [N-1:0] Q; //数据输出
wire CE; //中间变量
assign CE = CEP & CET; // CE = 1时，计数器计数
... | 7.181114 |
module counter7b (
clock,
cnt_en,
sclr,
q
);
input clock;
input cnt_en;
input sclr;
output [6:0] q;
wire [6:0] sub_wire0;
wire [6:0] q = sub_wire0[6:0];
lpm_counter lpm_counter_component (
.sclr(sclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
.aclr(1'... | 6.554521 |
module counter8 (
input [3:0] COUNTER_IN_LOW, //
input [7:4] COUNTER_IN_HIGH, //
input MPC_LOAD_BAR, //
input RESET, //
input COUNT, //
input SYSTEM_CLK, //
output [7:0] COUNTER_OUT //
);
// WIRES
wire CARRY;
w... | 6.879794 |
module counter8b (
clock,
cnt_en,
sclr,
q
);
input clock;
input cnt_en;
input sclr;
output [7:0] q;
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
lpm_counter lpm_counter_component (
.sclr(sclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
.aclr(1'... | 6.541684 |
module dflipflop (
d,
q,
clock,
reset
);
input reset;
input clock;
input d;
output reg q;
always @(negedge reset, posedge clock) begin
if (reset == 0) q <= 1'b0;
else q <= d;
end
endmodule
| 7.751981 |
module tflipflop (
t,
q,
clock,
reset
);
input t;
output q;
input clock;
input reset;
dflipflop dffIn (
t ^ q,
q,
clock,
reset
);
endmodule
| 6.576555 |
module counter4Bit (
SW,
KEY,
HEX0,
HEX1,
LEDR
);
input [1:0] SW;
input [1:0] KEY;
output [6:0] HEX0, HEX1;
output [9:0] LEDR;
wire [7:0] numCount;
assign enable = SW[1];
assign clock = KEY[0];
assign resetb = SW[0];
wire [7:0] q;
tflipflop u1 (
enable,
q[0],
c... | 7.286604 |
module counter8b_updown (
output reg [7:0] count,
input clk,
reset,
dir
);
initial begin
count = 0;
end
always @(posedge clk, reset) begin
case (dir)
1: count = count + 1;
0: count = count - 1;
endcase
if (reset == 1) begin
count = 0;
end
end
endmodule
| 6.611152 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add8_COUT (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire inst6... | 7.479272 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
wire inst4_Q;
wire inst5_Q;
wire inst6_Q;
wire inst7_Q;
SB_DFF inst0 (
.C(CLK),
.D(I[0]),
.Q(inst0_Q)
);
SB_DFF inst1 (
.C(CLK),
.D(I[1])... | 6.73316 |
module Counter8_COUT (
output [7:0] O,
output COUT,
input CLK
);
wire [7:0] inst0_O;
wire inst0_COUT;
wire [7:0] inst1_O;
Add8_COUT inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register8 inst1 (
.I (... | 7.314885 |
module JK_FF (
input CLK,
input J,
input K,
input RST_n,
output reg Q1
);
reg [1:0] JK;
always @(posedge CLK or negedge RST_n or negedge RST_n) begin
JK = {J, K};
if (RST_n == 0) Q1 <= 0;
else begin
case (JK)
2'b01: Q1 <= 0;
2'b10: Q1 <= 1;
2'b11: Q1 = ~... | 6.774624 |
module Counter8_myselftest (
input CLK, //ʱźţЧ
input rst_n, //λźţ͵ƽЧ
output wire [2:0] oQ, //Ƽ
output wire [6:0] oDisplay //߶ʾ
);
wire temp, Clock;
JK_FF JK_FF_test0 (
.CLK(Clock),
.J(1'b1),
.K(1'b1),
.rst_n(rst_n),
.oQ1(oQ[0]),
.oQ2()
);
JK_FF JK_FF_test1... | 7.258185 |
module Counter8_myselftest_tb;
reg CLK;
reg rst_n;
wire [2:0] oQ;
wire [6:0] oDisplay;
initial begin
CLK = 0;
rst_n = 0;
#20 rst_n = 1;
#500 rst_n = 0;
end
always #1 CLK = ~CLK;
Counter8_myselftest Counter8_myselftest_test (
.CLK(CLK),
.rst_n(rst_n),
.oQ(oQ),
... | 7.258185 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
wire inst4_O;
wire inst5_O;
wire inst6_O;
wire inst7_O;
wire inst8_O;
wire inst9_O;
wire inst10_O;
wire inst11_O;
wire inst12_O;
wire inst... | 7.265928 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
wire inst4_Q;
wire inst5_Q;
wire inst6_Q;
wire inst7_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D ... | 6.73316 |
module Counter8_COUT (
output [7:0] O,
output COUT,
input CLK
);
wire [7:0] inst0_O;
wire inst0_COUT;
wire [7:0] inst1_O;
Add8_cout inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register8 inst1 (
.I (... | 7.314885 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire inst0_O5;
wire inst0_O6;
wire inst1_O;
wire inst2_O;
wire inst3_O5;
wire inst3_O6;
wire inst4_O;
wire inst5_O;
wire inst6_O5;
wire inst6_O6;
wire inst7_O;
wire inst8_O;
wire inst9_O5;
wire ... | 7.265928 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
wire inst4_Q;
wire inst5_Q;
wire inst6_Q;
wire inst7_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D ... | 6.73316 |
module Counter8_COUT (
output [7:0] O,
output COUT,
input CLK
);
wire [7:0] inst0_O;
wire inst0_COUT;
wire [7:0] inst1_O;
Add8_cout inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register8 inst1 (
.I (... | 7.314885 |
module Counter8_tb ();
reg CLK;
reg rst_n;
wire [2:0] oQ;
wire [6:0] oDisplay;
Counter8 uut (
.CLK(CLK),
.rst_n(rst_n),
.oQ(oQ),
.oDisplay(oDisplay)
);
initial begin
CLK = 1'b0;
forever #10 CLK = ~CLK;
end
initial begin
rst_n = 1'b0;
#50 rst_n = 1'b1;
end
... | 7.057075 |
module counterB (
input clk,
input rstn,
output reg [3:0] out
);
always @(posedge clk) begin
if (!rstn) out <= 0;
else out <= out + 1;
end
endmodule
| 8.306779 |
module CounterBoard (
CLOCK_50,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
KEY,
LEDR,
SW
);
input CLOCK_50; // 50MHz clock.
output reg [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
output [9:0] LEDR;
input [3:0] KEY; // True when not pressed, False when pressed
input [9:0] SW;
... | 6.509301 |
module counterBuffer (
input [20:0] counter,
input enablepulse,
output [20:0] q,
output clear
);
reg [20:0] data;
reg clear_tmp = 1'b0;
always @(negedge enablepulse) begin
data[20:0] <= counter[20:0];
clear_tmp <= 1'b1;
end
assign clear = clear_tmp;
assign q = data;
endmodule
| 6.990522 |
module counterbusmux (
data0x,
data1x,
sel,
result
);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
wire [3:0] sub_wire0;
wire [3:0] sub_wire5 = data1x[3:0];
wire [3:0] result = sub_wire0[3:0];
wire sub_wire1 = sel;
wire sub_wire2 = sub_wire1;
wire [3:0] s... | 7.141534 |
module counterbusmux (
data0x,
data1x,
sel,
result
);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
endmodule
| 7.141534 |
module counterC (
clk,
resetn,
enable,
erase,
color,
x,
y,
plot,
done
);
input clk, resetn, enable, erase;
output reg plot;
output reg [7:0] x;
output reg [6:0] y;
wire [7:0] addr;
//wire [2:0] color_out;
output reg [2:0] color;
output reg done;
parameter width = 1... | 6.916177 |
module Div20x (
rst,
clk,
cet,
cep,
count,
tc
);
// TITLE 'Divide-by-20 Counter with enables'
// enable CEP is a clock enable only
// enable CET is a clock enable and
// enables the TC output
// a counter using the Verilog language
parameter size = 5;
parameter length = 20;
inp... | 7.200711 |
module Div20x (
rst,
clk,
cet,
cep,
count,
tc
);
// TITLE 'Divide-by-20 Counter with enables'
// enable CEP is a clock enable only
// enable CET is a clock enable and
// enables the TC output
// a counter using the Verilog language
parameter size = 5;
parameter length = 20;
inp... | 7.200711 |
module CounterClkGen #(
parameter REF_CLK_FREQ = 250, // Reference clock frequency in MHz
parameter OUT_CLK_FREQ = 10 // Output clock frequency in MHz
) (
input wire refclk,
input wire rst,
output wire clk_o
);
function integer clogb2;
input [31:0] value;
begin
value = value -... | 7.15768 |
module counterDflipflopWithAsyncClkDown4bit (
count,
Clk,
ClrN
);
output [3:0] count;
input Clk, ClrN;
wire w3, w2, w1, w0;
wire [3:0] dummy;
flipflopDposClknegRst
c0 (
w0,
dummy[0],
~w0,
Clk,
ClrN
),
c1 (
w1,
... | 7.15616 |
module counterDflipflopWithAsyncClkDown4bit_tb ();
input [3:0] count;
output reg Clk, ClrN;
counterDflipflopWithAsyncClkDown4bit dffAsynClock (
count,
Clk,
ClrN
);
initial /*stimulus*/
begin
$dumpfile("Simulation/counterDflipflopWithAsyncClkDown4bit_tb.vcd");
$dumpvars;
$mon... | 7.15616 |
module counterDflipflopWithAsyncClkUp4bit (
count,
Clk,
ClrN
);
output [3:0] count;
input Clk, ClrN;
wire w3, w2, w1, w0;
flipflopDnegClknegRst
c0 (
w0
,,
~w0,
Clk,
ClrN
),
c1 (
w1
,,
~w1,
w0... | 7.15616 |
module counterDflipflopWithAsyncClkUp4bit_tb ();
wire [3:0] count;
reg Clk, ClrN;
counterDflipflopWithAsyncClkUp4bit dffAsynClock (
count,
Clk,
ClrN
);
initial /*stimulus*/
begin
$dumpfile("Simulation/counterDflipflopWithAsyncClkUp4bit_tb.vcd");
$dumpvars;
$monitor($time, " ... | 7.15616 |
module counterdivider (
clk,
out
);
input clk;
output [2:0] out;
// reg clk_N;
divider(
clk, clk_N
); counter(
.clk(clk_N), .out(out)
);
// divider(clk, clk_N)
endmodule
| 7.206086 |
module counterdown16 (
clk,
reset,
count
);
input clk, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 16'hffff;
end
always @(posedge clk or negedge reset) begin
if (reset == 1'b0) count <= 16'hffff;
else count <= count - 1;
end
endmodule
| 7.125353 |
module counterdown16_1clk_negedge_async_resetn (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 16'hffff;
end
always @(negedge clock0 or negedge reset) begin
if (reset == 1'b0) begin
count <= 16'hffff;
end else begi... | 7.125353 |
module counterdown16_1clk_negedge_async_resetp (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 16'hffff;
end
always @(negedge clock0 or posedge reset) begin
if (reset == 1'b1) begin
count <= 16'hffff;
end else begi... | 7.125353 |
module counterdown16_1clk_negedge_sync_resetn (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
always @(negedge clock0) begin
if (reset == 1'b0) begin
count <= 16'hffff;
end else begin
count <= count - 1;
end
end
endmodule
| 7.125353 |
module counterdown16_1clk_negedge_sync_resetp (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
always @(negedge clock0) begin
if (reset == 1'b1) begin
count <= 16'hffff;
end else begin
count <= count - 1;
end
end
endmodule
| 7.125353 |
module counterdown16_1clk_posedge_async_resetn (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 16'hffff;
end
always @(posedge clock0 or negedge reset) begin
if (reset == 1'b0) begin
count <= 16'hffff;
end else begi... | 7.125353 |
module counterdown16_1clk_posedge_async_resetp (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 16'hffff;
end
always @(posedge clock0 or posedge reset) begin
if (reset == 1'b1) begin
count <= 16'hffff;
end else begi... | 7.125353 |
module counterdown16_1clk_posedge_sync_resetn (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 16'hffff;
end
always @(posedge clock0) begin
if (reset == 1'b0) begin
count <= 16'hffff;
end else begin
count <= c... | 7.125353 |
module counterdown16_1clk_posedge_sync_resetp (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 16'hffff;
end
always @(posedge clock0) begin
if (reset == 1'b1) begin
count <= 16'hffff;
end else begin
count <= c... | 7.125353 |
module counterdown16_4clk_posedge_async_resetn (
clock0,
clock1,
clock2,
clock3,
reset,
cnt0_16,
cnt1_16,
cnt2_16,
cnt3_16
);
input clock0, clock1, clock2, clock3;
input reset;
output [15:0] cnt0_16;
output [15:0] cnt1_16;
output [15:0] cnt2_16;
output [15:0] cnt3_16;
... | 7.125353 |
module counterfour (
input clk,
input rst,
input pulse,
input en_count,
output reg [15:0] count
);
wire rise_edge;
wire fall_edge;
reg [1:0] r_pulse;
//reg [15:0] cnt;
//
// ؼ
//
always @(posedge clk) begin
if (!rst) be... | 6.800516 |
module counterfunc #(
parameter integer WIDTH = 5
) (
input wire clk,
input wire rst,
input wire load,
input wire enab,
input wire [WIDTH-1:0] cnt_in,
output reg [WIDTH-1:0] cnt_out
);
//////////////////////////////////////////////////////////////////////////////
//TO DO: DEFINE THE CO... | 7.9802 |
module counterfunc_test;
localparam WIDTH=5;
reg clk ;
reg rst ;
reg load ;
reg enab ;
reg [WIDTH-1:0] cnt_in;
wire [WIDTH-1:0] cnt_out;
counterfunc
#(
.WIDTH ( WIDTH )
)
counter_inst
(
.clk ( clk ),
.rst ( rst ),
.load ( load ),
.enab ... | 6.55828 |
module counterM (
input wire clk,
input wire reset,
output empty
);
// Value of counter to set on 'reset'
parameter M = 35;
// Number of bits needed to store value of counter
localparam N = $clog2(M) + 1;
// Register to store counter value
reg [N-1:0] divcounter = 0;
// Counter: will only ... | 6.790811 |
module counter_mod10 (
output reg [3:0] ones,
output wire tc,
zero,
input wire [3:0] data,
input wire loadn,
clrn,
clock,
enable
);
assign tc = (enable && (ones == 0));
assign zero = ones == 0;
always @(posedge clock or negedge clrn) begin
if (!clrn) begin
ones <= 0;
... | 7.191868 |
module counter_mod6 (
output reg [3:0] ones,
output wire tc,
zero,
input wire [3:0] data,
input wire loadn,
clrn,
clock,
enable
);
assign tc = (enable && (ones == 0));
assign zero = (ones == 0);
always @(posedge clock or negedge clrn) begin
if (!clrn) ones <= 0;
else if... | 7.068199 |
module CounterModN #(
parameter N = 5,
parameter BITS = 3
) (
input en,
clr,
clk,
rst,
output reg [BITS-1:0] cnt,
output co
);
always @(posedge clk or posedge rst) begin
if (rst) cnt <= {BITS{1'b0}};
else if (clr) cnt <= {BITS{1'b0}};
else if (en) begin
if (co) cnt <=... | 8.301586 |
module counterMonitor (
clk,
reset,
enable,
count
);
input clk, reset, enable;
input [3:0] count;
wire clk, reset, enable;
wire [3:0] count;
initial $counterMonitor(clk, reset, enable, count);
endmodule
| 7.218509 |
module countern (
clk,
rst,
load,
en,
data_in,
data_out
);
parameter [1:0] COUNTER_STYLE_1 = 2'b01, COUNTER_STYLE_2 = 2'b10, COUNTER_STYLE_3 = 2'b11;
parameter [31:0] n = 2;
parameter [31:0] step = 1;
parameter [1:0] style = COUNTER_STYLE_1;
input clk;
input rst;
input load;
inpu... | 7.44423 |
module counterpip (
data_in,
en0,
en1,
clr,
clk,
load,
data_out,
data_out_next
);
parameter DATAWIDTH = 32;
parameter UPPERLIMIT = 4096;
input wire [DATAWIDTH-1:0] data_in;
input wire en0;
input wire en1;
input wire clr;
input wire clk;
input wire load;
output reg [DAT... | 7.356208 |
module counterrr (
clk,
out,
reset
);
input clk;
output reg [31:0] out;
input reset;
always @(posedge clk) begin
if (reset) out = 32'd0;
else out <= out + 32'd4;
end
endmodule
| 7.695491 |
module counter1 (
clk,
rst,
ping
);
input clk, rst;
output ping;
reg [31:0] count;
always @(posedge clk) begin
if (rst) count <= 0;
else count <= count + 1;
end
assign ping = &count;
endmodule
| 6.94605 |
module counter_4Hz (
CLK,
resetn,
EnableSignal
); // 4Hz Enable
output reg EnableSignal;
reg [23:0] cout;
input CLK, resetn;
always @(posedge CLK) begin
if (!resetn) begin
cout <= 24'b0;
EnableSignal <= 0;
end else if (cout == 24'b101111101011110000100000) begin
cout <= 2... | 7.24401 |
module counter160_64Hz (
Enable,
Clock,
crtState,
counter160
);
input Enable, Clock;
input [1:0] crtState;
reg [7:0] temp;
output [7:0] counter160;
always @(posedge Clock) begin
if (crtState == 2'b00) temp = 0;
else if (temp == 8'b10100001) begin
temp <= 0;
end else if (Ena... | 6.679701 |
module counter_64Hz (
CLK,
resetn,
EnableSignal
); // 64Hz Enable
output reg EnableSignal;
reg [19:0] cout;
input CLK, resetn;
always @(posedge CLK) begin
if (!resetn) begin
cout <= 20'b0;
EnableSignal <= 0;
end else if (cout == 20'b10111110101111000010) begin
cout <= 20'... | 8.039416 |
module counter_60Hz (
CLOCK,
signal
);
input CLOCK;
output reg signal;
reg [24:0] counter;
always @(posedge CLOCK) begin
if (counter == 25'd50000000) begin
counter <= 0;
signal <= 1;
end else begin
counter <= counter + 1;
signal <= 0;
end
end
endmodule
| 6.635525 |
module Newcounter (
CLOCK,
x_out,
y_out,
ADDRESS
);
input CLOCK;
output reg [7:0] x_out;
output reg [6:0] y_out;
output reg [14:0] ADDRESS;
always @(posedge CLOCK) begin
if (ADDRESS == 15'b100101100000000) ADDRESS = 0;
if (x_out == 8'b10011111) x_out <= 0;
else x_out <= x_ou... | 6.775412 |
module counterselect (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [20:0] data0x;
input [20:0] data1x;
input [20:0] data2x;
input [20:0] data3x;
input [1:0] sel;
output [20:0] result;
wire [20:0] sub_wire5;
wire [20:0] sub_wire4 = data3x[20:0];
wire [20:0] sub_wire3 ... | 6.807782 |
module counterselect (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [20:0] data0x;
input [20:0] data1x;
input [20:0] data2x;
input [20:0] data3x;
input [1:0] sel;
output [20:0] result;
endmodule
| 6.807782 |
module CounterSignal (
input wire clk,
input wire enabled,
output wire signal
);
parameter Total = `B115200;
parameter SignalValue = 0;
localparam bits = $clog2(Total);
// verilator lint_off WIDTH
// Occurs on |Total-1| possibly being a different width to |counter|
reg [bits-1:0] counter = 0;... | 7.749402 |
module counterSimple #(
// =============================================================================
// ** Parameters
// =============================================================================
// Size of word (parent should over-write this if needeD)
parameter N = 10
) (
// ==========... | 7.387603 |
module CounterStack #(
parameter S = 32,
parameter S2 = 5,
parameter CW = 32
) (
input clk,
input reset,
input call_as_cb,
input retn_as_cb,
input [CW-1:0] prev_descendant_count_push,
output [CW-1:0] prev_descendant_count_pop
);
//+++++++++++++++++++++++++++++
// STACK
//+++... | 8.064382 |
module: FourBitCounter
//
////////////////////////////////////////////////////////////////////////////////
module counterStimulus;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] count;
// Instantiate the Unit Under Test (UUT)
FourBitCounter uut (
.clk(clk),
.reset(reset),
.count(count)
);
in... | 7.43427 |
module CounterSynchronus (
KEY,
SW,
HEX0,
HEX1
);
input [0:0] KEY; //Clock.
input [1:0] SW; //SW[0] for Clear_b, SW[1] for Enable.
output [6:0] HEX0;
output [6:0] HEX1;
wire [7:0] wire8bit;
wire [6:0] T;
assign T[0] = SW[1] & wire8bit[0];
assign T[1] = T[0] & wire8bit[1];
assign T[2... | 6.794634 |
module hexDecoder (
in,
out
);
input [3:0] in;
reg [6:0] result;
output [6:0] out;
always @(*) begin
case (in[3:0])
4'b0000: result[6:0] = 7'b1000000;
4'b0001: result[6:0] = 7'b1111001;
4'b0010: result[6:0] = 7'b0100100;
4'b0011: result[6:0] = 7'b0110000;
4'b0100: resul... | 7.643178 |
module counterSyncPosRstWithPosEnUp4bit (
out,
clock,
reset,
enable
); //決定是否隨clock pulse遞增
//port 輸出輸入宣告
output [3:0] out;
input clock, reset, enable;
//port 類型宣告
reg [3:0] out;
wire clock, reset, enable;
//
always @(posedge clock) begin
//如果reset為HIGH就重設output
if (reset == 1... | 7.006601 |
module counterSyncPosRstWithPosEnUp4bit_tb ();
//宣告port類型
reg Clk, reset, enable;
wire [3:0] out;
//D.U.T. instantiation
counterSyncPosRstWithPosEnUp4bit dut (
.out(out),
.clock(Clk),
.reset(reset),
.enable(enable)
);
/* 時脈產生器*/
always begin
#`CLOCK_FREQ Clk = !Clk;
end
... | 7.006601 |
module counters_tb(
// general inputs
input wire clk,
// from behav
input wire [3:0] Q,
input wire RCO, LOAD,
// from syn
output reg [3:0] syn_Q,
output reg syn_RCO, syn_LOAD,
// Generated signals
output reg RESET, ENABLE,
output reg [3:0] D,
output reg [1:0] MODO
);
`include "./testers/driver.v"
`include "./s... | 6.782347 |
module VGA_sync (
input clk,
input rst,
output HS,
output VS,
output [3:0] red,
output [3:0] green,
output [3:0] blue
);
//VGA timing parameters for 640 x 480
localparam h_val_upperlim = 784;
localparam h_val_lowerlim = 143;
localparam v_val_upperlim = 515;
localparam v_val_lowerl... | 9.278993 |
module counters_wrapper_subm (
input clk,
input rst, (* mark_debug = "true", keep = "true" *)
input en, (* mark_debug = "true", keep = "true" *)
output A, (* mark_debug = "true", keep = "true" *)
output B
);
//switched inputs a_val and b_val to wires so I can view them on testbench
(* mark_d... | 6.877122 |
module counters_wrapper_tb ();
reg clk = 0;
reg rst = 0;
reg en = 0;
wire A;
wire B;
wire [9:0] a_val;
wire [9:0] b_val;
counters_wrapper_subm uut (
.clk(clk),
.rst(rst),
.en(en),
.A(A),
.B(B),
.a_val_out(a_val),
.b_val_out(b_val)
);
always #5 clk = ~cl... | 6.877122 |
module: counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module countert;
// Inputs
reg mainClock;
reg reset;
// Outputs
wire [3:0] count;
parameter DELY = 20;
// Instant... | 7.040838 |
module counter_testbench ();
reg clk, reset;
wire [3:0] counter1, counter2;
up_counter up (
clk,
reset,
counter1
);
down_counter down (
clk,
reset,
counter2
);
initial begin
$dumpfile("Counter.vcd");
$dumpvars(0, counter_testbench);
end
initial begin
c... | 6.694606 |
module tb ();
reg clk, rst;
wire [3:0] count;
counter c1 (
clk,
rst,
count
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst = 0;
#5 rst = 1;
#10 rst = 0;
#200 $finish;
end
initial $monitor("%d%d", clk, count);
initial begin
$dumpfil... | 7.002324 |
module counterTestGen (
clk,
reset,
enable,
count
);
input clk;
output reset, enable;
input [3:0] count;
wire clk;
reg reset, enable;
wire [3:0] count;
initial $counterTestGen(clk, reset, enable, count);
endmodule
| 7.314768 |
module CounterTop (
input CLK,
input IN,
output [19:0] bnum
);
wire [19:0] on_count;
wire [19:0] off_count;
wire [19:0] sum;
wire [19:0] period;
FrequencyCounter u1 (
.CLK(CLK),
.IN(IN),
.on_count(on_count),
.off_count(off_count)
);
SumFrequency u2 (
.on_count... | 7.084952 |
module CounterTopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input Clock,
input Reset,
output AggregatorBank1,
output LED1,
output LED2,
output LED3,
output LED4
);
wire [31:0] counter;
assign AggregatorBank1 = 1'b1;
assign LED1 = counter[18];
assign LED2 = counter[... | 6.789317 |
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