code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module counterup10_1clk_async_resetp (
clk,
reset,
count
);
input clk, reset;
output [9:0] count;
reg [9:0] count;
initial begin
count <= 0;
end
always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else count <= count + 1;
end
endmodule
| 6.797083 |
module counterup12_1clk_async_resetp (
clk,
reset,
count
);
input clk, reset;
output [11:0] count;
reg [11:0] count;
initial begin
count <= 0;
end
always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else count <= count + 1;
end
endmodule
| 6.913276 |
module counterup16 (
clk,
reset,
count
);
input clk, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 0;
end
always @(posedge clk or negedge reset) begin
if (reset == 1'b0) count <= 16'h0;
else count <= count + 1;
end
endmodule
| 6.695807 |
module counterup16_1clk_async_resetp (
clk,
reset,
count
);
input clk, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 0;
end
always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else count <= count + 1;
end
endmodule
| 6.64585 |
module counterup16_1clk_negedge_async_resetn (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
always @(negedge clock0 or negedge reset) begin
if (reset == 1'b0) begin
count <= 0;
end else begin
count <= count + 1;
end
end
endmodule
... | 6.64585 |
module counterup16_1clk_negedge_async_resetp (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
always @(negedge clock0 or posedge reset) begin
if (reset == 1'b1) begin
count <= 0;
end else begin
count <= count + 1;
end
end
endmodule
... | 6.64585 |
module counterup16_1clk_negedge_sync_resetn (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 0;
end
always @(negedge clock0) begin
if (reset == 1'b0) begin
count <= 0;
end else begin
count <= count + 1;
en... | 6.64585 |
module counterup16_1clk_negedge_sync_resetp (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 0;
end
always @(negedge clock0) begin
if (reset == 1'b1) begin
count <= 0;
end else begin
count <= count + 1;
en... | 6.64585 |
module counterup16_1clk_posedge_async_resetn (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 0;
end
always @(posedge clock0 or negedge reset) begin
if (reset == 1'b0) begin
count <= 0;
end else begin
count <=... | 6.64585 |
module counterup16_1clk_posedge_async_resetp (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 0;
end
always @(posedge clock0 or posedge reset) begin
if (reset == 1'b1) begin
count <= 0;
end else begin
count <=... | 6.64585 |
module counterup16_1clk_posedge_sync_resetn (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 0;
end
always @(posedge clock0) begin
if (reset == 1'b0) begin
count <= 0;
end else begin
count <= count + 1;
en... | 6.64585 |
module counterup16_1clk_posedge_sync_resetp (
clock0,
reset,
count
);
input clock0, reset;
output [15:0] count;
reg [15:0] count;
initial begin
count <= 0;
end
always @(posedge clock0) begin
if (reset == 1'b1) begin
count <= 0;
end else begin
count <= count + 1;
en... | 6.64585 |
module counterup16_4clk_posedge_async_resetn (
clock0,
clock1,
clock2,
clock3,
reset,
cnt0_16,
cnt1_16,
cnt2_16,
cnt3_16
);
input clock0, clock1, clock2, clock3;
input reset;
output [15:0] cnt0_16;
output [15:0] cnt1_16;
output [15:0] cnt2_16;
output [15:0] cnt3_16;
co... | 6.904577 |
module counterup16_7clk_posedge_async_resetn (
clock0,
clock1,
clock2,
clock3,
clock4,
clock5,
clock6,
reset,
cnt0_16,
cnt1_16,
cnt2_16,
cnt3_16,
cnt4_16,
cnt5_16,
cnt6_16
);
input clock0, clock1, clock2, clock3, clock4, clock5, clock6;
input reset;
outp... | 6.964797 |
module counterup16_8clk_posedge_async_resetn (
clock0,
clock1,
clock2,
clock3,
clock4,
clock5,
clock6,
clock7,
reset,
cnt0_16,
cnt1_16,
cnt2_16,
cnt3_16,
cnt4_16,
cnt5_16,
cnt6_16,
cnt7_16
);
input clock0, clock1, clock2, clock3, clock4, clock5, cloc... | 7.011539 |
module counterup36_8_2clk_async_resetp (
clock0,
reset,
out1,
out2
);
parameter N = 36;
parameter size = 77;
input clock0;
input reset;
output [(size*N)-1:0] out1;
wire [N-1:0] count_w;
output [9:0] out2;
cluster_counters a0 (
clock0,
reset,
count_w
);
counterup10... | 7.167888 |
module cluster_counters (
clock0,
reset,
out
);
input clock0;
input reset;
output [35:0] out;
counterup8_1clk_async_resetp ins0 (
.clk (clock0),
.reset(reset),
.count(out[7:0])
);
counterup12_1clk_async_resetp ins1 (
.clk (clock0),
.reset(reset),
.count(out... | 6.724969 |
module counterup8_1clk_async_resetp (
clk,
reset,
count
);
input clk, reset;
output [7:0] count;
reg [7:0] count;
initial begin
count <= 0;
end
always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else count <= count + 1;
end
endmodule
| 6.939701 |
module counterUpDown4bits (
input clk,
input UD,
output reg [3:0] Count,
input Clear
);
always @(Clear) if (Clear == 0) Count = 4'b0000;
always @(negedge clk)
case ({
UD, Clear
})
2'b01: Count = Count + 1;
2'b11: Count = Count - 1;
endcase
endmodule
| 7.432371 |
module counterupn_1clk_dualedge_async_resetp (
clk,
q_counter,
rst_counter
);
parameter n = 12;
input clk;
input rst_counter;
output [n-1:0] q_counter;
reg [n-1:0] q_counter1, q_counter2;
always @(posedge clk or posedge rst_counter) begin
if (rst_counter) q_counter1 <= 0;
else q_counte... | 7.549298 |
module counterUp_32bit ( //counter_up( clk, counterPeriod, countedUpTo )
input clock,
reset,
input [31:0] counterPeriod,
output [31:0] countedUpTo
);
reg [31:0] countedUpTo_reg;
// initial begin
// countedUpTo_reg <= 0;
// end
initial countedUpTo_reg <= 0;
// always@(posedg... | 8.406881 |
module CounterUp_TestBench ();
reg clock = 0;
reg reset = 0;
reg [27:0] counterPeriod = 0;
wire [27:0] countedUpTo;
parameter [27:0] PERIOD = 28'd1000000; //1,000,000 for 100 Hz; 1000 FOR 100 Khz
parameter [27:0] HALF_PERIOD = PERIOD >> 1;
parameter [27:0] QUARTER_PERIOD = PERIOD >> 2;
parameter [27... | 6.501703 |
module: counterrr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module counterx;
// Inputs
reg clk;
reg reset;
// Outputs
wire [31:0] out;
// Instantiate the Unit Under Test (UUT... | 7.378668 |
module counter_0to7_nonRecycling (
output reg out,
input clear,
clk
);
reg [2:0] counter;
always @(posedge clk) begin
// checa se clear é 1, se for limpa o contador e zera out
if (clear == 1) begin
counter <= 0;
out <= 0;
end else begin
// se o contador for menor que 7, in... | 6.82615 |
module counter_10 (
clock,
enable,
reset,
count
);
parameter BIT_SZ = 10;
input clock;
input enable;
input reset;
output [BIT_SZ-1:0] count;
reg [BIT_SZ-1:0] count;
initial count = 0;
always @(posedge clock) begin
if (enable == 1'b1) count <= count + 1'b1;
else if (reset == 1... | 7.079423 |
module counter_12 (
input clk,
input rst,
output reg [0:0] value
);
localparam SIZE = 1'h1;
localparam DIV = 2'h2;
localparam TOP = 1'h0;
localparam UP = 1'h1;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 3'h3;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ctr_q[2+0... | 6.540474 |
module counter_14 (
input clk,
input rst,
output reg [0:0] value
);
localparam SIZE = 1'h1;
localparam DIV = 5'h1a;
localparam TOP = 1'h0;
localparam UP = 1'h1;
reg [26:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 27'h3ffffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_... | 6.573208 |
module counter_14_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 14) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.798894 |
module counter_16 (
clock,
enable,
reset,
count
);
parameter BIT_SZ = 16;
input clock;
input enable;
input reset;
output [BIT_SZ-1:0] count;
reg [BIT_SZ-1:0] count;
initial count = 0;
always @(posedge clock) begin
if (enable == 1'b1) count <= count + 1'b1;
else if (reset == 1... | 6.881585 |
module counter_16b (
clk,
reset,
ena,
modulus,
count
);
input clk;
input reset;
input ena;
input [15:0] modulus;
output reg [15:0] count;
always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else if (ena)
if (count == modulus) begin
count <= 0;
... | 6.960613 |
module counter_16bit (
En,
Clk,
Clr,
Q
);
input En, Clk, Clr;
output [15:0] Q;
wire [15:0] T, Qs;
t_flipflop T0 (
En,
Clk,
Clr,
Qs[0]
);
assign T[0] = En & Qs[0];
t_flipflop T1 (
T[0],
Clk,
Clr,
Qs[1]
);
assign T[1] = T[0] & Qs[1];
... | 6.674368 |
module counter_16_bits (
input [1:0] SW,
input [0:0] KEY,
output [0:6] HEX0,
HEX1,
HEX2,
HEX3
);
wire [15:0] number;
counter counter0 (
KEY[0],
SW[0],
SW[1],
number
);
integer zmienna1, zmienna2, zmienna3, zmienna4;
always @(*) begin
zmienna1 = number % 16... | 6.720681 |
module counter_16_bits_board (
input KEY0,
input [1:0] SW,
output [6:0] HEX0,
HEX1,
HEX2,
HEX3
);
wire [15:0] counter_value;
counter_N_bits #(16) counter (
KEY0,
SW[0],
SW[1],
counter_value
);
decoder_hex_16(
counter_value % 16, HEX0
); decoder_hex_16(
... | 6.720681 |
module counter_17 (
input clk,
input rst,
output reg [1:0] value
);
localparam SIZE = 2'h2;
localparam DIV = 5'h10;
localparam TOP = 4'h3;
localparam UP = 1'h1;
reg [17:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 20'h3ffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.739877 |
module counter_18 (
input clk,
input rst,
output reg [1:0] value
);
localparam SIZE = 2'h2;
localparam DIV = 5'h10;
localparam TOP = 4'h3;
localparam UP = 1'h1;
reg [17:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 20'h3ffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.612631 |
module counter_19 (
input clk,
input rst,
output reg [1:0] value
);
localparam SIZE = 2'h2;
localparam DIV = 5'h10;
localparam TOP = 4'h3;
localparam UP = 1'h1;
reg [17:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 20'h3ffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.807282 |
module counter_1bit (
input clk,
reset,
increment,
output count
);
reg current = 0;
reg prev = 0;
always @(posedge clk) begin
if (reset) current <= 0;
else if (increment & ~prev) current <= ~current;
else current <= current;
prev <= increment;
end
assign count = current;
endm... | 6.536528 |
module counter_1s (
input wire clk,
input wire [31:0] freq,
output reg clk_1s
);
reg [31:0] cnt;
initial begin
cnt[31:0] <= 0;
clk_1s <= 0;
end
always @(posedge clk) begin
if (cnt < freq) begin
cnt <= cnt + 1;
end else begin
cnt <= 0;
clk_1s <= ~clk_1s;
end
en... | 6.619683 |
module counter_1bit (
input clk,
reset,
increment,
output count
);
reg current = 0;
always @(posedge clk) begin
if (reset) current <= 0;
else if (increment) current <= ~current;
else current <= current;
end
assign count = current;
endmodule
| 6.536528 |
module Counter_1_tb (
output wire done,
error
);
Counter_base_tb #(
.FILE_SOURCE ("../testbench/data/peripheral/counter/Counter_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/peripheral/counter/Counter_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 6.784019 |
module counter_2 (
input clk,
input rst,
output reg [0:0] value
);
localparam SIZE = 1'h1;
localparam DIV = 4'h8;
localparam TOP = 1'h0;
localparam UP = 1'h1;
reg [8:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 9'h0ff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ctr_q[8+... | 6.703607 |
module counter_20 (
input clk,
input rst,
output reg [1:0] value
);
localparam SIZE = 2'h2;
localparam DIV = 5'h10;
localparam TOP = 4'h3;
localparam UP = 1'h1;
reg [17:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 20'h3ffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.747681 |
module counter_200 (
input clk_in, // 200Hz
input pause_n, // 按住暂停
output reg [7:0] duty_cycle = 'd0
); // 输出占空比的数值
// 功能：在每第 0 ~ 1 秒，生成 0 ~ 199 递增的数值，在每第 1 ~ 2 秒，生成 200 ~ 1 递减的数值
reg dir = 'd0; // 0 为递增，1 为递减
always @(posedge clk_in) begin
if (pause_n... | 6.710169 |
module counter_200_tb ();
// 输入
reg clk_in;
reg pause_n;
// 输出
wire [7:0] duty_cycle;
// 例化待测模块
counter_200 uut_counter (
.clk_in(clk_in),
.pause_n(pause_n),
.duty_cycle(duty_cycle)
);
// 描述输入信号
initial begin
clk_in = 0;
pause_n = 1;
repeat (1000) #2.5
... | 7.003709 |
module counter_20_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 20) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.020974 |
module counter_21 (
input clk,
input rst,
output reg [1:0] value
);
localparam SIZE = 2'h2;
localparam DIV = 5'h10;
localparam TOP = 4'h3;
localparam UP = 1'h1;
reg [17:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 20'h3ffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.655415 |
module counter_23 (
input clk,
input rst,
output reg [2:0] value
);
localparam SIZE = 2'h3;
localparam DIV = 5'h10;
localparam TOP = 4'hf;
localparam UP = 1'h1;
reg [18:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 20'hfffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.589866 |
module counter_25 (
input clk,
input rst,
output reg [1:0] value
);
localparam SIZE = 2'h2;
localparam DIV = 5'h10;
localparam TOP = 4'h3;
localparam UP = 1'h1;
reg [17:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 20'h3ffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.514424 |
module counter_2bit #(
parameter DATA_WID = 2
) (
clk_in,
cnt_out
);
input clk_in;
output reg [DATA_WID-1:0] cnt_out;
always @(posedge clk_in) begin
cnt_out <= cnt_out + 1'b1;
end
endmodule
| 7.607481 |
module counter_30_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 30) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.816296 |
module counter_31 (
input clk,
input rst,
output reg [0:0] value
);
localparam SIZE = 1'h1;
localparam DIV = 5'h19;
localparam TOP = 1'h0;
localparam UP = 1'h1;
reg [25:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 26'h1ffffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_... | 6.622973 |
module counter_31_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 31) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.103667 |
module counter_31_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 31) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
... | 7.08126 |
module counter_31_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 31) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
... | 7.299146 |
module counter_32 (
clk,
out,
halt,
RST
);
input clk, halt, RST;
output reg [31:0] out;
initial out = 0;
always @(posedge clk) begin
if (RST) out <= 0;
else if (out < 32'hffffffff) begin
if (~halt) out <= out + 1'b1;
end else begin
out <= 0;
end
end
endmodule
| 7.282286 |
module top (
count,
clk,
enable,
set,
comb_out
);
parameter Width = 32;
input clk, enable, set; //, reset;
output [Width-1:0] count;
output comb_out;
reg [Width-1:0] count;
always @(posedge clk or posedge set)
if (set) count <= 32'hFFFFFFFF;
else if (enable) count <= count + 1;
... | 6.942486 |
module counter_34 (
input clk,
input rst,
output reg [1:0] value
);
localparam SIZE = 2'h2;
localparam DIV = 5'h10;
localparam TOP = 4'h3;
localparam UP = 1'h1;
reg [17:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 20'h3ffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.57998 |
module COUNTER_3BIT (
clear,
clock,
q
);
input clear, clock;
output [2:0] q;
reg [2:0] q;
initial q = 3'b0;
wire in1, in3;
wire [2:0] out;
assign in1 = 1'b1;
and (in3, out[1], out[0]);
TFF ff1 (
out[0],
in1,
clock,
clear
);
TFF ff2 (
out[1],
out[... | 6.61054 |
module Counter_x (
input clk,
input rst,
input clk0,
input clk1,
input clk2,
input counter_we,
input [31:0] counter_val,
input [1:0] counter_ch,
output counter0_OUT,
output counter1_OUT,
output counter2_OUT,
output [31:0] counter_out
);
endmodule
| 6.554661 |
module Counter_x (
input clk,
input rst,
input clk0,
input clk1,
input clk2,
input counter_we,
input [31:0] counter_val,
input [1:0] counter_ch, //Counter channel set
output counter0_OUT,
output counter1_OUT,
output counter2_OUT,
output [31:0] counter_out
);
reg [32:... | 6.554661 |
module counter_4 (
input clk,
input rst,
output reg [3:0] value
);
localparam SIZE = 3'h4;
localparam DIV = 4'ha;
localparam TOP = 1'h0;
localparam UP = 1'h1;
reg [13:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 11'h3ff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ctr_q[... | 6.562775 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.324518 |
module counter_4b (
input clk,
input sclr,
output [3:0] out,
output cout
);
// This module is a 4-bit counter with synchronous clear
// Instantiate register that will count
reg [4:0] count;
// Initialize the register
initial count = 5'b00000;
// Assign outputs
assign out = count[3:0];... | 6.615669 |
module counter_4bit_2clock (
clk0,
rst,
clk1,
q0,
q1
);
input clk0;
input rst;
output [3:0] q0;
reg [3:0] q0;
input clk1;
output [3:0] q1;
reg [3:0] q1;
initial begin
q0 <= 0;
q1 <= 0;
end
always @(posedge clk0) begin
if (rst) q0 <= 4'b0000;
else q0 <= q0 + 1;... | 6.757432 |
module counter_4bit_2clock_tb;
reg clk0, rst0;
wire [3:0] q0;
reg clk1, rst1;
wire [3:0] q1;
counter_4bit_2clock C_1 (
clk0,
q0,
rst0
);
counter_4bit_2clock C_1 (
clk1,
q1,
rst1
);
initial begin
#0 rst0 = 1'b1;
clk0 = 1'b0;
#100 rst0 = 1'b0;
end
... | 6.757432 |
module counter_4_1hz (
output [3:0] b,
input clk,
input rst_n
);
wire clk_out;
freq_div_1hz U0 (
clk_out
,,
clk,
rst_n
);
counter_4 U1 (
b,
clk_out,
rst_n
);
endmodule
| 6.660768 |
module counter_5 (
input clk,
input rst,
output reg [0:0] value
);
localparam SIZE = 1'h1;
localparam DIV = 5'h16;
localparam TOP = 1'h0;
localparam UP = 1'h1;
reg [22:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 23'h3fffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.894743 |
module counter_5b (
input clk,
input sclr,
output [4:0] out,
output cout
);
// This module is a 5-bit counter with synchronous clear
// Instantiate register that will count
reg [5:0] count;
// Initialize the register
initial count = 6'b000000;
// Assign outputs
assign out = count[4:0]... | 6.581074 |
module counter_5bit (
reset,
clock,
current_state
);
input wire clock, reset;
output wire [4:0] current_state;
reg [4:0] state;
assign current_state = state;
//asynchronous reset
always @(posedge clock, posedge reset) begin
if (reset) begin
state = 0;
end else begin
state... | 7.026993 |
module counter_5bit (
clk,
reset,
count_en,
count
);
input clk, reset, count_en;
output reg [4:0] count;
always @(posedge clk or negedge reset) begin
if (~reset) count <= 0;
else if (count_en) count <= count + 1'b1;
end
endmodule
| 7.026993 |
module counter_tb ();
reg clk, rst;
wire [4:0] state;
counter_5bit c1 (
.reset(rst),
.clock(clk),
.current_state(state)
);
initial begin
rst = 0;
clk = 0;
#5 rst = 1;
#20 rst = 0;
#40 rst = 1;
#10 rst = 0;
#70 rst = 1;
end
always begin
#5 clk = ~clk;
... | 7.107233 |
module for a counter starting
//from 5 to 67 and counter disables
//once it reaches 67.
module counter_5to67 (output reg [7:0] count,
input wire clk
);
initial count= 8'd5;
always @(posedge clk) begin: counter
forever @(posedge clk) begin
if(count== 8'd67) begin
... | 6.745491 |
module counter_5to67_tb ();
wire [7:0] count;
reg clk;
counter_5to67 c1 (
count,
clk
);
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
$dumpfile("counter_5to67_tb.vcd");
$dumpvars(0, counter_5to67_tb);
#1000 $finish;
end
endmodule
| 6.706697 |
module Counter_5_3 (
input wire x0,
input wire x1,
input wire x2,
input wire x3,
input wire cin,
output wire cout,
output wire carry,
output wire sum
);
// assign cout = (x3&x2)|(x2&x1)|(x3&x1);
assign cout = ((x0 ^ x1) & x2) | (~(x0 ^ x1) & x0);
assign sum = x3 ^ x2 ^ x1 ... | 7.292028 |
module counter_5_bit (
clock,
cnt_en,
sclr,
q
);
input clock;
input cnt_en;
input sclr;
output [4:0] q;
wire [4:0] sub_wire0;
wire [4:0] q = sub_wire0[4:0];
lpm_counter LPM_COUNTER_component (
.clock(clock),
.cnt_en(cnt_en),
.sclr(sclr),
.q(sub_wire0),
.acl... | 6.967896 |
module counter_6 (
input clk,
input rst,
output reg [0:0] value
);
localparam SIZE = 1'h1;
localparam DIV = 5'h15;
localparam TOP = 1'h0;
localparam UP = 1'h1;
reg [21:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 22'h1fffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ct... | 6.768667 |
module counter_60 (
input rst_n,
input clk,
input load,
input set,
input [1:0] set_id,
input [3:0] set_num,
input signal,
output reg [3:0] ones,
output reg [2:0] tens,
output reg loop
);
/*
当set信号到来，必须停止计时：
置位的判别方法：判断set_id: tens -> 2'b10; ones -... | 6.958851 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module counter_63_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 63) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
... | 7.360162 |
module counter_63_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 63) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
... | 7.231427 |
module Counter_64 (
input clk,
input start,
input reset,
output reg [6:0] count1,
output reg [6:0] count2,
output reg done
);
parameter mod = 64;
always @(posedge clk) begin
if (reset || ~start) begin
count1 <= 0;
count2 <= 0;
done <= 0;
end else if (start) begi... | 6.955713 |
module counter_6bit (
output reg [5:0] Q_OUT,
input [5:0] load,
input parallel,
input increase,
input decrease,
input CLK,
input CLR
);
initial begin
Q_OUT = 6'b00_0000;
end
always @(posedge CLK) begin
if (increase == 1'b1 || decrease == 1'b1 || CLR == 1'b1 || parallel == 1'b1... | 6.717341 |
module counter_7_seg(
input CLK,
input switch_up,
input switch_clear,
output [7:0] SEG,
output [3:0] DIGIT
);
wire s_up, s_clear;
debouncer d1(.CLK (CLK), .switch_input (switch_up), .trans_dn (s_up));
debouncer d2(.CLK (CLK), .switch_input (switch_clear), .trans_dn (s_clear));
reg [3:0] units,... | 6.70527 |
module counter_8 (
clock,
enable,
count
);
parameter BIT_SZ = 8;
input clock;
input enable;
output [BIT_SZ-1:0] count;
reg [BIT_SZ-1:0] count;
initial count = 0;
always @(posedge clock) if (enable == 1'b1) count <= count + 1'b1;
endmodule
| 7.065173 |
module counter_8b (
input counter_clk, // defining all the inputs and outputs.
input reset,
output [7:0] count
);
reg [7:0] count_reg = 8'b00000000;
reg [7:0] count_next; // we don't initialize next variable as it is the output of the combinational bolck
always @(posedge counter_clk) // sequentia... | 6.717018 |
module counter_8bit (
LED,
CLK_200KHz,
CLK_50MHz,
Res
);
output reg [7:0] LED = 8'd255;
output reg CLK_200KHz;
input CLK_50MHz, Res;
reg [7:0] count = 8'd0;
// 50MHz --> 200KHz
always @(posedge CLK_50MHz) begin
if (count < 8'd125) count = count + 1;
else begin
CLK_200KHz = ~C... | 7.471104 |
module counter_8_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 8) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
en... | 6.902674 |
module counter_9 (
input clk,
input rst,
output reg [1:0] value
);
localparam SIZE = 2'h2;
localparam DIV = 5'h1a;
localparam TOP = 2'h3;
localparam UP = 1'h1;
reg [27:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 28'hfffffff;
always @* begin
M_ctr_d = M_ctr_q;
value = M_c... | 6.652343 |
module counter_99 (
count,
clk,
reset
);
input clk;
input reset;
//This implementation assumes that the counter resets on active low
output reg [7:0] count;
initial begin
//start counter with 0;
count <= 8'b00_00_00_00;
end
always @(posedge clk, negedge reset) begin
if (~reset) beg... | 7.047737 |
module counter (clk, reset, preset, type, DN, CU, CD, ACC);
input clk, reset;
input [`tcPresetLen-1:0] preset;
input [`tcTypeLen-1:0] type;
output DN, CU, CD;
output [`tcAccLen-1:0] ACC;
reg DN = 0, CU = 0, CD = 0;
reg [`tcAccLen-1:0] ACC = 0;
reg [`tcTypeLen-1:0] CounterType;
reg [`tcTypeLen-1:0] typeN... | 6.850043 |
module counter_amb (
input clk,
input up,
input cross_amb,
output count
);
reg cuenta;
assign count = cuenta;
always @(posedge clk) begin
if ((cuenta < 1) && up) cuenta = cuenta + 1;
else if (cross_amb && (cuenta > 0)) cuenta = cuenta - 1;
end
endmodule
| 7.902528 |
module counter_ar (
clk,
rst,
en,
count
);
parameter n = 3;
input clk, rst, en;
output [n-1:0] count;
wire [n-1:0] next_count, count;
dffar #(n) count_reg (
.clk(clk),
.r (rst),
.en (en),
.d (next_count),
.q (count)
);
assign next_count = rst ? {n{1'b0... | 7.738875 |
module counter_asyn #(
parameter N = 4
) (
output reg [N-1:0] count,
input clk,
rst_n
);
always @(posedge clk, posedge rst_n) begin
if (~rst_n) count <= 0;
else count <= count + 1;
end
endmodule
| 7.317138 |
module counter_add3 (
clk,
rstn, // It is negative reset
out
);
output reg [2:0] out = 3'b000;
input clk;
input rstn;
// This always block will be triggered at the falling edge of clk (0->1)
// Once inside this block, it checks if the reset is 0, if yes then change out to zero
// If reset is ... | 7.824485 |
module counter_auto (
input clr_n,
input stop_n,
input clk,
output reg [2:0] counter
);
reg flag;
always @(posedge clk or negedge clr_n) begin
if (clr_n == 1'b0) flag <= 1'b1;
else if (counter == 'd6) flag <= 1'b0;
else if (counter == 'd1) flag <= 1'b1;
end
//counter
always @(pos... | 7.431878 |
module counter_b (
clk,
rst,
mode,
cs,
a,
b,
c,
d,
e,
f,
g,
dp
);
output a, b, c, d, e, f, g, dp;
output cs;
input clk, rst;
input mode;
wire cs;
wire a, b, c, d, e, f, g, dp;
reg [3:0] count;
reg clk_reg;
reg [31:0] clk_cnt;
initial begin
clk_cn... | 6.549586 |
module Counter_base_tb #(
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam ADDR_WIDTH = 8;
localparam DATA_WIDTH = 8;
localparam TIME_WIDTH = 8;
reg clk = 0, reset = 1;
initial #11 reset = 0;
always #2.5 clk <= ~clk;
wire [DATA_WIDTH-1:... | 7.320731 |
module decoder_hex_10 (
input [3:0] SW,
output reg [0:6] HEX,
output reg E
);
always @(*)
if (SW > 4'b1001) begin
E = 1;
end else begin
E = 0;
casex (SW)
4'd0: HEX = 7'b0000001;
4'd1: HEX = 7'b1001111;
4'd2: HEX = 7'b0010010;
4'd3: HEX = 7'b0000110... | 7.325232 |
module counter_mod_M #(
parameter M = 10
) (
input clk,
aclr,
enable,
output reg [N-1:0] Q
);
localparam N = clogb2(M - 1);
function integer clogb2(input [31:0] v);
for (clogb2 = 0; v > 0; clogb2 = clogb2 + 1) v = v >> 1;
endfunction
always @(posedge clk, negedge aclr)
if (!aclr) ... | 7.524421 |
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