code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module counter_modulo_k #(
parameter M = 20
) (
input clk,
aclr,
enable,
output reg [N-1:0] Q,
output reg rollover
);
localparam N = clogb2(M - 1);
function integer clogb2(input [31:0] v);
for (clogb2 = 0; v > 0; clogb2 = clogb2 + 1) v = v >> 1;
endfunction
always @(posedge clk, ne... | 6.951862 |
module counter_BCD_3_digits (
input CLOCK_50,
input [1:0] KEY,
output [0:6] HEX0,
HEX1,
HEX2,
output [1:0] LEDR
);
wire c0, c1, c2;
wire [3:0] h0, h1, h2;
delay_1_sec del (
CLOCK_50,
c0
);
counter_modulo_k #(10) count0 (
c0,
KEY[0],
1'b1,
h0,
... | 8.09504 |
module counter_BCD_3_digits_board (
input CLOCK_50,
KEY0,
output [6:0] HEX0,
HEX1,
HEX2,
output LEDR0
);
counter_BCD_3_digits(
CLOCK_50, 1'b1, KEY0, HEX0, HEX1, HEX2, LEDR0
);
endmodule
| 8.09504 |
module counter_bidir #(
parameter LENGTH = 8
) (
input clk,
input enable,
input rst,
input up_down,
output [LENGTH-1:0] out
);
reg [LENGTH-1:0] ctr_d, ctr_q;
assign out = ctr_q;
always @(*) begin
if (up_down) begin
ctr_d = ctr_q + 1'b1;
end else begin
ctr_d = ctr_q - ... | 6.529996 |
module counter_block (
reset,
clk,
enable,
count
);
input reset, clk;
input enable;
parameter COUNT_LEN = 13;
output reg [COUNT_LEN-1:0] count;
always @(posedge clk or posedge reset) begin
if (reset) begin
count = 0;
end else if (enable) begin
count = count + 1;
end ... | 6.536741 |
module counter_bus_mux (
data0x,
data1x,
sel,
result
);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
wire [3:0] sub_wire5;
wire [3:0] sub_wire2 = data1x[3:0];
wire [3:0] sub_wire0 = data0x[3:0];
wire [7:0] sub_wire1 = {sub_wire2, sub_wire0};
wire sub_wire3 ... | 7.106033 |
module counter_bus_mux (
data0x,
data1x,
sel,
result
);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
endmodule
| 7.106033 |
module Counter_Cell (
input iClk,
input iRst_n,
input iEn,
output [6:0] oOut
);
reg [6:0] counter;
reg [7:0] temp;
always @(posedge iClk) begin
if (iEn) begin
if (!iRst_n) begin
temp <= 8'd0;
counter <= 7'd0;
end else begin
counter <= counter + 1'b1;
... | 7.11641 |
module
*/
//////////////////////////////////////////////////////////////////////////////////
module counter_clk_div(clk,rst,counter_out);
input clk,rst;
reg div_clk;
reg [25:0] delay_count;
output reg [3:0] counter_out;
//////////clock division block////////////////////
always @(posedge clk)
begin
if(rst)
begi... | 6.981371 |
module
*/
//////////////////////////////////////////////////////////////////////////////////
module counter_clk_div(clk,rst,counter_out);
input clk,rst;
reg div_clk;
reg [25:0] delay_count;
output reg [3:0] counter_out;
//////////clock division block////////////////////
always @(posedge clk)
begin
if(rst)
begi... | 6.981371 |
module counter_clk_div (
clk
);
input clk;
wire rst;
reg div_clk;
reg [25:0] delay_count;
reg [3:0] counter_out;
//We will add a VIO here. So, convert all outputs to reg and all
//inputs to wires except clk
//VIO --- Design. VIO outputs will be connected to the counter input
//Counter outputs wi... | 7.365368 |
module counter_control (
output reg out, //STOP SIGNAL
output reg data_valid_out, //WRITE SIGNAL
output reg sel_line1,
output reg sel_line2,
input wire [15:0] width,
input wire [15:0] high,
input wire [31:0] frames,
input wire clk,
input wire rst,
input wire enable
);
reg [63... | 6.500478 |
module Counter_Controller #(
parameter DWIDTH = 7
) (
input clk,
input rst_n,
input start_i,
input [DWIDTH-1:0] cnt_val_i,
input [DWIDTH-1:0] cnt_i,
output run_o,
output done_o
);
localparam S_IDLE = 2'b00, S_RUN = ... | 7.811166 |
module counter_d #(
parameter W = 4
) (
input wire clk,
input wire rst,
input wire load,
input wire enable,
input wire [W-1:0] d,
output wire max_tick,
output wire min_tick,
output wire [W-1:0] q
);
reg [W-1:0] count;
always @(posedge clk, posedge rst) begin
if (rst) count <=... | 7.788815 |
module counter_datamux_syn (
i_clk_din,
i_rstn_din,
i_mux_sel,
i_inner_din_a,
i_inner_din_b,
i_clk_dout,
i_rstn_dout,
o_mux_dout
);
parameter COUNTER_NUM = 4;
input wire [COUNTER_NUM-1:0] i_clk_din;
input wire [COUNTER_NUM-1:0] i_rstn_din;
input wire [COUNTER_NUM-1:0] i_mux_sel;... | 7.117278 |
module counter_data_syn (
i_clk_din,
i_rstn_din,
i_din,
i_clk_dout,
i_rstn_dout,
o_syn_dout
);
//
input wire i_clk_din;
input wire i_rstn_din;
input wire i_din;
//
input wire i_clk_dout;
input wire i_rstn_dout;
output wire o_syn_dout;
reg r1_din_syn;
reg r1_... | 7.280192 |
module counter_data_syn_param (
i_clk_din,
i_rstn_din,
i_din,
i_clk_dout,
i_rstn_dout,
o_syn_dout
);
parameter BUS_WIDTH = 4;
//
input wire i_clk_din;
input wire i_rstn_din;
input wire [BUS_WIDTH-1:0] i_din;
//
input wire i_clk_dout;
input wire i_rstn_dout;
output wire ... | 7.280192 |
module is intended for use with the DE1_SoC and Spinal Tap.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
//Declaration of DE1_SoC inputs and outputs: LED as output,
//an active-low reset on Switch 0 and a 50 MHz clock
module counter_DE1(LEDR, CLOCK_50, SW);
//Decla... | 9.106975 |
module counter_Dec_bo (
input clk,
input en,
output isfull
);
reg [4:0] count;
always @(posedge clk) begin
count <= count + 1;
if (count == 22) count <= 0;
end
assign isfull = (count >= 5'b10110) ? 1 : 0;
endmodule
| 7.130446 |
module top (
input clk_p,
clk_n,
input rst,
output [7:4] io_led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
reg [31:0] counter = 32'b0;
assign io_led = counter[25:22];
always @(posedge clk) begin
if (rst) counter <= 32'b0;
else counter <= ... | 7.233807 |
module counter_disable_a (
reset,
clk,
enable,
count
);
input reset, clk;
input enable;
output reg [9:0] count;
always @(posedge clk or posedge reset) begin
if (reset) begin
count = 10'd0;
end else if (enable) begin
if (count == 0) count = 10'b1_1111_1111_1;
else cou... | 7.384415 |
module counter_disable_b (
reset,
clk,
enable,
count,
enable0
);
input reset, clk;
input enable;
input enable0;
output reg [9:0] count;
always @(posedge clk or posedge reset) begin
if (reset) begin
count = 10'd0;
end else if (enable) begin
if (enable0 == 0) count = 1... | 7.384415 |
module counter_div (
clk,
rst,
DEC,
z
);
input clk;
input rst;
input DEC;
output reg z;
reg [4:0] cont = 16;
always @(negedge clk) begin
if (rst) cont = 5'b10000; //16
else begin
if (DEC) cont = cont - 1;
else cont = cont;
end
z = (cont == 0) ? 1 : 0;
... | 6.902986 |
module counter_divide_by_100 (
input clk,
output reg newclk
);
reg [6:0] count = 7'b0000000;
always @(posedge clk) begin
count = count + 1;
newclk = count[5];
end
endmodule
| 6.558469 |
module counter_up_4_down_test;
wire [3:0] count_variable;
reg clk;
initial begin
clk = 1'b0;
forever begin
#5 clk = ~clk;
end
end
counter_down_4_bit wire_driver (
clk,
count_variable
);
initial begin
#200 $finish;
end
endmodule
| 6.805363 |
module counter_drp (
input reset,
input ref_clock,
input target_clock,
output [31:0] counter_value,
output done
);
reg [31:0] counter_ref;
reg [31:0] counter_target;
reg reg_done;
wire [31:0] tmp;
wire tmp2;
wire done_status;
alwa... | 6.788168 |
module counter1 (
input en,
input clk,
input reset,
output [2:0] count
);
reg [2:0] data;
always @(posedge clk) begin
if (reset == 1) data <= 0;
else begin
if (en == 1) data <= data + 1'b1;
end
end
assign count = data;
endmodule
| 6.94605 |
module counter_f (
Clk,
Rst,
Load_In,
Count_Enable,
Count_Load,
Count_Down,
Count_Out,
Carry_Out
);
parameter C_NUM_BITS = 9;
parameter C_FAMILY = "nofamily";
input Clk;
input Rst;
input [C_NUM_BITS - 1:0] Load_In;
input Count_Enable;
input Count_Load;
input Count_Down;
... | 7.397705 |
module counter_fixed_num (
CLK,
RST,
COUNT
);
parameter n = 32;
input CLK, RST;
output reg [n-1:0] COUNT;
always @(posedge CLK, negedge RST) begin
if (RST) COUNT <= 32'b0000000000000000_0000000000000000;
else COUNT <= COUNT + 32'b0000000000000001_0000000000000000;
end
endmodule
| 7.853239 |
module counter_for73 (
CEP,
CET,
PE1,
PE2,
CLK,
D1,
D2,
TC1,
TC2,
Q1,
Q2,
CR
); //, CR1, CR2);
parameter N = 4;
parameter M = 16;
input CEP, CET, PE1, PE2, CLK, CR;//, CR1, CR2; //控制信号输入(功能选择、PE=0同步置位、时钟、清零)
input [N-1:0] D1, D2; // 并行数据输入
output TC1, TC2; //... | 7.578492 |
module counter_tb ();
reg clock, rst;
reg d_en;
wire rdy;
wire [11:0] d_out;
initial begin
$display($time, " << Starting the Simulation >>");
d_en = 1'b0;
wait (rdy == 1'b1) begin
d_en = 1'b0;
end
#10 d_en = 1'b1;
#164000 $display($time, " << Simulation Complete >>");
$... | 7.107233 |
module counter_fre (
clk_05,
cin,
cout,
data,
Rst_n
);
input clk_05; //ʱ2Hz
input cin; //ź
input Rst_n; //λ
output reg cout; //ж
output reg [23:0] data; //6λ,BCD
wire out;
wire [23:0] num;
wire cout_1, cout_2, cout_3, cout_4, cout_5;
counter(
.clk(clk_05), .cin(cin), ... | 6.58414 |
module counter_fucker (
SW,
CLOCK_50,
HEX0
);
input CLOCK_50;
input [9:0] SW;
output [6:0] HEX0;
wire [3:0] wtohex;
CLOCK_counter c0 (
SW[2],
SW[1:0],
CLOCK_50,
SW[9],
wtohex
);
hex_display h0 (
wtohex,
HEX0
);
endmodule
| 6.775445 |
module CLOCK_counter (
enable,
select,
clk,
reset_n,
out
);
input enable, clk, reset_n;
input [1:0] select;
output [3:0] out;
wire w0;
wire w1;
wire w2;
always @(*) begin
case (select)
2'b00: out = enable;
2'b01: out = (w0 == 0) ? 1 : 0;
2'b10: out = (w1 =... | 7.369185 |
module rate_divider (
enable,
load,
clk,
reset_n,
q
);
input enable, clk, reset_n;
input [27:0] load;
output reg [27:0] q;
always @(posedge clk) begin
if (reset_n == 1'b0) q <= load;
else if (enable == 1'b1) begin
if (q == 0) q <= load;
else q <= q - 1'b1;
end
end
... | 7.346866 |
module for s1
module s1(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = ~c3 & c2 & ~c1 & c0 | c3 & c2 & ~c0 | c1 & c0 & c3 | c1 & ~c0 & c2;
endmodule
| 6.773514 |
module for s2
module s2(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = ~c3 & ~c2 & c1 & ~c0 | c3 & c2 & ~c0 | c3 & c2 & c1;
endmodule
| 6.735825 |
module for s3
module s3(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = ~c3 & c2 & ~c1 & ~c0 | c3 & ~c2 & c1 & ~c0 | ~c1 & c0 & ~c2 | c1 & c0 & c2;
endmodule
| 6.844572 |
module for s4
module s4(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = ~c3 & c0 | ~c3 & c2 & ~c1 | ~c1 & c0 & ~c2;
endmodule
| 7.72525 |
module for s5
module s5(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = c3 & c2 & ~c1 & c0 | c1 & c0 & ~c3 | ~c3 & ~c2 & c0 | ~c3 & ~c2 & c1;
endmodule
| 6.657867 |
module for s6
module s6(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = ~c3 & c2 & c1 & c0 | c3 & c2 & ~c1 & ~c0 | ~c3 & ~c2 & ~c1;
endmodule
| 6.590278 |
module counter_g #(
Add_W = 4
) (
input CLK,
RST,
input CE,
input SCLR,
output reg [Add_W-1:0] Q
);
always @(posedge CLK) begin
if (RST == 0) Q <= 0;
else if (SCLR == 1) Q <= 0;
else if (CE == 0) Q <= Q;
else if (CE == 1) Q <= Q + 1;
end
endmodule
| 6.922517 |
module counter_gen (
clk,
rst,
valid,
ready,
data
);
input clk;
input rst;
output reg valid;
input ready;
output reg [7:0] data;
always @(posedge clk)
if (rst) begin
valid <= 0;
data <= 0;
end else begin
valid <= 1;
if (ready) data <= data + 1;
end
... | 6.701181 |
module counter_gray (
input clk,
rst_n,
output [3:0] cnt
);
reg [3:0] bin_cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) bin_cnt <= 0;
else bin_cnt <= bin_cnt + 1;
end
assign cnt = bin_cnt ^ (bin_cnt >> 1);
endmodule
| 7.255389 |
module is intended for use with GTKwave on the PC.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
//Create a connection between the testbench and converted schematic .bdf file
`include "rippleDownCounter.v"
module counter_GTK;
// connect the two modules
wire clk, r... | 9.106975 |
module used to apply inputs to our counter
module Tester (clk, rst, out);
input [3:0] out;
output reg clk, rst;
parameter stimDelay = 20;
initial // Creates output in CMD
begin
$display("\t\t Reset \t Out[3] Out[2] Out[1] Out[0] \t Time ");
$monitor("\t\t %b\t %b \t %b \t %b", rst, out[3], out[2], out[1], ou... | 6.557475 |
module counter_h (
input clk,
input up,
input cross_h,
output [6:0] count
);
reg [6:0] cuenta;
assign count = cuenta;
always @(posedge clk) begin
if ((cuenta < 99) && up) cuenta = cuenta + 1;
else if (cross_h && (cuenta > 0)) cuenta = cuenta - 1;
end
endmodule
| 6.560038 |
module Counter_Half_Duplex #(
parameter BASE = 10,
parameter NUMBER_OF_BITS = 4,
parameter EXPOSE_NUMBER = 1
) (
input wire clk,
input wire rst,
input wire enable,
input wire up_down,
input wire set,
inout wire [(NUMBER_OF_BITS-1):0] number,
output wire threshold
);
wire [(NUM... | 6.512596 |
module Counter_tb ();
reg clk; // clock
reg rst; // reset
reg enable;
reg up_down;
reg set;
wire [3:0] number;
reg [3:0] set_number;
assign number = (set) ? set_number : 'bz;
Counter_Half_Duplex /*#(.EXPOSE_NUMBER(1))*/ dut (
.clk(clk),
.rst(rst),
.enable(enable),
.up_dow... | 6.630148 |
module Counter_Jhnson (
input iClk,
output [3:0] oSalida
);
reg [3:0] rCount_D;
reg [3:0] rCount_Q;
reg rPulso_D = 1'b0;
reg rPulso_Q;
assign oSalida = rCount_Q;
always @(posedge iClk) begin
rPulso_Q <= rPulso_D;
rCount_Q <= rCount_D;
end
always @* begin
rPulso_D = rPulso_Q + 1'... | 6.93848 |
module counter_john (
input clk,
rst_n,
output reg [3:0] cnt
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= 0;
else if (cnt[3]) cnt <= cnt << 1;
else cnt <= {cnt[2:0], 1'b1};
end
endmodule
| 7.683509 |
module d_flipflop (
d,
clk,
q,
set,
clear
); // Not using qbar over here, to simplify logic.
input d, clk, set, clear;
output reg q;
initial begin // Clearing the flipflop.
q <= 0;
end
always @(posedge clk) begin
if (set == 1'b1) begin
q <= 1;
end else if (clear == 1... | 7.276171 |
module counter_line
(
input clk,
input Reset,
input EN,
input CLR,
output reg[7:0] counter,
output OV
);
//Defination for Varables in the module
reg[7:0] old_counter;
//Stored counter for overflow judgement
wire error;
//Error signal to display
//Logicals
//Combanitory logicals
assign OV ... | 7.131696 |
module counter_loadable (CLK, //input assert posedge to increment/decrement counter
EN, //input enable signal (assert to allow counter to count)
RST, ... | 7.285747 |
module counter_loop (
input clk,
rst_n,
output reg [3:0] cnt
);
always @(posedge clk) begin
if (!rst_n) cnt <= 4'b0001;
else cnt <= {cnt[2:0], cnt[3]}; //循环左移，不能用移位操作符
end
endmodule
| 7.529419 |
module Counter_M24 (
input clk,
input rst_n,
input en,
input clr,
input di,
output reg [3:0] data_0,
output reg [3:0] data_1,
output reg co,
output reg d0
);
always @(posedge clk or negedge rst_n) begin
if (!rs... | 6.73886 |
module counter_mod10 (
clk,
reset,
count
);
input clk, reset;
output [3:0] count;
wire reset_comb;
reg [3:0] reg_count;
assign count = reg_count;
assign reset_comb = (reset & ((reg_count == 4'b1001) ? 1'b0 : 1'b1));
always @(posedge clk) begin
if (!reset_comb) reg_count <= 4'b0000;
... | 7.191868 |
module counter_mod100 (
clk,
en,
clr_n,
num1,
num0,
rco
);
input clk, en, clr_n;
output reg [3:0] num1;
output reg [3:0] num0;
output reg rco;
integer cnt;
initial begin
cnt = 0;
end
always @(posedge clk or negedge clr_n) begin
if (!clr_n) begin //异步清零
cnt <= 0;
... | 7.191868 |
module counter_mod10_TB ();
// entradas
reg [3:0] data_TB;
reg loadn_TB, clearn_TB, clock_TB, en_TB;
// saidas
wire [3:0] digit_TB;
wire zero_TB, tc_TB;
counter_mod10 seconds_ones (
// entradas
.loadn(loadn_TB),
.clearn(clearn_TB),
.clock(clock_TB),
.en(en_TB),
.data... | 7.191868 |
module counter_mod6 (
input wire [3:0] data, // entrada de dados doc ontador usada no loadn
input wire loadn, // sicrono, active low
input wire clearn, // assincrono, active low
input wire clock,
input wire en, // active high
output reg [3:0] digit, // saida do contador
output wire tc, ... | 7.068199 |
module counter_mod6_TB ();
// entradas
reg [3:0] data_TB;
reg loadn_TB, clearn_TB, clock_TB, en_TB;
// saidas
wire [3:0] digit_TB;
wire zero_TB, tc_TB;
counter_mod6 seconds_ones (
// entradas
.loadn(loadn_TB),
.clearn(clearn_TB),
.clock(clock_TB),
.en(en_TB),
.data(d... | 7.573505 |
module counter_mod8 (
cp,
qcc,
Q
);
input cp;
output qcc;
output [3:0] Q;
reg [3:0] A;
wire ld;
wire clk_N;
assign ld = (Q[3] & Q[0]) ? 0 : 1;
initial begin
A <= 4'b0010;
end
// 仿真时，注释掉25行并将counter1的cp输入改为cp
divider divider1 (
.clk (cp),
.clk_N(clk_N)
);
counter... | 6.886157 |
module counter_mod8_TB ();
reg clock_TB, clearn_TB;
wire F_TB;
counter_mod8 DUT (
.F(F_TB), // saidas
.clock(clock_TB),
.clearn(clearn_TB)
); // entradas
integer i;
// loop do clock
initial begin
$dumpfile("test/counter_mod8_TB.vcd");
$dumpvars(0, counter_mod8_TB);
for ... | 6.804464 |
module counter_modk (
clock,
reset_n,
Q
);
parameter n = 4;
parameter k = 16;
input clock, reset_n;
output [n-1:0] Q;
reg [n-1:0] Q;
always @(posedge clock or negedge reset_n) begin
if (~reset_n) Q <= 'd0;
else begin
Q <= Q + 1'b1;
if (Q == k - 1) Q <= 'd0;
end
end
en... | 7.274214 |
module counter_module_1us (
input clk,
input rst_n,
output _1us,
output _is1US,
output [4:0] c1
);
/********************/
//20MHz
parameter T1US = 5'd20; //大前提 而不是T1US = 5'd20;
/********************/
reg [4:0] count_1us;
reg is1US;
always @(posedge clk or negedge rst_n) begin
... | 6.951862 |
module counter_module_1us_3us (
input clk,
input rst_n,
output _1us,
output _is1US,
output [4:0] c1,
output _3us,
output _is3US,
output [5:0] c2
);
/********************/
//20MHz
parameter T1US = 5'd20;
/********************/
reg [4:0] count_1us;
reg is1US;
always @(... | 6.951862 |
module counter_module_tb;
reg clk;
reg rst_n;
/*
wire _1us; //由寄存器驱动
wire _is1US; //由组合逻辑驱动
wire [4:0]c1;
wire _3us;
wire _is3US;
wire [5:0]c2;
counter_module_1us_3us u1
(
.clk(clk),
.rst_n(rst_n),
._1us(_1us),
._is... | 6.951862 |
module counter_modulo_k #(
parameter M = 20
) (
input clk,
aclr,
enable,
output reg [N-1:0] Q,
output reg rollover
);
localparam N = clogb2(M - 1);
function integer clogb2(input [31:0] v);
for (clogb2 = 0; v > 0; clogb2 = clogb2 + 1) v = v >> 1;
endfunction
always @(posedge clk, n... | 6.951862 |
module counter_modulo_20 (
input [2:0] KEY,
output [9:0] LEDR
);
counter_modulo_k #(20) counter (
~KEY[0],
KEY[1],
KEY[2],
LEDR[4:0],
LEDR[9]
);
endmodule
| 6.951862 |
module counter_modulo_k #(
parameter M = 20
) (
input clk,
aclr,
enable,
output reg [N-1:0] Q,
output reg rollover
);
localparam N = clogb2(M - 1);
function integer clogb2(input [31:0] v);
for (clogb2 = 0; v > 0; clogb2 = clogb2 + 1) v = v >> 1;
endfunction
always @(posedge clk, n... | 6.951862 |
module counter_modulo_M #(
parameter M = 10
) (
input clk,
aclr,
enable,
output reg [N-1:0] Q
);
localparam N = clogb2(M - 1);
function integer clogb2(input [31:0] v);
for (clogb2 = 0; v > 0; clogb2 = clogb2 + 1) v = v >> 1;
endfunction
always @(posedge clk, negedge aclr)
if (!aclr... | 6.951862 |
module counter_mod_M (
input CLOCK_50,
input [1:0] SW,
output [0:6] HEX0
);
counter counter0 (
CLOCK_50,
SW[0],
SW[1],
HEX0
);
endmodule
| 7.524421 |
module counter_mod_M_1s_interval #(
parameter M = 10
) (
input CLOCK_50,
aclr,
enable,
output [N-1:0] Q
);
localparam intervalSize = clogb2(50000000);
localparam N = clogb2(M);
function integer clogb2(input [31:0] v);
for (clogb2 = 0; v > 0; clogb2 = clogb2 + 1) v = v >> 1;
endfunction... | 7.524421 |
module counter_mod_M_rollover #(
parameter M = 20
) (
input clk,
aclr,
enable,
output reg [N-1:0] Q,
output rollover
);
localparam N = clogb2(M - 1);
function integer clogb2(input [31:0] v);
for (clogb2 = 0; v > 0; clogb2 = clogb2 + 1) v = v >> 1;
endfunction
always @(posedge clk,... | 7.524421 |
module counter_mod_M_rollover_aload #(
parameter M = 10
) (
input clk,
aclr,
enable,
aload,
input [N-1:0] data,
output reg [N-1:0] Q = {N{1'b0}},
output rollover
);
localparam N = clogb2(M - 1);
function integer clogb2(input [31:0] v);
for (clogb2 = 0; v > 0; clogb2 = clogb2 + ... | 7.524421 |
module counter_mod_M_rollover_board (
input CLOCK_50,
KEY1,
KEY2,
output [4:0] LEDR,
output LEDR9
);
counter_mod_M_rollover#(20) (
CLOCK_50, KEY1, KEY2, LEDR, LEDR9
);
endmodule
| 7.524421 |
module counter_ms (
input clk,
input rst,
input [17:0] clocks_in_ms,
output reg [31:0] time_ms,
output reg pulse_ms
);
reg [17:0] cnt_ms;
always @(posedge clk)
if (rst) begin
cnt_ms <= 0;
time_ms <= 0;
pulse_ms <= 0;
end else if (cnt_ms >= clocks_in_ms) begin
... | 7.525342 |
module counter_n (
clk,
en,
r,
q,
co
);
parameter n = 2; //����n��ʾ������ģ
parameter counter_bits = 1; //����counter_bits��ʾ������λ��
input clk, en, r;
output co;
output [counter_bits-1:0] q;
reg [counter_bits-1:0] q = 0;
assign co = (q == (n - 1)) && en; //��λ
always @(posedg... | 6.719488 |
module counter_nbit_sync #(
parameter CNTR_WIDTH = 8
) (
// Inputs
input clk,
input rst,
input clken,
input sig_in,
// Outputs
output overflow_out,
output [CNTR_WIDTH-1:0] count_out
);
// Local Parameter Declarations
localparam MAXCOUNT = 2 ** CNTR_WIDTH - 1;
// Variable Decl... | 7.161793 |
module: counter_nbit_sync
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`define CNTR_WIDTH 8
module counter_nbit_sync_tb;
// Inputs
reg clk;
reg rst;
reg clken;
reg sig_in;
// Ou... | 6.674563 |
module counter_nested_if (
input clock,
input reset,
input c1,
input c2,
output reg [3:0] cnt_o
);
reg [4:0] cnt_o_next;
always @(*) begin
if (c1 == 1) begin
if (c2 == 1) begin
cnt_o_next = cnt_o + 3;
end else begin
cnt_o_next = cnt_o + 1;
end
end else... | 6.576617 |
module COUNTER_NOTUSE #(
// parameter
parameter COUNT_BIT = 2,
)
(
// port
input clk,
input rst_n,
input en,
input mode, // 1'b0 : down, 1'b1: : up
output [COUNT_BIT-1:0] cnt_o;
);
localparam DOWN = 1'b0;
reg [COUNT_BIT-1:0] cnt_temp;
... | 8.034557 |
module counter_N_bits #(
parameter N = 16
) (
input clk,
aclr,
enable,
output reg [N-1:0] Q
);
always @(posedge clk, negedge aclr)
if (!aclr) Q <= {N{1'b0}};
else if (enable) Q <= Q + 1'b1;
else Q <= Q;
endmodule
| 7.342358 |
module counter_odd (
reset,
clk,
enable,
count
);
input reset, clk;
input enable;
output reg [9:0] count;
always @(posedge clk or posedge reset) begin
if (reset) begin
count = 10'd0;
end else if (enable) begin
if (count == 0) count = 10'd1;
else count = count + 2;
... | 7.170729 |
module counter_opt (
input clk,
input reset,
output q
);
reg [2:0] count;
assign q = count[0];
always @(posedge clk, posedge reset) begin
if (reset) count <= 3'b000;
else count <= count + 1;
end
endmodule
| 7.038809 |
module counter_opt (
input clk,
input reset,
output q
);
reg [2:0] count;
assign q = (count[2:0] == 3'b100);
always @(posedge clk, posedge reset) begin
if (reset) count <= 3'b000;
else count <= count + 1;
end
endmodule
| 7.038809 |
module counter_opt2 (
clk,
reset,
q
);
wire [2:0] _00_;
wire _01_;
wire _02_;
input clk;
reg [2:0] count;
output q;
input reset;
assign _02_ = ~(count[1] | count[0]);
assign q = _02_ & count[2];
assign _00_[0] = ~count[0];
assign _00_[1] = count[1] ^ count[0];
assign _01_ = count[1] ... | 6.569286 |
module counter_parameter #(
parameter WIDTH = 8,
//Bit width for output
MAX_VALUE = 200
)
//Maximun value for counter)
(
input clk,
RST,
output reg [WIDTH - 1:0] counter
);
//Load other module(s)
//Definition for Variables in the module
//Logic
always @(posedge clk or negedge RST) be... | 7.928898 |
modules
module counter_parameter_test;
//defination for Variables
reg clk;
reg reset;
wire[7:0] counter1;
wire[3:0] counter2;
wire[2:0] counter3;
//Connection to the modules
top_counter_parameter T1(.clk(clk), .RST(reset),
.counter1(counter1), .counter2(counter2),
.cou... | 6.626478 |
module counter_products (
input clk,
input [3:0] inc,
input [3:0] dec,
output [13:0] product0,
output [13:0] product1,
output [13:0] product2,
output [13:0] product3
);
reg [13:0] cuenta[3:0];
assign product0 = cuenta[0];
assign product1 = cuenta[1];
assign product2 = cuenta[2];
a... | 6.970951 |
module counter_receipts (
input clk,
input up,
output [13:0] count
);
reg [13:0] cuenta;
assign count = cuenta;
always @(posedge clk) begin
if ((cuenta < 9999) && up) cuenta = cuenta + 1;
end
endmodule
| 6.894997 |
module counter_reg (
input clk,
output reg [7:0] a
);
always @(posedge clk) begin
a = a + 1;
end
initial begin
a = 0;
end
endmodule
| 7.776229 |
module d_flipflop (
d,
clk,
q,
set,
clear
); // Not using qbar over here, to simplify logic.
input d, clk, set, clear;
output reg q;
initial begin // Clearing the flipflop.
q <= 0;
end
always @(posedge clk) begin
if (set == 1'b1) begin
q <= 1;
end else if (clear == 1... | 7.276171 |
module counter_rollover #(
parameter W = 256, // width of counter
parameter N = 4
) // how many parts contain counter?
(
input wire CLK,
input wire ENABLE,
input wire LOAD,
input wire [W-1:0] DI,
output wire [W-1:0] DO
);
reg [(W/N)-1:0] cnt[N-1:0];
wire [... | 8.176742 |
module counter_rollover2 #(
parameter W = 8, // width of counter
parameter N = 2
) // not used, always equal to 2
(
input wire CLK,
input wire ENABLE,
input wire LOAD,
input wire [W-1:0] DI,
output wire [W-1:0] DO
);
reg [(W/2)-1:0] CounterMSB;
reg [(W/2)-1... | 8.176742 |
module counter_rollover_tb ();
parameter WIDTH_DATA = 16;
parameter PART_OF_DATA = 4;
// clock generator settings:
parameter cycles_reset = 2; // rst active (clk)
parameter clk_period = 10; // clk period ns
parameter clk_delay = 0; // clk initial delay
reg clk; // clock
reg rst; // sync reset
... | 8.176742 |
module counter_s (
input clk,
go,
clr,
output s_tick
);
parameter DVSR = 10000_0000 - 1;
reg [23:0] s_reg;
wire [23:0] s_next;
//Ĵ
always @(posedge clk, posedge clr) begin
s_reg <= s_next;
end
//һ״̬
assign s_next = (clr || (s_reg == DVSR && go)) ? 0 : (go) ? s_reg + 1 : s_reg;
... | 6.67131 |
module Counter_Second_Use (
input clkinput,
input reset,
output reg [3:0] first,
output reg [3:0] second,
output reg carry
);
always @(posedge clkinput, posedge reset) begin
if (reset) begin
first <= 0;
second <= 0;
end else begin
if (second == 9) begin
second <=... | 6.641902 |
module counter_sim ();
reg CLK, clr, N;
wire A0, A1, A2, A3;
design_1 ul (
A0,
A1,
A2,
A3,
CLK,
N,
clr
);
initial begin
CLK = 0;
clr = 0;
N = 1;
end
always #5 CLK = ~CLK;
always #100 clr = ~clr;
endmodule
| 6.584786 |
module counter_simple (
output reg [5:0] count,
input clock,
input rst_n,
input dir
);
always @(posedge clock or negedge rst_n) begin
if (!rst_n) count <= (dir) ? 6'b11_1111 : 6'b0;
else begin
if (!dir) count <= count + 1;
else count <= count - 1;
end
end
endmodule
| 7.158346 |
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