code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module counter_SUB_bytes (
clk,
rst,
start,
out,
flag_sub,
flag_shift
);
input wire clk, rst, start;
output reg [3:0] out;
output reg flag_sub, flag_shift;
always @(posedge clk or negedge rst) begin
if (!rst) begin
out <= 4'b0;
flag_sub <= 1'b0;
flag_shift <= 1'b0... | 6.759235 |
module counter_testbench ();
// Test bench gets wires for all device under test (DUT) outputs:
wire [3:0] out;
// Regs for all DUT inputs:
reg clk;
reg reset;
counter dut ( // (dut means device under test)
// Outputs
.out (out[3:0]),
// Inputs
.reset(reset),
.cl... | 6.694606 |
module counter_tb;
reg clk, reset, enable;
wire [3:0] count;
counter U0 (
.clk (clk),
.reset (reset),
.enable(enable),
.count (count)
);
endmodule
| 7.169317 |
module counter_tb;
reg clk, reset, enable;
wire [3:0] count;
counter U0 (
.clk (clk),
.reset (reset),
.enable(enable),
.count (count)
);
initial begin
clk = 0;
reset = 0;
enable = 0;
end
always #5 clk = !clk;
endmodule
| 7.169317 |
module counter_tb;
reg clk, reset, enable;
wire [3:0] count;
counter U0 (
.clk (clk),
.reset (reset),
.enable(enable),
.count (count)
);
initial begin
clk = 0;
reset = 0;
enable = 0;
end
always #5 clk = !clk;
initial begin
$dumpfile("counter.vcd");
$dump... | 7.169317 |
module: Part2_4bit_counter_modern
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module counter_test;
// Inputs
reg clk;
reg rst;
// Outputs
wire [3:0] a;
// Instantiate the Unit ... | 6.724104 |
module counter_testbench ();
reg clock = 0;
reg ce;
wire [3:0] LEDS;
counter ctr (
.clk (clock),
.ce (ce),
.LEDS(LEDS)
);
// Notice that this code causes the `clock` signal to constantly
// switch up and down every 4 time steps.
always #(4) clock <= ~clock;
initial begin
`ifdef I... | 6.694606 |
module: counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module counter_textb;
// Inputs
reg clk;
reg rst_n;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (U... | 7.040838 |
module counter_three (
out,
reverse,
pause,
clk,
reset
);
output [3:0] out;
input reverse, pause, clk, reset;
wire [3:0] Q, D, Q_next, next, next_above, increment;
register #(4) counter (
Q,
D,
clk,
~pause,
reset
);
mux2v #(4) mux_dir (
increment,
... | 7.129057 |
module counter_tmp #(
parameter CNT_SIZE = 32 + 8,
parameter CNT_SIZE_WIDTH = 6
) (
input clk,
input reset,
input flush,
input cnt_add_flag,
output [CNT_SIZE_WIDTH-1:0] cnt,
output cnt_end
);
reg [CNT_SIZE_WIDTH-1:0] cnt_r;
assign cnt = cnt_r;
always @(posedge clk) begin
if (r... | 7.268126 |
module counter_toggle_out (
input clk ,
input reset_n ,
input enable ,
input [31:0] i_cnt_th ,
output reg o_toggle
);
reg [31:0] cnt_always;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
cnt_always <= 0;
o_toggle <= 0;
end else if (!enabl... | 7.754219 |
module Counter_top #(
parameter DWIDTH = 7
) (
input clk,
input rst_n,
input start_i,
input [DWIDTH-1:0] cnt_val_i,
output [DWIDTH-1:0] cnt_o,
output done_o
);
wire [DWIDTH-1:0] cnt_w;
wire en_w;
Counter #(
.D... | 7.417963 |
module counter_toplevel (
input clk,
input rst,
input enable,
output [WIDTH-1:0] contador,
output valid
);
parameter WIDTH = 5;
enable_counter #(
.WIDTH(WIDTH)
) cnt (
.clk(clk),
.rst(rst),
.enable(enable),
.contador(contador),
.valid(valid)
);
`ifdef CO... | 6.935445 |
module counter_to_decoder (
clkup,
switch,
reset,
tcount,
clk,
pcount,
wtime1,
wtime2,
full_flag,
empty_flag,
alarm
);
//input are all input in project
//output are all output in project
input clkup, switch, reset, clk;
input [1:0] tcount;
//number of bits of tailer... | 7.696607 |
module----------
module counter_to_decoder_dut();
reg clkup,switch,clk,reset;
reg [1:0] tcount;
wire [6:0]wtime1; //output on sevensegment2
wire [6:0]wtime2; // output on sevensegment3
wire [6:0] pcount; //output on sevensegment 1
wire full_flag,empty_flag,alarm;
//------------------
initial
begin
clk=0;
tcount=2'b0... | 7.185136 |
module counter_to_decoder (
clkup,
switch,
reset,
tcount,
clk,
pcount,
wtime1,
wtime2,
full_flag,
empty_flag,
alarm
);
//input are all input in project
//output are all output in project
input clkup, switch, reset, clk;
input [1:0] tcount;
//number of bits of tailer... | 7.696607 |
module counter_T_4_bits (
input [1:0] SW,
input [0:0] KEY,
output [0:6] HEX0
);
wire [3:0] number;
counter counter0 (
KEY[0],
SW[0],
SW[1],
number
);
displayer displayNumber (
number,
HEX0
);
endmodule
| 7.898151 |
module counter_T_4_bits_board (
input KEY0,
input [1:0] SW,
output [6:0] HEX0
);
wire [3:0] counter_value;
counter_T_4_bits(
KEY0, SW[0], SW[1], counter_value
); decoder_hex_16(
counter_value, HEX0
);
endmodule
| 7.898151 |
module counter_T_8_bits (
input [1:0] SW,
input [0:0] KEY,
output [0:6] HEX0,
HEX1
);
wire [7:0] number;
counter counter0 (
KEY[0],
SW[0],
SW[1],
number
);
integer modulo16, multiple16;
always @(*) begin
modulo16 = number % 16;
multiple16 = number / 16;
en... | 7.39969 |
module counter_up (
reset,
clk,
enable,
count
);
input reset, clk;
input enable;
parameter COUNT_LEN = 10;
output reg [COUNT_LEN:0] count;
always @(posedge clk or posedge reset) begin
if (reset) begin
count = 0;
end else if (enable) begin
count = count + 1;
end else ... | 6.708914 |
module defines an up/down counter with
// asynchronous reset inputs, and synchronous load,
// up/down control, and count enable.
//
/***************************************************************/
// DEFINES
//
// TOP MODULE
module counter_updown(
// input clock
clk,
// in... | 7.2734 |
module counter_up_4_bit (
input clk,
output [3:0] count
);
reg clear;
reg [3:0] count;
initial begin
count = 4'b000;
end
always @(posedge clk) begin
$display("At time : %d; count is %d", $time, count);
if (clear) begin
count = 4'd0;
clear = 1'b0;
end else begin
... | 6.805363 |
module counter_up_4_bit_test;
wire [3:0] count_variable;
reg clk;
initial begin
clk = 1'b0;
forever begin
#5 clk = ~clk;
end
end
counter_up_4_bit wire_driver (
clk,
count_variable
);
initial begin
#200 $finish;
end
endmodule
| 6.805363 |
module counter_up_down #(
parameter WIDTH = 16
) (
input clk,
reset,
up_down,
output reg [WIDTH-1:0] count
);
always @(posedge clk) begin
if (reset) count <= 0;
else if (up_down) count <= count + 1;
else count <= count - 1;
end
endmodule
| 6.866722 |
module Counter_Up_Down_4bit (
clk,
CLRN,
CIN,
DNUP,
QA,
QB,
QC,
QD
);
input wire clk;
input wire CLRN;
input wire CIN;
input wire DNUP;
output wire QA;
output wire QB;
output wire QC;
output wire QD;
wire SYNTHESIZED_WIRE_26;
wire SYNTHESIZED_WIRE_2;
wire SYNTHES... | 6.729336 |
module counter_up_down_4_bit (
input clk,
input down_counting_boolean,
output [3:0] count
);
reg set;
reg clear;
reg [3:0] count;
initial begin
set = 1'b0;
clear = 1'b0;
if (down_counting_boolean) begin
// MOD 16 DOWN counter (counting from 15-0)
count = 4'd15;
//... | 6.866722 |
module counter_up_down_4_bit_test;
wire [3:0] count_variable;
reg clk;
reg down_counting_boolean;
initial begin
down_counting_boolean = 1'b0; // Down Counting is OFF
clk = 1'b0;
forever begin
#5 clk = ~clk;
end
end
counter_up_down_4_bit wire_driver (
clk,
down_counting... | 6.866722 |
module counter_up_down_tb #(
parameter WIDTH = 2
) ();
reg clk = 0, reset, up_down;
wire [WIDTH-1:0] count;
counter_up_down #(WIDTH) uut (
clk,
reset,
up_down,
count
);
always #5 clk = ~clk;
initial begin
reset = 1'b1;
up_down = 1'b1;
#10 up_down = 1'b0;
#10 r... | 6.866722 |
module counter_up_tb ();
reg clk, clr;
wire [3-1:0] counter;
counter_up #(
.N(3)
) DUT (
.clk(clk),
.clr(clr),
.counter(counter)
);
//sirve para generar el grafico en el sitio online
initial begin
$dumpfile("dump.vcd");
$dumpvars;
#200 $finish;
end
//creo el clk... | 7.173887 |
module Counter_v2 #(
// Parameter
parameter COUNT_NUM = 4
) (
// Port
input clk,
input rst_n,
input start_i,
output run_o,
output done_o
);
localparam COUNT_LG2 = $clog2(COUNT_NUM);
localparam IDLE = 2'b00;
localparam RUN = 2'b01;
localparam DONE = 2'b10;
reg [1:0] c_state,... | 8.138685 |
module counter_top (
clock,
reset,
button,
ones,
tens
);
input button;
wire button;
wire button_debounced;
input clock;
wire clock;
output [3:0] ones;
wire [3:0] ones;
input reset;
wire reset;
output [3:0] tens;
wire [3:0] tens;
counter counter_component (
.button_debou... | 6.97985 |
module counter_with_button (
input clk,
input [4:0] sw,
output [3:0] an,
output [6:0] seg
);
wire boton1_mas, boton2_mas;
wire boton1_menos, boton2_menos;
wire reset;
reg [6:0] count_1;
reg [6:0] count_2;
wire clock;
reg rst = 1'b0;
DeBouncer_D(
clk, sw[0], boton1_menos
); DeBo... | 6.844271 |
module counter_with_ld #(
parameter n = 8
) (
clk,
rst,
inc_cnt,
ld,
ld_value,
co,
count_out
);
input clk, inc_cnt, rst, ld;
input [n-1:0] ld_value;
output co;
output reg [n-1:0] count_out;
always @(posedge clk) begin
if (rst) begin
count_out <= {n{1'b0}};
end els... | 6.844271 |
module counter_with_ld(
// clk,
// rst,
// ld_value_lsb,
// ld_value_msb,
// ld,
// inc_cnt,
// co,
// count_out
// );
// input clk,inc_cnt,rst,ld;
// input [3:0]ld_value_lsb;
// input [5:0] ld_value_msb;
// output co;
// output reg [8:0] count_out;
// always @(posedge clk) begin
// ... | 6.844271 |
module counter_with_tlast (
input wire i_clk,
output wire [7:0] o_data,
output wire o_tlast
);
reg [10:0] r_counter = 0;
assign o_data = r_counter[7:0];
assign o_tlast = (r_counter == 2047);
always @(negedge i_clk) begin
r_counter <= r_counter + 1;
end
endmodule
| 6.844271 |
module counter_wrapper (
clk,
rst,
rst_count,
inc_count,
co,
count_out
);
input clk, rst_count, inc_count, rst;
output co;
output reg [7:0] count_out;
always @(posedge clk) begin
if (rst_count | rst) begin
count_out <= 8'b0;
end else begin
if (inc_count) begin
... | 6.587825 |
module Counter_x (
input clk,
input rst,
input clk0,
input clk1,
input clk2,
input counter_we,
input [31:0] counter_val,
input [1:0] counter_ch, //Counter channel set
output counter0_OUT,
output counter1_OUT,
output counter2_OUT,
output [31:0] counter_out
);
reg [32:... | 6.554661 |
module top (
input wire clk,
output wire [3:0] led
);
wire [63:0] emio_gpio_o;
wire [63:0] emio_gpio_t;
wire [63:0] emio_gpio_i;
wire clk_bufg;
BUFG BUFG (
.I(clk),
.O(clk_bufg)
);
wire en_counter = ~emio_gpio_o[0];
wire count_direction = ~emio_gpio_o[1];
reg [31:0] counter = 0;... | 7.233807 |
module: counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module countetb;
// Inputs
reg clk;
reg reset;
// Outputs
wire [31:0] out;
// Instantiate the Unit Under Test (UUT)
... | 7.040838 |
module
:Version
1.0
:Modified
2015-05-31
Copyright (C) 2015 Tianyu Dai (dtysky) <dtysky@outlook.com>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (... | 7.135037 |
module countgen_counter (
clk,
rst,
in,
period
);
parameter scan_window = 64;
input wire clk;
input wire rst;
input wire in;
output reg [31:0] period;
reg [scan_window-1:0] past;
reg [31:0] counter;
reg state;
always @(posedge clk) begin
if (rst) begin
period <= 0;
... | 7.316961 |
module countgen_generator (
clk,
rst,
out,
period
);
input wire clk;
input wire rst;
output reg out;
input wire [31:0] period;
reg [31:0] counter;
always @(posedge clk) begin
if (rst) begin
counter <= 0;
out <= 0;
end else begin
if (counter + 1 < period >> 1) be... | 7.003637 |
module countgen_tb ();
reg clk, rst, cyc, stb, we;
reg [5:0] adr;
reg [31:0] dat_i;
wire [31:0] dat_o;
wire ack;
wire [7:0] gens;
reg [31:0] period;
countgen cg (
.clk_i(clk),
.rst_i(rst),
.cyc_i(cyc),
.stb_i(stb),
.adr_i(adr),
.we_i(we),
.dat_i(dat_i),
... | 6.803626 |
module countgen (
// 8bit WISHBONE bus slave interface
clk_i, // clock
rst_i, // reset (asynchronous active low)
cyc_i, // cycle
stb_i, // strobe
adr_i, // address
we_i, // write enable
dat_i, // data input
dat_o, // data output
ack_o, // normal bus termination
coun... | 7.82445 |
module CountingBlock #(
parameter N = 256,
parameter N2 = 8,
parameter S = 32,
parameter S2 = 5,
parameter CW = 32
) (
input clk,
input reset,
input do_hier,
input exe_start_as,
input [CW-1:0] init_count_on_jump,
input call_as_cb,
input retn_as_cb,
input cnt_inc_as... | 7.577609 |
module CountingOnes (
input [7:0] in,
output [3:0] glycemicIndex
);
//https://stackoverflow.com/questions/46721548/in-verilog-counting-and-outputting-the-number-of-1s-in-an-8bit-input
assign glycemicIndex = in[0] + in[1] + in[2] + in[3] + in[4] + in[5] + in[6] + in[7];
endmodule
| 6.880161 |
module: CountingOnes
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module countingonesTest;
// Inputs
reg [7:0] a;
// Outputs
wire [3:0] y;
// Instantiate the Unit Under Test (UUT... | 6.914402 |
module CountInRange #(
parameter COUNTWIDTH = 7,
parameter COUNTLIM_L = 0,
parameter COUNTLIM_H = 99 // default for count in range 0..99
) (
input wire clk,
input wire enable,
input wire direction,
output reg [COUNTWIDTH-1:0] counter,
output wire done
);
always @(posedge clk) begin
... | 6.980959 |
module counton6 (
input inpulse,
input rst,
output [3:0] cnt,
output reg outpulse
);
//THIS IS SIMILAR TO counton9 just counts up to 6 and inputs a 1-->0 pulse
reg [3:0] count_q, count_d;
assign cnt = count_q;
always @(count_q) begin
if (count_q == 4'd5) begin
count_d = 4'd0;
... | 6.779647 |
module countonine (
input inpulse,
input rst,
output [3:0] cnt,
output reg outpulse
);
reg [3:0] count_q, count_d;
assign cnt = count_q; //output to BCD digit
//Feedback operation of flip flop ouput to increment to flip flop input is assumed
always @(count_q) begin
if (count_q == 4'd9) be... | 6.833732 |
module countrce #(
parameter WIDTH = 4
) (
output reg [WIDTH-1:0] q,
input wire [WIDTH-1:0] d,
input wire ld, // load the counter
input wire ce, //clock enable
input wire rst, // synchronous reset
input wire clk
);
wire [WIDTH-1:0... | 7.187181 |
module CountRegister (
input [7:0] Count_in,
input CLK,
input RESET,
input Count_load,
input Count_dec,
output reg [7:0] Count_out,
output reg zero_flag
);
always @(posedge CLK or negedge RESET) begin
if (RESET == 0) begin
Count_out = 0;
zero_flag = |Count_out;
end else... | 8.007563 |
module countsec (
input wire clk,
output wire [3:0] data
);
//-- Parametro del divisor. Fijarlo a 1Hz
//-- Se define como parametro para poder modificarlo desde el testbench
//-- para hacer pruebas
parameter M = `F_1Hz;
//-- Señal de reloj de 1Hz. Salida del divisor
wire clk_1HZ;
//-- Contador ... | 7.560327 |
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q
);
reg [3:0] acc;
initial acc = 0;
assign q = acc;
always @(posedge clk) begin
if (reset) acc = 4'd0;
else begin
if (slowena)
if (acc == 4'd9) acc = 4'd0;
else acc += 1'd1;
end
end
en... | 7.203305 |
module counttest (
input [11:0] test,
output [ 5:0] sum
);
parameter WIDTH = 12;
// NOTE: $clog2 was added in 1364-2005, not supported in 1364-1995 or 1364-2001
reg [5:0] count_ones;
assign sum = count_ones;
integer idx;
always @* begin
count_ones = {WIDTH{1'b0}};
for (idx = 0; idx < WIDT... | 6.639519 |
module countUD10L (
input clk,
input Up,
input Dw,
input reset,
input LD,
input [9:0] D,
output [9:0] Q
);
wire UTC, DTC;
countUD5L counter1 (
.clkin(clk),
.Up(Up),
.Dw(Dw),
.reset(reset),
.LD(LD),
.D(D[4:0]),
.Q(Q[4:0]),
.UTC(UTC),
... | 6.886442 |
module countUD4L (
input clk,
input Up, //count enable (increment)
input Dw, //not count enable (decrement)
input LD,
input [3:0] Din,
output [3:0] Q,
output UTC,
output DTC
);
wire [3:0] D;
wire upen, dwen;
assign upen = Up & ~Dw;
assign dwen = Dw & ~Up;
assign D[0] = (LD &... | 6.565201 |
module count_1 (
input wire clk_in,
input reset,
output reg [7:0] count_out
);
always @(posedge clk_in) begin
case (reset)
1'b1: count_out = 8'b00000000;
1'b0: count_out = count_out + 1;
endcase
end
endmodule
| 6.589112 |
module count_1s (
input clk, //系统时钟
input sys_reset_n, //复位信号
input EN, //使能 保持
output reg [7:0] data_s, //秒计时器
output reg [7:0] data_m, //分钟计时器
output [3:0] point //点
);
parameter time_60 = 8'd60;
parameter MAX_NUM = 28'd24_999_999;
reg [27:0] cnt; //1s计数器
reg clk_1s; //1s脉冲... | 6.796143 |
module count_6 (
input wire rst,
input wire clk,
input wire en,
output reg [3:0] count,
output reg co
);
always @(posedge clk) begin
if (rst) begin
count <= 4'b0;
co <= 1'b0;
end else if (en) begin
if (count == 4'd5) begin
count <= 4'b0;
co <= 1'b0;
... | 6.611596 |
module count_60 (
input wire rst,
input wire rst2,
input wire clk,
input wire en,
output [3:0] count1,
output [3:0] count2,
output co
);
wire co10, co6;
count_10 u_count_10 (
.rst (rst),
.clk (clk),
.en (en),
.count(count1),
.co (co10)
);
count... | 7.426304 |
module count_60 (
input wire rst,
input wire clk,
input wire en,
output wire [7:0] cont,
output wire co
);
wire co10, co6, co10_1;
wire [3:0] cont10, cont6;
count_10 u_count_10 (
.rst (rst),
.clk (clk),
.en (en),
.count(cont10),
.co (co10_1)
);
//and u... | 7.426304 |
module count_6 (
input wire rst,
input wire clk,
input wire en,
output reg [3:0] count,
output reg co
);
always @(posedge clk) begin
if (rst) begin
count <= 4'b0;
co <= 1'b0;
//assign co = 1'b0;
end else if (en) begin
if (count == 4'd5) begin
count <= 4'b0;
... | 6.611596 |
module count_adder32A;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#3500 init = 0;
#200000 $stop;
end
initial begin
$dumpfile("count_adder32A.vcd");
$dumpvars(0, count_adder32A);
end
genvar i;
///// testbench no input
/////////////////////////////
///// Circ... | 6.726988 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module top_module (
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
wire ena_mm, ena_hh;
// 分钟进位：59秒+1
assign ena_mm = ena & (ss == 8'h59);
// 小时进位：59分59秒+1
assign ena_hh = ena_mm & (mm == 8'h59);
cnt60 u_cnt60_ss (
clk,... | 7.203305 |
module count_cmp #(
parameter RSTVAL = 23,
parameter MAXVAL = 23,
parameter LEN = 5,
parameter CMPVAL = 22,
parameter mode = 0 // upcount
) (
input rst_n
, input clk
, input cnt_en
, input ld_en
, output cnt_full
, output cmp_matched
);
wire [LEN-1:0] cnt_val;
gene... | 7.572683 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/count_comb/count_comb.opt (
a0_pad,
a_pad,
b0_pad,
b_pad,
c0_pad,
c_pad,
d0_pad,
d_pad,
e0_pad,
e_pad,
f0_pad,
f_pad,
g0_pad,
g_pad,
h0_pad,
h_pad,
i0_pad,
... | 6.939825 |
module count_cycle_cw16_18 #(
parameter DATA_WIDTH = 32
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
input [15:0] cnt_limit,
output s_axis_tready,
input start_sig,
output af,
output m_axis_tvalid,
output [DATA_WIDTH-1:0] m_axis_... | 7.180356 |
module count_cycle_cw16_65 #(
parameter DATA_WIDTH = 32,
parameter TUSER_WIDTH = 32
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
input [15:0] cnt_limit,
input [TUSER_WIDTH-1:0] s_axis_tuser,
input s_axis_tlast,
output s_axis_tready,... | 7.180356 |
module count_cycle_cw16_8 #(
parameter DATA_WIDTH = 32
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
input [15:0] cnt_limit,
output s_axis_tready,
output m_axis_tvalid,
output [DATA_WIDTH-1:0] m_axis_tdata,
output m_axis_final_cnt,
... | 7.180356 |
module count_data_gen #(
parameter integer C_M_AXIS_DATA_WIDTH = 32
) (
// Global
input wire ACLK,
input wire ARESETN,
// Input
input wire sample_clk,
input wire enable,
// Regis... | 6.960887 |
module count_debounce (
input wire clk,
input wire rst_i,
input wire count_up_i,
output reg [6:0] count_o
);
//internal wires and regs
wire btn_press;
wire btn_ready;
//debounce the input
debounce debounce1 (
.clk(clk),
.rst_i(rst_i),
.btn_i(count_up_i),
.btn_press_o... | 7.573836 |
module count_fps (
//mudule clock
input clk, // 时钟信号
input rst_n, // 复位信号
input fps,
//user interface
output reg [19:0] data // 6个数码管要显示的数值
);
//parameter define
parameter MAX_NUM = 31'd5000_0000; // 计数器计数的最大值
//reg define
reg [31:0] cnt; //... | 7.195019 |
module count_frequent (
CLK,
nRST,
CHARACTER_IN,
FREQUENT_OUT
);
input CLK;
input nRST;
input [27:0] CHARACTER_IN;
output [15:0] FREQUENT_OUT;
reg [ 3:0] temp_frequent1;
reg [ 3:0] temp_frequent2;
reg [ 3:0] temp_frequent3;
reg [ 3:0] temp_frequent4;
reg [ 3:0] temp_character;
reg ... | 6.565665 |
module: count_leading_zeros
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module count_leading_zeros_tb;
// Inputs
reg [10:0] D;
// Outputs
wire [2:0] exp;
wire [3:0] sig;
wire f... | 7.232645 |
module counter_mod8 (
input wire clearn, // assincrono, active high
input wire clock,
output reg F
); // indica se o contador chegou a 0
reg [2:0] count;
reg active_count;
// para a contagem quando temos um posedge
always @(posedge clearn) begin
active_count = 1'b0;
end
// começa a ... | 6.886157 |
module count_reg #(
parameter D_WIDTH = 8
) (
input [D_WIDTH-1:0] count_load,
input en,
input load,
input rst,
input clk,
output reg [D_WIDTH-1:0] count
);
always @(posedge clk) begin
if (rst) begin
count <= 0;
end else begin
if (en) begin
if (load) begin
... | 6.636744 |
module count_regp #(
parameter D_WIDTH = 8
) (
input [D_WIDTH-1:0] count_load,
input en,
input load,
input rst,
input clk,
output reg [D_WIDTH-1:0] count
);
always @(posedge clk) begin
if (rst) begin
count <= 0;
end else begin
if (en) //if enable signal is high, then t... | 7.050114 |
module count_reset #(
parameter [19:0] num = 20'hffff0
) (
input clk_i,
output rst_o
);
reg [19:0] cnt = 20'd0;
reg rst_d0;
/*count for clock*/
always @(posedge clk_i) begin
cnt <= (cnt <= num) ? (cnt + 20'd1) : num;
end
/*generate output signal*/
always @(posedge clk_i) begin
rst_... | 6.868634 |
module count_reset_v1 #(
parameter [19:0] num = 20'hffff0
) (
input clk_i,
output rst_o
);
reg [19:0] cnt = 20'd0;
reg rst_d0;
/*count for clock*/
always @(posedge clk_i) begin
cnt <= (cnt <= num) ? (cnt + 20'd1) : num;
end
/*generate output signal*/
always @(posedge clk_i) begin
r... | 6.8048 |
module dff_counter_sid_top_tb ();
reg Clk, rst_n;
wire [3:0] sid;
//D.U.T. instantiation
count_sid test (
sid,
Clk,
rst_n
);
//初始化
initial begin
$dumpfile("Simulation/count_sid_tb.vcd");
$dumpvars;
$monitor($time, " out=%4b, <=== clk=%b, rst_n=%b", sid, Clk, rst_n);
Clk... | 7.347362 |
module count_up (
clock, // Clock input of the design
reset, // active high, synchronous Reset input
counter_out
); // 4 bit vector output of the counter
// End of port list
//-------------Input Ports-----------------------------
input clock;
input reset;
//-------------Output Ports------------... | 6.628158 |
module Coun_Baud // este modo es para generar los pulsos necesarios para el modo receptor y transmisor
#(
parameter N = 10, // number of bits incounter = log2(M)
M = 656 // mod-M Para una frecuencia de relog 100 MHZ --->9600bauds
) // M se obtiene de 100MHZ/(2X8X9600)
(
input wire clk,
reset,
ou... | 7.076451 |
module COUPLER #(
parameter P_WIDTH = 128
) (
input wire i_clk,
input wire [P_WIDTH-1:0] i_data,
output wire [2*P_WIDTH-1:0] o_data,
input wire i_enq,
input wire i_deq,
output o_full,
output o_empty
);
reg next_state;
reg state;
reg... | 8.346031 |
module Course_Design (
input clk,
input rst_n,
input uart_rx,
output [7:0] rx_data,
output [5:0] seg_sel,//数码管选通信号
output [7:0] seg_data,//数码管数据
output uart_tx,
output da1_clk, //DA1 时钟信号
output da1_wrt, //DA1 数据写信号
output [10:0] da1_data,
dout9, //... | 7.553696 |
module court (
input wire px_clk, // Pixel clock.
input wire [22:0] strVGA, // Stream VGA input.
output wire [25:0] strRGB // Stream RGB out.
);
// Bit address alias.
`define Active 0:0
`define VS 1:1
`define HS 2:2
`define YC 12:3
`define XC 22:13
`define R 23:23
`define G 24:... | 7.102438 |
module couter32 (
CLK,
EN,
nCLR,
DOUT
);
input CLK, EN, nCLR;
output DOUT[31:0];
reg [31:0] DOUT;
always @(posedge CLK or negedge nCLR) begin
if (nCLR == 0) begin
DOUT = 0;
end else if (EN == 1) begin
DOUT = DOUT + 1;
end
end
endmodule
| 6.941458 |
module Covariance (
input wire GO_cov,
input wire CLK_cov,
input wire signed [25:0] Xcen1,
input wire signed [25:0] Xcen2,
input wire signed [25:0] Xcen3,
input wire signed [25:0] Xcen4,
output wire signed [15:0] C11,
output wire signed [15:0] C12,
output wire signed [15:0] C13,
... | 7.477991 |
module CovController (
input wire GO,
input wire CLK,
output reg COV_busy,
output wire CLK_Multi,
output wire CLK_add_div,
output reg En_Multi,
output reg En_add_div
);
assign CLK_Multi = CLK;
assign CLK_add_div = CLK;
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
reg [3:... | 6.968802 |
module Coverage (
input clock,
input reset,
input [3:0] io_in1,
input [3:0] io_in2,
input [1:0] io_in3,
output io_out1,
output [3:0] io_out2
);
assign io_out1 = io_in1 != 4'h0 ? &io_in2 : |io_in2;
assign io_out2 = io_in2;
endmodule
| 6.665745 |
module cov_mhu
import bsg_cache_non_blocking_pkg::*;
(
input clk_i
, input reset_i
, input mhu_state_e mhu_state_r
, input data_mem_pkt_yumi_i
, input is_secondary
, input miss_fifo_v_i
, input tl_block_loading_i
);
covergroup cg_dequeue_mode @(negedge clk_i iff mhu_state_r == DEQU... | 6.634765 |
module bsg_two_fifo_width_p80 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [79:0] data_i;
output [79:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [79:0] data_o;
wire ready_o,v_o,N0,N1,enq_i,n... | 6.635899 |
module MetadataArray_tag_arr (
CLK,
RST,
init,
W0A,
W0E,
W0I,
W0M,
R1A,
R1E,
R1O
);
input [5:0] W0A;
input [87:0] W0I;
input [87:0] W0M;
input [5:0] R1A;
output [87:0] R1O;
input CLK;
input RST;
input init;
input W0E;
input R1E;
wire [87:0] R1O;
bsg_mem_... | 6.901681 |
module DataArray_T9 (
CLK,
RST,
init,
W0A,
W0E,
W0I,
W0M,
R1A,
R1E,
R1O
);
input [7:0] W0A;
input [127:0] W0I;
input [127:0] W0M;
input [7:0] R1A;
output [127:0] R1O;
input CLK;
input RST;
input init;
input W0E;
input R1E;
wire [127:0] R1O;
bsg_mem_1r1w_... | 6.622475 |
module RRArbiter_3 (
clk,
reset,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr,
io_in_1_bits_prv,
io_in_1_bits_store,
io_in_1_bits_fetch,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr,
io_in_0_bits_prv,
io_in_0_bits_store,
io_in_0_bits_fetch,
io_out_ready,... | 6.713066 |
module CompareRecFN (
io_a,
io_b,
io_signaling,
io_lt,
io_eq,
io_gt,
io_exceptionFlags
);
input [64:0] io_a;
input [64:0] io_b;
output [4:0] io_exceptionFlags;
input io_signaling;
output io_lt;
output io_eq;
output io_gt;
wire [4:0] io_exceptionFlags;
wire io_lt,io_eq,io_g... | 6.787862 |
module DivSqrtRecF64 (
clk,
reset,
io_inReady_div,
io_inReady_sqrt,
io_inValid,
io_sqrtOp,
io_a,
io_b,
io_roundingMode,
io_outValid_div,
io_outValid_sqrt,
io_out,
io_exceptionFlags
);
input [64:0] io_a;
input [64:0] io_b;
input [1:0] io_roundingMode;
output [... | 6.793472 |
module bsg_two_fifo_width_p73 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [72:0] data_i;
output [72:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [72:0] data_o;
wire ready_o,v_o,N0,N1,enq_i,n... | 6.635899 |
module bsg_nasti_client_resp (
clk_i,
reset_i,
nasti_r_valid_o,
nasti_r_data_o,
nasti_r_ready_i,
resp_valid_i,
resp_data_i,
resp_yumi_o
);
output [72:0] nasti_r_data_o;
input [72:0] resp_data_i;
input clk_i;
input reset_i;
input nasti_r_ready_i;
input resp_valid_i;
output ... | 6.750039 |
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