code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bsg_nasti_client (
clk_i,
reset_i,
nasti_aw_valid_i,
nasti_aw_data_i,
nasti_aw_ready_o,
nasti_w_valid_i,
nasti_w_data_i,
nasti_w_ready_o,
nasti_b_valid_o,
nasti_b_data_o,
nasti_b_ready_i,
nasti_ar_valid_i,
nasti_ar_data_i,
nasti_ar_ready_o,
nasti_r_vali... | 6.750039 |
module bsg_decode_num_out_p3 (
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
assign o = {1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_with_v_num_out_p3 (
i,
v,
o
);
input [1:0] i;
output [2:0] o;
input v;
wire [2:0] o, lo;
bsg_decode_num_out_p3 bd (
.i(i),
.o(lo)
);
assign o[2] = v & lo[2];
assign o[1] = v & lo[1];
assign o[0] = v & lo[0];
endmodule
| 7.148573 |
module bsg_two_fifo_width_p73_verbose_p0_allow_enq_deq_on_full_p1 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [72:0] data_i;
output [72:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [72:0] data... | 6.635899 |
module bsg_channel_tunnel_in_width_p73_num_in_p2_remote_credits_p128_use_pseudo_large_fifo_p1_lg_credit_decimation_p4
(
clk_i,
reset_i,
data_i,
v_i,
yumi_o,
data_o,
v_o,
yumi_i,
credit_local_return_data_o,
credit_local_return_v_o,
credit_remote_return_data_o,
credit_remot... | 6.961227 |
module bsg_channel_tunnel_width_p73_num_in_p2_remote_credits_p128_use_pseudo_large_fifo_p1 (
clk_i,
reset_i,
multi_data_i,
multi_v_i,
multi_yumi_o,
multi_data_o,
multi_v_o,
multi_yumi_i,
data_i,
v_i,
yumi_o,
data_o,
v_o,
yumi_i
);
input [74:0] multi_data_i;
o... | 6.961227 |
module bsg_rocket_node_client_rocc (
clk_i,
reset_i,
en_i,
rocc_cmd_v_o,
rocc_cmd_data_o,
rocc_cmd_ready_i,
rocc_resp_v_i,
rocc_resp_data_i,
rocc_resp_ready_o,
rocc_mem_req_v_i,
rocc_mem_req_data_i,
rocc_mem_req_ready_o,
rocc_mem_resp_v_o,
rocc_mem_resp_data_o,
... | 6.764292 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module cp
#(parameter num_sz = 16,
parameter max_tg = 128,
parameter in_blk = 1,
parameter out_blk = 1,
parameter obits = out_blk * 2 * num_sz,
parameter ibits = in_blk * 2 * num_sz
)(
input reset, clk,
input load,
/* the prefix time (sample ct) */
input [/*xxx*/0:0] param_Tg,
input [ibits-1:... | 6.781285 |
module CP0ForwardingUnit (
id_cp0Op,
ex_cs,
ex_sel,
ex_cp0Op,
mem_cs,
mem_sel,
mem_cp0Op,
cp0Forward
);
input [2:0] id_cp0Op;
input [4:0] ex_cs;
input [2:0] ex_sel;
input [2:0] ex_cp0Op;
input [4:0] mem_cs;
input [2:0] mem_sel;
input [2:0] mem_cp0Op;
output reg [1:0] cp... | 6.577497 |
module CP0Gen (
input [ `INST_BUS] inst,
input [ `INST_OP_BUS] op,
input [`REG_ADDR_BUS] rs,
input [`REG_ADDR_BUS] rd,
input [ `DATA_BUS] reg_data_1,
output reg cp0_write_en,
output reg cp0_read_en,
output reg [ `DATA_BUS] cp0_write_data,
out... | 7.595916 |
module CP0ReadProxy (
input [`CP0_ADDR_BUS] cp0_read_addr,
// from cp0
input [ `DATA_BUS] cp0_count_i,
input [ `DATA_BUS] cp0_status_i,
input [ `DATA_BUS] cp0_cause_i,
input [ `DATA_BUS] cp0_epc_i,
input [ `DATA_BUS] cp0_config0_i,
input [ `DATA_BUS] cp0_read_data_i,
... | 7.069684 |
module cp0_reg_bypass_mux ( /*autoarg*/
//Inputs
clk,
rst_n,
reg_cp0_addr,
reg_cp0_sel,
val_from_cp0,
ex_cp0_write_enable,
ex_cp0_write_addr,
ex_cp0_sel,
val_from_ex,
mm_cp0_write_enable,
mm_cp0_write_addr,
mm_cp0_sel,
val_from_mm,
wb_cp0_write_enable,
wb... | 6.585049 |
module CPA (
Sout,
Cout,
A,
B,
Cin
);
output Sout, Cout;
input A, B, Cin;
assign Sout = A ^ B ^ Cin;
assign Cout = (A && B) || (Cin && (A ^ B));
endmodule
| 6.928734 |
module cpa3_b10 (
input clk,
input rst_n,
input [7:0] in1,
input [7:0] in2,
input [8:0] in3,
output reg [9:0] summ
);
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
summ <= 10'b0;
end else begin
summ <= in1 + in2 + in3;
end
end
endmodule
| 6.854743 |
module cpa_b1 (
input x1,
input x2,
input ed,
input ec,
input stall,
input cin,
output cout,
output carry,
output summ
);
wire s1;
assign {cout, s1} = x1 + x2;
assign {carry, summ} = ((stall == 1'b1) ? ec : ed) + s1 + cin;
endmodule
| 7.224088 |
module cpa_b10 (
input clk,
input rst_n,
input [9:0] in1,
input [9:0] in2,
output reg [10:0] summ
);
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
summ <= 11'b0;
end else begin
summ <= in1 + in2;
end
end
endmodule
| 7.101783 |
module tb ();
reg reset, n_clk, p_clk;
cpci_clock_checker cc (
.error (error),
.clk_chk_p_max ('d3333333),
.clk_chk_n_exp ('d6250000),
.reset (reset),
.shift_amount(4'd3),
.p_clk (p_clk),
.n_clk (n_clk)
);
always #15 p_clk = ~p_clk;
always #8 n_clk = ~n_clk;
... | 7.195167 |
module cpci_clock_checker (
output error,
output reg [31:0] n_clk_count,
input [31:0] clk_chk_p_max, // MAX value for PCI counter
input [31:0] clk_chk_n_exp, // Expected value of n_clk counter.
input [3:0] shift_amount, // see below
input reset, // pci clock reset
input p_clk, //nomina... | 8.071602 |
module cpci_program_iface
(
output reg cpci_rp_done,
output reg cpci_rp_init_b,
output reg cpci_rp_cclk,
input cpci_rp_en,
input cpci_rp_prog_b,
input cpci_rp_din
);
// Set the clock period to 4 MHz
parameter CCLK_PERIOD = 250;
// Minimum amout of time to hold pr... | 8.192309 |
module ii2pp(p, i);
input `WORD i;
output `WORD p;
i2p p1(p `LO8,i `LO8);
i2p p2(p `HI8,i `HI8);
endmodule
| 7.17843 |
module i2p(p,i);
input wire `HALF i;
output wire `HALF p;
reg [7:0] look[255:0];
initial $readmemh2(look);
assign p = look[i];
endmodule
| 6.972574 |
module pp2ii(i,p);
output `WORD i;
input `WORD p;
i2p p1(i `LO8,p `LO8);
i2p p2(i `HI8,p `HI8);
endmodule
| 6.833023 |
module p2i(i,p);
output wire `HALF i;
input wire `HALF p;
reg [15:8] look[255:0];
initial $readmemh2(look);
assign i = look[p];
endmodule
| 6.950528 |
module CPI (
// Inputs
input wire [15:0] in0R,
input wire [15:0] in0I,
input wire [15:0] in1R,
input wire [15:0] in1I,
input wire [15:0] in2R,
input wire [15:0] in2I,
input wire [15:0] in3R,
input wire [15:0] in3I,
input wire [15:0] in4R,
input wire [15:0] in4I,
input wir... | 6.921358 |
module cpipe ( /*AUTOARG*/
// Outputs
cia,
co,
// Inputs
rst,
ci,
coa
);
input rst; // active high reset
input ci; // credit input
output cia; // credit input ack
output co; // credit output
input coa; // credit output ack
wire c0, c1; // internal wires
dc2 C0 (
... | 6.503277 |
module mux4to1 (
load,
sel,
bzin32,
in32,
out8,
clr
);
input [2:0] sel;
input [31:0] in32, bzin32;
input load, clr;
output [7:0] out8;
reg [7:0] out8;
wire [2:0] sel;
always @(sel or clr or load) begin
if (clr) out8 = 0;
else if (load) begin
case (sel)
3'b000... | 7.010477 |
module cpld_bridge #(
parameter BIT_RW = 9 // read/write control bit
) (
input clk, // mem_clk
input [5:0] cfg_nbits,
input ss,
input sck,
input mosi,
output miso,
inout dio
);
// last byte dir control
reg oe = 1'b1;
reg [5:0] cnt = 0;
reg sck1 = 0;
wire sck_f_edge = s... | 6.685515 |
module CJD4CE (
Q,
C,
CE,
CLR
) /* synthesis syn_black_box */;
output [3:0] Q;
input C, CE, CLR;
endmodule
| 7.024955 |
module CJD4RE (
Q,
C,
CE,
R
) /* synthesis syn_black_box */;
output [3:0] Q;
input C, CE, R;
endmodule
| 7.132299 |
module CJD5CE (
Q,
C,
CE,
CLR
) /* synthesis syn_black_box */;
output [4:0] Q;
input C, CE, CLR;
endmodule
| 6.821949 |
module CJD5RE (
Q,
C,
CE,
R
) /* synthesis syn_black_box */;
output [4:0] Q;
input C, CE, R;
endmodule
| 6.883776 |
module CJD8CE (
Q,
C,
CE,
CLR
) /* synthesis syn_black_box */;
output [7:0] Q;
input C, CE, CLR;
endmodule
| 7.011891 |
module CJD8RE (
Q,
C,
CE,
R
) /* synthesis syn_black_box */;
output [7:0] Q;
input C, CE, R;
endmodule
| 7.141391 |
module FDD4RE (
C,
R,
CE,
D,
Q
) /* synthesis syn_black_box */;
input C;
input R;
input CE;
input [3:0] D;
output [3:0] Q;
endmodule
| 6.535495 |
module FDD8RE (
C,
R,
CE,
D,
Q
) /* synthesis syn_black_box */;
input C;
input R;
input CE;
input [7:0] D;
output [7:0] Q;
endmodule
| 6.86479 |
module SRD16CE (
Q,
C,
CE,
CLR,
SLI
) /* synthesis syn_black_box */;
output [15:0] Q;
input C, CE, CLR, SLI;
endmodule
| 7.421337 |
module SRD16CLE (
Q,
C,
CE,
CLR,
SLI,
L,
D
) /* synthesis syn_black_box */;
output [15:0] Q;
input [15:0] D;
input C, CE, CLR, SLI, L;
endmodule
| 7.260501 |
module SRD16CLED (
Q,
C,
CE,
CLR,
SLI,
SRI,
LEFT,
L,
D
) /* synthesis syn_black_box */;
output [15:0] Q;
input [15:0] D;
input C, CE, CLR, SLI, SRI, LEFT, L;
endmodule
| 6.844107 |
module SRD16RE (
Q,
C,
CE,
R,
SLI
) /* synthesis syn_black_box */;
output [15:0] Q;
input C, CE, R, SLI;
endmodule
| 7.916339 |
module SRD16RLE (
Q,
C,
CE,
R,
SLI,
L,
D
) /* synthesis syn_black_box */;
output [15:0] Q;
input [15:0] D;
input C, CE, R, SLI, L;
endmodule
| 7.832787 |
module SRD16RLED (
Q,
C,
CE,
R,
SLI,
SRI,
LEFT,
L,
D
) /* synthesis syn_black_box */;
output [15:0] Q;
input [15:0] D;
input C, CE, R, SLI, SRI, LEFT, L;
endmodule
| 7.058108 |
module SRD4CE (
Q,
C,
CE,
CLR,
SLI
) /* synthesis syn_black_box */;
output [3:0] Q;
input C, CE, CLR, SLI;
endmodule
| 7.889194 |
module SRD4CLE (
Q,
C,
CE,
CLR,
SLI,
L,
D
) /* synthesis syn_black_box */;
output [3:0] Q;
input [3:0] D;
input C, CE, CLR, SLI, L;
endmodule
| 7.659346 |
module SRD4CLED (
Q,
C,
CE,
CLR,
SLI,
SRI,
LEFT,
L,
D
) /* synthesis syn_black_box */;
output [3:0] Q;
input [3:0] D;
input C, CE, CLR, SLI, SRI, LEFT, L;
endmodule
| 6.929059 |
module SRD4RE (
Q,
C,
CE,
R,
SLI
) /* synthesis syn_black_box */;
output [3:0] Q;
input C, CE, R, SLI;
endmodule
| 8.069639 |
module SRD4RLE (
Q,
C,
CE,
R,
SLI,
L,
D
) /* synthesis syn_black_box */;
output [3:0] Q;
input [3:0] D;
input C, CE, R, SLI, L;
endmodule
| 7.962629 |
module SRD4RLED (
Q,
C,
CE,
R,
SLI,
SRI,
LEFT,
L,
D
) /* synthesis syn_black_box */;
output [3:0] Q;
input [3:0] D;
input C, CE, R, SLI, SRI, LEFT, L;
endmodule
| 7.024657 |
module SRD8CE (
Q,
C,
CE,
CLR,
SLI
) /* synthesis syn_black_box */;
output [7:0] Q;
input C, CE, CLR, SLI;
endmodule
| 7.58738 |
module SRD8CLE (
Q,
C,
CE,
CLR,
SLI,
L,
D
) /* synthesis syn_black_box */;
output [7:0] Q;
input [7:0] D;
input C, CE, CLR, SLI, L;
endmodule
| 7.507903 |
module SRD8CLED (
Q,
C,
CE,
CLR,
SLI,
SRI,
LEFT,
L,
D
) /* synthesis syn_black_box */;
output [7:0] Q;
input [7:0] D;
input C, CE, CLR, SLI, SRI, LEFT, L;
endmodule
| 6.651966 |
module SRD8RE (
Q,
C,
CE,
R,
SLI
) /* synthesis syn_black_box */;
output [7:0] Q;
input C, CE, R, SLI;
endmodule
| 7.739062 |
module SRD8RLE (
Q,
C,
CE,
R,
SLI,
L,
D
) /* synthesis syn_black_box */;
output [7:0] Q;
input [7:0] D;
input C, CE, R, SLI, L;
endmodule
| 7.598941 |
module SRD8RLED (
Q,
C,
CE,
R,
SLI,
SRI,
LEFT,
L,
D
) /* synthesis syn_black_box */;
output [7:0] Q;
input [7:0] D;
input C, CE, R, SLI, SRI, LEFT, L;
endmodule
| 6.532182 |
module CJD4CE (
Q,
C,
CE,
CLR
);
parameter WIDTH = 4;
output [WIDTH-1:0] Q;
input C, CE, CLR;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE) begin
Q[0] <= !Q[WIDTH-1];
Q[WIDTH-1:1] <= Q[WIDTH-2:0];
end
end
... | 7.024955 |
module CJD4RE (
Q,
C,
CE,
R
);
parameter WIDTH = 4;
output [WIDTH-1:0] Q;
input C, CE, R;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE) begin
Q[0] <= !Q[WIDTH-1];
Q[WIDTH-1:1] <= Q[WIDTH-2:0];
end
end
endmodule
| 7.132299 |
module CJD5CE (
Q,
C,
CE,
CLR
);
parameter WIDTH = 5;
output [WIDTH-1:0] Q;
input C, CE, CLR;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE) begin
Q[0] <= !Q[WIDTH-1];
Q[WIDTH-1:1] <= Q[WIDTH-2:0];
end
end
... | 6.821949 |
module CJD5RE (
Q,
C,
CE,
R
);
parameter WIDTH = 5;
output [WIDTH-1:0] Q;
input C, CE, R;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE) begin
Q[0] <= !Q[WIDTH-1];
Q[WIDTH-1:1] <= Q[WIDTH-2:0];
end
end
endmodule
| 6.883776 |
module CJD8CE (
Q,
C,
CE,
CLR
);
parameter WIDTH = 8;
output [WIDTH-1:0] Q;
input C, CE, CLR;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE) begin
Q[0] <= !Q[WIDTH-1];
Q[WIDTH-1:1] <= Q[WIDTH-2:0];
end
end
... | 7.011891 |
module CJD8RE (
Q,
C,
CE,
R
);
parameter WIDTH = 8;
output [WIDTH-1:0] Q;
input C, CE, R;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE) begin
Q[0] <= !Q[WIDTH-1];
Q[WIDTH-1:1] <= Q[WIDTH-2:0];
end
end
endmodule
| 7.141391 |
module FDD4RE (
Q,
C,
CE,
D,
R
);
output [3:0] Q;
input C;
input CE;
input R;
input [3:0] D;
reg [3:0] Q;
always @(posedge C or negedge C)
if (R) Q = 4'b0;
else if (CE) Q[3:0] = D[3:0];
endmodule
| 6.535495 |
module FDD8 (
Q,
C,
D
);
output [7:0] Q;
input C;
input [7:0] D;
reg [7:0] Q;
always @(posedge C or negedge C) Q[7:0] = D[7:0];
endmodule
| 6.546037 |
module FDD8RE (
Q,
C,
CE,
D,
R
);
output [7:0] Q;
input C;
input CE;
input R;
input [7:0] D;
reg [7:0] Q;
always @(posedge C or negedge C)
if (R) Q = 8'b0;
else if (CE) Q[7:0] = D[7:0];
endmodule
| 6.86479 |
module FDDS (
Q,
C,
D,
S
);
output Q;
input C;
input S;
input D;
reg Q;
always @(posedge C or negedge C) begin
if (S) Q = 1'b1;
else Q = D;
end
endmodule
| 6.595514 |
module SRD16CE (
Q,
C,
CE,
CLR,
SLI
);
parameter WIDTH = 16;
output [WIDTH-1:0] Q;
input C, CE, CLR, SLI;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE) Q <= {Q[WIDTH-2:0], SLI};
end
endmodule
| 7.421337 |
module SRD16CLE (
Q,
C,
CE,
CLR,
D,
L,
SLI
);
parameter WIDTH = 16;
output [WIDTH-1:0] Q;
input C, CE, CLR, L, SLI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE)
if (L) Q <= D;
... | 7.260501 |
module SRD16CLED (
Q,
C,
CE,
CLR,
D,
L,
LEFT,
SLI,
SRI
);
parameter WIDTH = 16;
output [WIDTH-1:0] Q;
input C, CE, CLR, L, LEFT, SLI, SRI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (... | 6.844107 |
module SRD16RE (
Q,
C,
CE,
R,
SLI
);
parameter WIDTH = 16;
output [WIDTH-1:0] Q;
input C, CE, R, SLI;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE) Q <= {Q[WIDTH-2:0], SLI};
end
endmodule
| 7.916339 |
module SRD16RLE (
Q,
C,
CE,
L,
D,
R,
SLI
);
parameter WIDTH = 16;
output [WIDTH-1:0] Q;
input C, CE, L, R, SLI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE)
if (L) Q <= D;
else Q <= {Q[WIDTH-2:... | 7.832787 |
module SRD16RLED (
Q,
C,
CE,
D,
L,
LEFT,
R,
SLI,
SRI
);
parameter WIDTH = 16;
output [WIDTH-1:0] Q;
input C, CE, L, LEFT, R, SLI, SRI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE)
if (L) Q <=... | 7.058108 |
module SRD4CE (
Q,
C,
CE,
CLR,
SLI
);
parameter WIDTH = 4;
output [WIDTH-1:0] Q;
input C, CE, CLR, SLI;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE) Q <= {Q[WIDTH-2:0], SLI};
end
endmodule
| 7.889194 |
module SRD4CLE (
Q,
C,
CE,
CLR,
D,
L,
SLI
);
parameter WIDTH = 4;
output [WIDTH-1:0] Q;
input C, CE, CLR, L, SLI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE)
if (L) Q <= D;
el... | 7.659346 |
module SRD4CLED (
Q,
C,
CE,
CLR,
D,
L,
LEFT,
SLI,
SRI
);
parameter WIDTH = 4;
output [WIDTH-1:0] Q;
input C, CE, CLR, L, LEFT, SLI, SRI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE... | 6.929059 |
module SRD4RE (
Q,
C,
CE,
R,
SLI
);
parameter WIDTH = 4;
output [WIDTH-1:0] Q;
input C, CE, R, SLI;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE) Q <= {Q[WIDTH-2:0], SLI};
end
endmodule
| 8.069639 |
module SRD4RLE (
Q,
C,
CE,
D,
L,
R,
SLI
);
parameter WIDTH = 4;
output [WIDTH-1:0] Q;
input C, CE, R, SLI, L;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE)
if (L) Q <= D;
else Q <= {Q[WIDTH-2:0]... | 7.962629 |
module SRD4RLED (
Q,
C,
CE,
D,
L,
LEFT,
R,
SLI,
SRI
);
parameter WIDTH = 4;
output [WIDTH-1:0] Q;
input [WIDTH-1:0] D;
input C, CE, R, SLI, SRI, LEFT, L;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE)
if (L) Q <= D... | 7.024657 |
module SRD8CE (
Q,
C,
CE,
CLR,
SLI
);
parameter WIDTH = 8;
output [WIDTH-1:0] Q;
input C, CE, CLR, SLI;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE) Q <= {Q[WIDTH-2:0], SLI};
end
endmodule
| 7.58738 |
module SRD8CLE (
Q,
C,
CE,
CLR,
D,
L,
SLI
);
parameter WIDTH = 8;
output [WIDTH-1:0] Q;
input C, CE, CLR, L, SLI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE)
if (L) Q <= D;
el... | 7.507903 |
module SRD8CLED (
Q,
C,
CE,
CLR,
D,
L,
LEFT,
SLI,
SRI
);
parameter WIDTH = 8;
output [WIDTH-1:0] Q;
input C, CE, CLR, L, LEFT, SLI, SRI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C or posedge CLR) begin
if (CLR) Q <= 0;
else if (CE... | 6.651966 |
module SRD8RE (
Q,
C,
CE,
R,
SLI
);
parameter WIDTH = 8;
output [WIDTH-1:0] Q;
input C, CE, R, SLI;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE) Q <= {Q[WIDTH-2:0], SLI};
end
endmodule
| 7.739062 |
module SRD8RLE (
Q,
C,
CE,
D,
L,
R,
SLI
);
parameter WIDTH = 8;
output [WIDTH-1:0] Q;
input C, CE, L, R, SLI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE)
if (L) Q <= D;
else Q <= {Q[WIDTH-2:0]... | 7.598941 |
module SRD8RLED (
Q,
C,
CE,
D,
L,
LEFT,
R,
SLI,
SRI
);
parameter WIDTH = 8;
output [WIDTH-1:0] Q;
input C, CE, L, LEFT, R, SLI, SRI;
input [WIDTH-1:0] D;
reg [WIDTH-1:0] Q;
always @(posedge C or negedge C) begin
if (R) Q <= 0;
else if (CE)
if (L) Q <= D... | 6.532182 |
module nand8 (
input [7:0] i,
output o
);
assign o = !(&i);
endmodule
| 8.725348 |
module cpld_fourrom (
dip,
reset_b,
adr15,
adr14,
adr13,
ioreq_b,
mreq_b,
romen_b,
wr_b,
rd_b,
data,
romdis,
rom01cs_b,
rom23cs_b,
clk,
romoe_b,
skt01p27,
skt23p27,
roma14
);
input [7:0] dip;
input reset_b;
input adr15;
input adr14;
... | 6.833927 |
module cpld_model (
input aux_clk,
input start,
input mode,
input done,
output dout,
output reg sclk,
output detached
);
reg [ 7:0] rom [0:65535];
reg [15:0] addr;
reg [ 7:0] data;
assign dout = data[7];
reg [2:0] state, bitcnt;
localparam IDLE = 3'd0;
localparam READ = 3'... | 6.706177 |
module cpld_ram1m_plcc84 (
input rfsh_b,
input adr15_aux, // unused
input [15:0] adr,
input ioreq_b,
input mreq_b,
input reset_b,
input busreset_b,
input busack_b,
input wr_b, // now rnw on 6809
input rd_b,
... | 6.892982 |
module cpld_sixrom (
dip,
reset_b,
adr15,
adr14,
adr13,
ioreq_b,
mreq_b,
romen_b,
wr_b,
rd_b,
data,
romdis,
rom01cs_b,
rom23cs_b,
rom45cs_b,
clk,
romoe_b,
roma14,
busrq_b,
busack_b
);
input [7:0] dip;
input reset_b;
input adr15;
i... | 7.29908 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "S... | 7.493109 |
module AL_BUFKEEP (
i,
o
);
input i;
output o;
parameter KEEP = "OUT";
buf u1 (o, i);
endmodule
| 6.80915 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (... | 7.286889 |
module reg_ar_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.IN... | 7.572347 |
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