code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module AL_BUFKEEP (
i,
o
);
input i;
output o;
parameter KEEP = "OUT";
buf u1 (o, i);
endmodule
| 6.80915 |
module add_pu32_pu32_o32 (
i0,
i1,
o
);
input [31:0] i0;
input [31:0] i1;
output [31:0] o;
endmodule
| 6.598391 |
module reg_ar_as_w4 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [3:0] d;
input en;
input [3:0] reset;
input [3:0] set;
output [3:0] q;
endmodule
| 6.513638 |
module reg_ar_as_w24 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [23:0] d;
input en;
input [23:0] reset;
input [23:0] set;
output [23:0] q;
endmodule
| 6.927514 |
module add_pu25_mu25_o25 (
i0,
i1,
o
);
input [24:0] i0;
input [24:0] i1;
output [24:0] o;
endmodule
| 6.599963 |
module M3WithAHB // al_ip/M3WithAHB.v(14)
(
h2h_hrdata,
h2h_hreadyout,
h2h_hresp,
h2h_mclk,
h2h_rstn,
ppm_clk,
h2h_haddr,
h2h_hburst,
h2h_hprot,
h2h_hsize,
h2h_htrans,
h2h_hwdata,
h2h_hwrite
);
input [31:0] h2h_hrdata; // al_ip/M3WithAHB.v(35)
input h2h_hreadyo... | 6.563045 |
module reg_ar_as_w13 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [12:0] d;
input en;
input [12:0] reset;
input [12:0] set;
output [12:0] q;
endmodule
| 7.1302 |
module reg_ar_as_w33 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [32:0] d;
input en;
input [32:0] reset;
input [32:0] set;
output [32:0] q;
endmodule
| 6.547574 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "S... | 7.493109 |
module AL_BUFKEEP (
i,
o
);
input i;
output o;
parameter KEEP = "OUT";
buf u1 (o, i);
endmodule
| 6.80915 |
module reg_sr_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL... | 7.168682 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (... | 7.286889 |
module reg_ar_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.IN... | 7.572347 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module AL_FADD (
input a,
input b,
input c,
output sum,
output cout
);
wire prop;
wire not_prop;
wire sel_i0;
wire sel_i1;
xor u0 (prop, a, b);
xor u1 (sum, prop, c);
not u2 (not_prop, prop);
and u3 (sel_i1, prop, c);
and u4 (sel_i0, not_prop, a);
or u5 (cout, sel_i0, sel_i1... | 8.066381 |
module cpram_sclk_2w1r #(
parameter ADDR_WIDTH = 5,
parameter DATA_WIDTH = 32,
parameter CLEAR_ON_INIT = 1,
parameter ENABLE_BYPASS = 1
) (
clk,
rst,
we1,
waddr1,
wdata1,
we2,
waddr2,
wdata2,
re,
raddr,
rdata
);
/*
Ports
*/
input clk;
input rst;
inp... | 7.075294 |
module cprs_3_2 (
in,
out
);
input [2:0] in;
output [1:0] out;
assign in0_xor_in1 = in[0] ^ in[1];
assign in0_and_in1 = in[0] & in[1];
assign out[1] = in0_xor_in1 & in[2] | in0_and_in1;
assign out[0] = in0_xor_in1 ^ in[2];
endmodule
| 6.841716 |
module cprs_4_2 (
in,
out,
err
);
input [3:0] in;
output [1:0] out;
output err;
assign in0_and_in1 = in[0] & in[1];
assign in0_or_in1 = in[0] | in[1];
assign in0_xor_in1 = in[0] ^ in[1];
assign in2_or_in3 = in[2] | in[3];
assign in2_xor_in3 = in[2] ^ in[3];
assign out[0] = in0_xor_in1 ^... | 7.077964 |
module cprs_4_2_apx1 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
wire x1_xor_x2, x3_xor_x4, x1_and_x2, x3_and_x4;
assign x1_xor_x2 = x1 ^ x2;
assign x3_xor_x4 = x3 ^ x4;
assign x1_and_x2 = x1 & x2;
assign x3_and_x4 = x3 & x4;
assign ... | 7.110479 |
module cprs_4_2_apx2 (
input x1,
input x2,
input x3,
input x4,
output carry,
output sum,
output err
);
wire x1_xor_x2, x3_xor_x4, x1_and_x2, x3_and_x4;
assign x1_xor_x2 = x1 ^ x2;
assign x3_xor_x4 = x3 ^ x4;
assign x1_and_x2 = x1 & x2;
assign x3_and_x4 = x3 & x4;
assign e... | 7.233653 |
module cprs_4_2_apx3 (
input x1,
input x2,
input x3,
input x4,
output carry,
output sum,
output err
);
wire x1_xor_x2, x3_or_x4, x1_and_x2, x1_or_x2;
assign x1_xor_x2 = x1 ^ x2;
assign x1_and_x2 = x1 & x2;
assign x1_or_x2 = x1 | x2;
assign x3_or_x4 = x3 | x4;
assign err = ... | 6.885778 |
module cprs_4_2_fa (
input x1,
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output sum
);
wire s;
assign {cout, s} = x1 + x2 + x3;
assign {carry, sum} = cin + x4 + s;
endmodule
| 7.684253 |
module cprs_8_2 (
input [7:0] in,
input [4:0] yi,
output [1:0] out,
output [4:0] yo
);
cprs_4_2 I0 (
.in (in[7:4]),
.out({yo[0], I0_out}),
.err(I0_err)
);
cprs_4_2 I1 (
.in (in[3:0]),
.out({yo[1], I1_out}),
.err(I1_err)
);
cprs_3_2 I2 (
.in ({{I0_... | 6.871141 |
module cprs_8_2_top (
input clk,
input rst_n,
input [7:0] in0,
input [7:0] in1,
input [7:0] in2,
input [7:0] in3,
input [4:0] yi,
output reg [1:0] out0,
output reg [1:0] out1,
output reg [1:0] out2,
output reg [1:0] out3,
output [4:0] yo
);
reg [7:0] in0_r1, in1_r1, in... | 7.078999 |
module cprs_8_2 (
input [7:0] in,
input [4:0] yi,
output [1:0] out,
output [4:0] yo
);
wire I0_out, I1_out, I2_out, I3_out, I4_out;
wire I0_err, I1_err, I2_err, I3_err, I4_err;
cprs_4_2 I0 (
.in (in[7:4]),
.out({yo[0], I0_out}),
.err(I0_err)
);
cprs_4_2 I1 (
.in (in... | 6.871141 |
module cprs_3_2 (
in,
out
);
input [2:0] in;
output [1:0] out;
wire in0_xor_in1, in0_and_in1;
assign in0_xor_in1 = in[0] ^ in[1];
assign in0_and_in1 = in[0] & in[1];
assign out[1] = in0_xor_in1 & in[2] | in0_and_in1;
assign out[0] = in0_xor_in1 ^ in[2];
endmodule
| 6.841716 |
module cprs_4_2 (
in,
out,
err
);
input [3:0] in;
output [1:0] out;
output err;
wire in0_and_in1, in0_or_in1, in0_xor_in1;
assign in0_and_in1 = in[0] & in[1];
assign in0_or_in1 = in[0] | in[1];
assign in0_xor_in1 = in[0] ^ in[1];
wire in2_or_in3, in2_xor_in3;
assign in2_or_in3 = in[2]... | 7.077964 |
module cpstr_desc #(
parameter ESC_CHAR = 8'd27
) (
input i_clk,
input i_rst,
//
input [7:0] i_data,
input i_valid,
output o_ready,
//
output [7:0] o_data,
output o_valid,
input i_ready,
//
output [7:0] o_esc_data,
output o_esc_valid,
input i_esc_ready
);
w... | 6.854896 |
module CPT4 (
A,
B,
Y
);
input [3:0] A, B;
output Y;
xor i0 (D0, A[0], B[0]);
xor i1 (D1, A[1], B[1]);
xor i2 (D2, A[2], B[2]);
xor i3 (D3, A[3], B[3]);
nor i4 (Y, D0, D1, D2, D3);
endmodule
| 7.148151 |
module : determines the address of the next instruction
module pcBlock(clk,pcin,pcload,imm,pcsel,sbus,dbus,addrsel,address);
input clk,pcload,pcsel;
input [7:0] imm,sbus,dbus;
inout [7:0] pcin;
input [1:0] addrsel;
output [7:0] address;
wire [7:0] pcout;
reg [7:0] pcadd;
initial
... | 8.481357 |
module : determines the address of the next instruction
module pcBlock(clk,pcin,pcload,imm,pcsel,sbus,dbus,addrsel,address);
input clk,pcload,pcsel;
input [7:0] imm,sbus,dbus;
inout [7:0] pcin;
input [1:0] addrsel;
output [7:0] address;
wire [7:0] pcout;
wire [7:0] pcadd;
... | 8.481357 |
module irLoad (
input [1:0] phase,
output irload
);
assign irload = (phase == 2'b00) ? 1 : 0;
endmodule
| 7.11438 |
module imLoad (
input [1:0] phase,
input irbit7,
output imload
);
assign imload = (phase == 2'b01) ? irbit7 : 0;
endmodule
| 6.733351 |
module readWrite (
irbit4,
irbit5,
irbit6,
phase,
readwrite
);
input irbit4, irbit5, irbit6, irbit7;
input [1:0] phase;
output readwrite;
assign readwrite = (phase == 2'b10) ? (irbit4 & ~irbit5 & irbit6) : 0;
endmodule
| 6.670079 |
module regSel (
op1op2,
phase,
regsel
);
input [3:0] op1op2;
input [1:0] phase;
output reg [1:0] regsel;
reg [1:0] mux1out;
always @(op1op2) begin
case (op1op2)
4'b0000, 4'b0001, 4'b0010, 4'b0011: mux1out <= 2'b11;
4'b0100, 4'b110: mux1out <= 2'b10;
4'b0110... | 6.694468 |
module destRegWrite (
op1op2,
phase,
dwrite
);
input [3:0] op1op2;
input [1:0] phase;
output dwrite;
wire [1:0] mux1out;
assign mux1out = (op1op2 == 4'b0101 | 4'b0111 | 4'b1000 | 4'b1001 | 4'b1010 | 4'b1011 | 4'b1101 | 4'b1111)?0:1 ;
assign dwrite = (phase == 2'b10) ? mux1out : 0;
endmodule
| 7.039863 |
module addressSelect (
op1op2,
phase,
addrsel
);
input [3:0] op1op2;
input [1:0] phase;
output [1:0] addrsel;
wire [1:0] mux1out;
assign mux1out = (op1op2 == 4'b1101 | 4'b1110)?(2'b01):((op1op2==4'b0100 | 4'b0101)?2'b10:0);
assign addrsel = (phase == 2'b10) ? mux1out : 2'b00;
endmodule
| 6.709912 |
module registerFile (
input [7:0] dval,
input dwrite,
input [1:0] dregsel,
input [1:0] sregsel,
input clk,
output reg zero,
output reg negative,
output [7:0] dbus,
output [7:0] sbus
);
wire [3:0] res_enable;
wire [7:0] res0, res1, res2, res3;
demux_1x4 demux1 (
dwrite,
... | 6.674499 |
module mux_4x1 (
input [7:0] I0,
I1,
I2,
I3,
input [1:0] sel,
output [7:0] out
);
assign out = (sel[1] == 0) ? ((sel[0] == 0) ? I0 : I1) : ((sel[0] == 0) ? I2 : I3);
endmodule
| 8.288733 |
module demux_1x4 (
input I0,
input [1:0] sel,
output o0,
o1,
o2,
o3
);
assign o0 = (sel[1] == 0) ? ((sel[0] == 0) ? I0 : 0) : ((sel[0] == 0) ? 0 : 0);
assign o1 = (sel[1] == 0) ? ((sel[0] == 0) ? 0 : I0) : ((sel[0] == 0) ? 0 : 0);
assign o2 = (sel[1] == 0) ? ((sel[0] == 0) ? 0 : 0) : ((se... | 6.751033 |
module
module register8(
input clk,
input [7:0]data_in,
input enable,
output reg [7:0]data_out
);
always @(posedge clk & enable)
begin
data_out <= data_in;
end
initial
data_out <= 8'b00000000;
endmodule
| 7.37291 |
module
//Module that stores instruction to be executed
module ram (data,addr,we, clk,q);
input [7:0] data, addr;
input we, clk;
output reg [7:0] q;
// Declare the RAM variable
reg [7:0] ram[255:0];
// Variable to hold the registered read address
reg [7:0] addr_reg;
initial
begin
//Write your progra... | 6.613159 |
module bit_8_AND (
aANDb,
A,
B
);
output [7:0] aANDb;
input [7:0] A, B;
assign aANDb = A & B;
endmodule
| 7.483326 |
module bit_8_OR (
aORb,
A,
B
);
output [7:0] aORb;
input [7:0] A;
input [7:0] B;
assign aORb = A | B;
endmodule
| 7.095413 |
module half_adder (
sum,
carry,
A,
B
);
output sum, carry;
input A, B;
assign sum = A & (~B) | (~A) & B;
assign carry = A & B;
endmodule
| 6.966406 |
module bit_8_ADDER (
out,
A,
B,
carry_in
);
output [7:0] out;
input [7:0] A;
input [7:0] B;
input carry_in;
wire carry[6:0];
full_adder add0 (
out[0],
carry[0],
A[0],
B[0] ^ carry_in,
carry_in
);
full_adder add1 (
out[1],
carry[1],
A[1],
... | 6.880326 |
module mux_2X1 (
output [7:0] O,
input [7:0] I0,
input [7:0] I1,
input sel
);
assign O = (sel == 0) ? I0 : I1;
endmodule
| 8.024585 |
module
module bit_8_ALU(
input [7:0]in_A,
input [7:0]in_B,
input [1:0]in_operation,
output [7:0]out_c
);
wire [7:0]out_and,out_or,out_adder,mux1;
bit_8_AND i1(out_and,in_A,in_B);
bit_8_OR i2(out_or,in_A,in_B);
bit_8_ADDER i3(out_adder,in_A,in_B,in_operation[0]);
mux_2X1 i4(mux1,out_and,out_or,in_operatio... | 7.788587 |
module instructionFetcher (
clock,
switches,
state
);
input [7:0] switches;
input clock, state;
output reg [16:0] instruction;
always @(posedge clock) begin
case (state)
0: begin //set opcode for instruction
end
1: begin //set regid1 for instruction
end
2: b... | 6.694181 |
module instructionMemory (
clock,
instruction,
instructionMem,
instructionDone,
state
);
input clock;
input [2:0] state;
input [16:0] instruction;
input instructionDone;
integer i = 0;
output reg [9:0] instructionMem;
always @(posedge instructionDone) begin
instructionMem[i] <= i... | 8.458827 |
module cpu_riscv_min_sopc (
input wire clk,
input wire rst
);
// connect inst_rom
wire [`InstAddrBus] rom_addr;
wire [127:0] rom_data;
wire rom_done;
wire rom_read;
// connect data_ram
wire ram_we;
wire [`RegBus] ram_addr;
wire [`RegBus] ram_data_i;
wire [`RegBus] ram_data_o;
wire [3:0]... | 6.859296 |
module cpu_riscv_min_sopc_tb ();
reg CLOCK_50;
reg rst;
// 100MHz
initial begin
CLOCK_50 = 1'b0;
forever #5 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst = `RstDisable;
#100000 $stop;
end
cpu_riscv_min_sopc cpu_riscv_min_sopc0 (
.clk(CLOCK_50),
.r... | 6.859296 |
module CPU_Test ();
wire [63:0] mux2pc;
wire [63:0] pc2out;
wire [63:0] add2mux_1;
wire [31:0] insMem2out;
wire con2mux_1;
wire con2and;
wire con2mem_1;
wire con2mux_2;
wire con2ALUcon_1;
wire con2ALUcon_2;
wire con2mem_2;
wire con2mux_3;
wire con2reg;
wire [4:0] mux2reg_1;
wire [63... | 7.62873 |
module CPU_Test_Piped ();
wire [63:0] mux2pc;
wire [63:0] pc2out;
wire [63:0] add2mux_1;
wire [31:0] insMem2out;
wire con2mux_1;
wire con2and;
wire con2mem_1;
wire con2mux_2;
wire con2ALUcon_1;
wire con2ALUcon_2;
wire con2mem_2;
wire con2mux_3;
wire con2reg;
wire [4:0] mux2reg_1;
wi... | 7.092137 |
module cpu
//-------------------------------------------------------------------------------------------------
(
input wire clock,
input wire pe,
input wire ne,
input wire reset,
output wire rfsh,
output wire mreq,
output wire iorq,
in... | 6.55777 |
module cpu (
input clock,
reset,
output [0:7] segPc1,
output [0:7] segPc0,
output [0:7] segTick,
output [0:7] segAlu1,
output [0:7] segAlu0,
input CLOCK_50, // 50 MHz clock
//LCD Module 16X2
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
... | 6.869387 |
module cpu0m (
input clock,
reset,
output reg [15:0] pc,
output reg [2:0] tick,
output reg [15:0] ir,
output reg [15:0] mar,
output reg [15:0] mdr,
inout [15:0] dbus,
output reg m_en,
m_rw,
output reg signed [15:0] aluOut
);
reg [4:0] op;
reg [10:0] rb;
reg signed [10:0... | 6.924209 |
module Seg7 (
input [3:0] num,
output [0:7] seg
);
reg [7:0] nseg;
always @(num) begin
case (num)
4'b0000: nseg = 8'b11111100; // 0
4'b0001: nseg = 8'b01100000; // 1
4'b0010: nseg = 8'b11011010; // 2
4'b0011: nseg = 8'b11110010; // 3
4'b0100: nseg = 8'b01100110; // 4
... | 6.771186 |
module Reset_Delay (
iCLK,
oRESET
);
input iCLK;
output reg oRESET;
reg [19:0] Cont;
always @(posedge iCLK) begin
if (Cont != 20'hFFFFF) begin
Cont <= Cont + 1'b1;
oRESET <= 1'b0;
end else oRESET <= 1'b1;
end
endmodule
| 6.570866 |
module LCD_display_string (
index,
out,
hex0
);
input [4:0] index;
input [7:0] hex0;
output [7:0] out;
reg [7:0] out;
// ASCII hex values for LCD Display
// Enter Live Hex Data Values from hardware here
// LCD DISPLAYS THE FOLLOWING:
//----------------------------
//| Count=XX ... | 8.592639 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
.clock(clock),
.reset(reset),
.pc(pc),
.tick(tick),
.ir(ir),
.mar(mar),
.mdr(mdr),
.dbus(... | 6.659372 |
module cpu (
input clock,
reset,
output reg [2:0] tick,
output reg [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output reg m_en,
m_rw
);
`define PC R[15]
parameter [7:0] LD = 8'h00, ST = 8'h01, ADD = 8'h13, JMP = 8'h26;
reg signed [31:0] R[0:15];
reg [7:0] op;
reg [3:0] ... | 6.869387 |
module cpu (
input clock,
reset,
output [31:0] abus,
input [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b, alu_out, r_d1, r_d2, r_wd;
wire [31:0] ir, mar, mdr;
wire [3:0] alu_op, r_a1, r_a2, r_wa;
wire r_w;
alu alu0 (
alu_a,
alu_b,
alu_op,
al... | 6.869387 |
module computer (
input clock,
reset
);
wire [2:0] tick;
wire [31:0] mar, mdr;
wire m_en, m_rw;
cpu cpu0 (
clock,
reset,
mar,
mdr,
m_en,
m_rw
);
memory mem0 (
clock,
reset,
m_en,
m_rw,
mar,
mdr
);
endmodule
| 6.659372 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
.clock(clock),
.reset(reset),
.pc(pc),
.tick(tick),
.ir(ir),
.mar(mar),
.mdr(mdr),
.dbus(... | 6.659372 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
.clock(clock),
.reset(reset),
.pc(pc),
.tick(tick),
.ir(ir),
.mar(mar),
.mdr(mdr),
.dbus(... | 6.659372 |
module cpu (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
reg signed [31:0] R[0:15], alu_a, alu_b;
wire signed [31:0] alu_out;
reg [31:0] ir, pc, mar, mdr;
reg [3:0] alu_op;
alu alu0 (
alu_a,
... | 6.869387 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
.clock(clock),
.reset(reset),
.pc(pc),
.tick(tick),
.ir(ir),
.mar(mar),
.mdr(mdr),
.dbus(... | 6.659372 |
module cpu (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
reg signed [31:0] alu_a, alu_b;
wire signed [31:0] alu_out;
reg [31:0] ir, pc, mar, mdr;
reg [3:0] alu_op;
wire [3:0] r_a1, r_a2, r_wa;
wire si... | 6.869387 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
.clock(clock),
.reset(reset),
.pc(pc),
.tick(tick),
.ir(ir),
.mar(mar),
.mdr(mdr),
.dbus(... | 6.659372 |
module cpu (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b;
wire signed [31:0] alu_out;
reg [31:0] ir, pc, mar, mdr;
wire [3:0] alu_op;
wire [3:0] r_a1, r_a2, r_wa;
wire ... | 6.869387 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
clock,
reset,
tick,
pc,
ir,
mar,
mdr,
dbus,
m_en,
m_rw
);
memory mem0 (
... | 6.659372 |
module cpu (
input clock,
reset,
output [2:0] tick,
output [31:0] pc,
ir,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b;
wire signed [31:0] alu_out;
reg [31:0] ir, mar, mdr;
wire [3:0] alu_op;
wire [3:0] r_a1, r_a2, r_wa;
wire signe... | 6.869387 |
module cpu (
input clock,
reset,
output [2:0] tick,
output [31:0] mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b, alu_out;
reg [31:0] ir, mar, mdr;
wire [3:0] alu_op, r_a1, r_a2, r_wa;
wire signed [31:0] r_d1, r_d2, r_wd;
wire r_wen;
alu al... | 6.869387 |
module computer (
input clock,
reset
);
cpu cpu0 (
clock,
reset,
mar,
mdr,
dbus,
m_en,
m_rw
);
memory mem0 (
clock,
reset,
m_en,
m_rw,
mar,
mdr,
dbus
);
endmodule
| 6.659372 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
clock,
reset,
tick,
pc,
ir,
mar,
mdr,
m_en,
m_rw
);
memory mem0 (
clock,
... | 6.659372 |
module cpu (
input clock,
reset,
output [2:0] tick,
output [31:0] pc,
ir,
mar,
input [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b;
wire signed [31:0] alu_out;
reg [31:0] ir, mar, mdr;
wire [3:0] alu_op;
wire [3:0] r_a1, r_a2, r_wa;
wire signed [31:0] ... | 6.869387 |
module cpu (
input clock,
reset,
output [31:0] abus,
input [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b;
wire signed [31:0] alu_out;
reg [31:0] ir, mar, mdr;
wire [3:0] alu_op, r_a1, r_a2, r_wa;
wire [2:0] tick;
wire signed [31:0] r_d1, r_d2, r_wd;
wire r_wen;
... | 6.869387 |
module computer (
input clock,
reset
);
wire [2:0] tick;
wire [31:0] ir, pc, mar, mdr;
wire m_en, m_rw;
cpu cpu0 (
clock,
reset,
mar,
mdr,
m_en,
m_rw
);
memory mem0 (
clock,
reset,
m_en,
m_rw,
mar,
mdr
);
endmodule
| 6.659372 |
module cpu (
input clock,
reset,
output [31:0] abus,
input [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b;
wire signed [31:0] alu_out;
reg [31:0] ir, mar, mdr;
wire [3:0] alu_op, r_a1, r_a2, r_wa;
wire [2:0] tick;
wire signed [31:0] r_d1, r_d2, r_wd;
wire r_wen;
... | 6.869387 |
module computer (
input clock,
reset
);
wire [2:0] tick;
wire [31:0] ir, pc, mar, mdr;
wire m_en, m_rw;
cpu cpu0 (
clock,
reset,
mar,
mdr,
m_en,
m_rw
);
memory mem0 (
clock,
reset,
m_en,
m_rw,
mar,
mdr
);
endmodule
| 6.659372 |
module cpu (
input clock,
reset,
output [31:0] abus,
input [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b, alu_out, r_d1, r_d2, r_wd;
reg [31:0] ir, mar, mdr;
wire [3:0] alu_op, r_a1, r_a2, r_wa;
wire r_w;
alu alu0 (
alu_a,
alu_b,
alu_op,
alu... | 6.869387 |
module computer (
input clock,
reset
);
wire [2:0] tick;
wire [31:0] mar, mdr;
wire m_en, m_rw;
cpu cpu0 (
clock,
reset,
mar,
mdr,
m_en,
m_rw
);
memory mem0 (
clock,
reset,
m_en,
m_rw,
mar,
mdr
);
endmodule
| 6.659372 |
module cpu (
input clock,
reset,
output [31:0] abus,
input [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b, alu_out, r_d1, r_d2, r_wd;
reg [31:0] ir, mar, mdr;
wire [3:0] alu_op, r_a1, r_a2, r_wa;
wire r_w;
alu alu0 (
alu_a,
alu_b,
alu_op,
alu... | 6.869387 |
module computer (
input clock,
reset
);
wire [2:0] tick;
wire [31:0] mar, mdr;
wire m_en, m_rw;
cpu cpu0 (
clock,
reset,
mar,
mdr,
m_en,
m_rw
);
memory mem0 (
clock,
reset,
m_en,
m_rw,
mar,
mdr
);
endmodule
| 6.659372 |
module cpu (
input clock,
reset,
output [31:0] abus,
input [31:0] dbus,
output m_en,
m_rw
);
wire signed [31:0] alu_a, alu_b, alu_out, r_d1, r_d2, r_wd;
wire [31:0] ir, mar, mdr;
wire [3:0] alu_op, r_a1, r_a2, r_wa;
wire r_w;
alu alu0 (
alu_a,
alu_b,
alu_op,
al... | 6.869387 |
module computer (
input clock,
reset
);
wire [2:0] tick;
wire [31:0] mar, mdr;
wire m_en, m_rw;
cpu cpu0 (
clock,
reset,
mar,
mdr,
m_en,
m_rw
);
memory mem0 (
clock,
reset,
m_en,
m_rw,
mar,
mdr
);
endmodule
| 6.659372 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
clock,
reset,
tick,
pc,
ir,
mar,
mdr,
m_en,
m_rw
);
memory mem0 (
clock,
... | 6.659372 |
module cpu (
input clock,
reset,
output [2:0] tick,
output [31:0] pc,
ir,
mar,
input [31:0] dbus,
output m_en,
m_rw
);
wire [31:0] alu_a, alu_b;
wire [31:0] alu_out;
reg [31:0] ir, mar, mdr;
wire [3:0] alu_op;
wire [3:0] r_a1, r_a2;
wire [31:0] r_d1, r_d2;
wire r_w2;
... | 6.869387 |
module cpu0mc (
input clock
); // CPU0-Mini ֨Gcpu0mc Ҳ
parameter [7:0] LD = 8'h00, ST = 8'h01, ADD = 8'h13, JMP = 8'h26; // 䴩 4 ӫO
reg signed [31:0] R [ 0:15]; // ŧiȦs R[0..15] 16 32 줸Ȧs
reg signed [31:0] IR; // OȦs IR
reg [ 7:0] m [0:128]; // ֨O
reg ... | 6.501212 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
.clock(clock),
.reset(reset),
.pc(pc),
.tick(tick),
.ir(ir),
.mar(mar),
.mdr(mdr),
.dbus(... | 6.659372 |
module Pipe_Reg (
input clock,
reset,
zero,
stall,
input [size-1:0] data_i,
output reg [size-1:0] data_o
);
parameter size = 0;
always @(posedge clk_i) begin
if (~reset) data_o <= 0;
else if (zero == 1) data_o <= 0;
else if (stall == 1) data_o <= data_o;
else data_o <= data_i... | 7.806836 |
module computer (
input clock,
reset,
output [2:0] tick,
output [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output m_en,
m_rw
);
cpu cpu0 (
.clock(clock),
.reset(reset),
.pc(pc),
.tick(tick),
.ir(ir),
.mar(mar),
.mdr(mdr),
.dbus(... | 6.659372 |
module cpu (
input clock,
reset,
output reg [2:0] tick,
output reg [31:0] ir,
pc,
mar,
mdr,
inout [31:0] dbus,
output reg m_en,
m_rw
);
`define PC R[15]
parameter [7:0] LD = 8'h00, ST = 8'h01, ADD = 8'h13, JMP = 8'h26;
reg signed [31:0] R[0:15];
reg [7:0] op;
reg [3:0] ... | 6.869387 |
module computer (
input clock,
reset
);
wire [2:0] tick;
wire [31:0] mar, mdr;
wire m_en, m_rw;
cpu cpu0 (
clock,
reset,
mar,
mdr,
m_en,
m_rw
);
memory m (
clock,
reset,
m_en,
m_rw,
mar,
mdr
);
endmodule
| 6.659372 |
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