code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module decode (
input [31:0] ir,
output [ 7:0] op,
output [ 3:0] ra,
rb,
rc,
output [11:0] cx12
);
assign op = ir[31:24];
assign ra = ir[23:20];
assign rb = ir[19:16];
assign rc = ir[15:12];
assign cx12 = $signed(ir[11:0]);
endmodule
| 7.887076 |
module control (
input [31:0] pc,
input [7:0] op,
input [3:0] ra,
rb,
rc,
input [11:0] cx12,
input [15:0] cx16,
input [23:0] cx24,
output reg [3:0] alu_op,
output reg reg_w,
output reg mem_rw,
mem_en
);
parameter [7:0] LD = 8'h00, ST = 8'h01, ADD = 8'h13, JMP = 8'h26;
... | 7.715617 |
module cpu (
input clock,
reset,
output [31:0] abus,
input [31:0] dbus,
output m_en,
m_rw
);
wire [31:0] pc_i, pc_o, pcadd4, rb_data1, rb_data2, rb_wdata;
reg [31:0] ir, mar, mdr;
wire [7:0] op;
wire [3:0] ra, rb, rc, alu_op, rb_src1, rb_src2, rb_dst;
wire [11:0] cx12;
wire [15:0] cx... | 6.869387 |
module register (
input clock,
reset,
w_en,
input [31:0] ri,
output reg [31:0] ro
);
always @(posedge clock) begin
if (reset == 1) ro <= 0;
else if (w_en == 1) ro <= ri;
else ro <= ro;
end
endmodule
| 6.542519 |
module computer (
input clock,
reset
);
wire [2:0] tick;
wire [31:0] mar, mdr;
wire m_en, m_rw;
cpu cpu0 (
clock,
reset,
mar,
mdr,
m_en,
m_rw
);
memory m (
clock,
reset,
m_en,
m_rw,
mar,
mdr
);
endmodule
| 6.659372 |
module decode (
input [31:0] ir,
output [ 7:0] op,
output [ 3:0] ra,
rb,
rc,
output [11:0] cx12
);
assign op = ir[31:24];
assign ra = ir[23:20];
assign rb = ir[19:16];
assign rc = ir[15:12];
assign cx12 = $signed(ir[11:0]);
endmodule
| 7.887076 |
module control (
input [31:0] pc,
input [7:0] op,
input [3:0] ra,
rb,
rc,
input [11:0] cx12,
input [15:0] cx16,
input [23:0] cx24,
output reg [3:0] alu_op,
output reg reg_w,
output reg mem_rw,
mem_en
);
parameter [7:0] LD = 8'h00, ST = 8'h01, ADD = 8'h13, JMP = 8'h26;
... | 7.715617 |
module cpu (
input clock,
reset,
output [31:0] abus,
input [31:0] dbus,
output m_en,
m_rw
);
wire [31:0] pc_i, pc_o, pcadd4, rb_data1, rb_data2, rb_wdata;
reg [31:0] ir, mar, mdr;
wire [7:0] op;
wire [3:0] ra, rb, rc, alu_op, rb_src1, rb_src2, rb_dst;
wire [11:0] cx12;
wire [15:0] cx... | 6.869387 |
module register (
input clock,
reset,
w_en,
input [31:0] ri,
output reg [31:0] ro
);
always @(posedge clock) begin
if (reset == 1) ro <= 0;
else if (w_en == 1) ro <= ri;
else ro <= ro;
end
endmodule
| 6.542519 |
module computer (
input clock,
reset
);
wire [2:0] tick;
wire [31:0] mar, mdr;
wire m_en, m_rw;
cpu cpu0 (
clock,
reset,
mar,
mdr,
m_en,
m_rw
);
memory m (
clock,
reset,
m_en,
m_rw,
mar,
mdr
);
endmodule
| 6.659372 |
module decode (
input [31:0] ir,
output [ 7:0] op,
output [ 3:0] ra,
rb,
rc,
output [11:0] cx12,
output [15:0] cx16,
output [23:0] cx24
);
assign op = ir[31:24];
assign ra = ir[23:20];
assign rb = ir[19:16];
assign rc = ir[15:12];
assign cx12 = ir[11:0];
assign cx16 ... | 7.887076 |
module control (
input [31:0] pc,
input [7:0] op,
input [3:0] ra,
rb,
rc,
input [11:0] cx12,
input [15:0] cx16,
input [23:0] cx24,
output reg [3:0] alu_op,
output reg reg_w,
output reg mem_rw,
mem_en
);
parameter [7:0] LD = 8'h00, ST = 8'h01, ADD = 8'h13, JMP = 8'h26;
... | 7.715617 |
module cpu (
input clock,
reset,
output [31:0] abus,
input [31:0] dbus,
output m_en,
m_rw
);
wire [31:0] pc_i, pc_o, pcadd4, rb_data1, rb_data2, rb_wdata;
reg [31:0] ir, mar, mdr;
wire [7:0] op;
wire [3:0] ra, rb, rc, alu_op, rb_src1, rb_src2, rb_dst;
wire [11:0] cx12;
wire [15:0] cx... | 6.869387 |
module register (
input clock,
reset,
w_en,
input [31:0] ri,
output reg [31:0] ro
);
always @(posedge clock) begin
if (reset == 1) ro <= 0;
else if (w_en == 1) ro <= ri;
else ro <= ro;
end
endmodule
| 6.542519 |
module yAlu (
z,
ex,
a,
b,
op
);
input [31:0] a, b;
input [2:0] op;
output [31:0] z;
output ex;
wire [31:0] andi, ori, arith, sub, slt;
wire condition;
wire [15:0] z16;
wire [7:0] z8;
wire [3:0] z4;
wire [1:0] z2;
wire z1;
assign slt[31:1] = 0;
//and------------------------... | 7.488274 |
module yMux1 (
z,
a,
b,
c
);
output z;
input a, b, c;
wire notC, upper, lower;
not my_not (notC, c);
and upperAnd (upper, a, notC);
and lowerAnd (lower, c, b);
or my_or (z, upper, lower);
endmodule
| 7.817008 |
module yMux (
z,
a,
b,
c
);
parameter SIZE = 2;
output [SIZE-1:0] z;
input [SIZE-1:0] a, b;
input c;
yMux1 mine[SIZE-1:0] (
z,
a,
b,
c
);
endmodule
| 7.089728 |
module yMux4to1(z,a0,a1,a2,a3, c);
parameter SIZE = 2;
output [SIZE-1:0] z;
input [SIZE-1:0] a0, a1, a2, a3;
input [1:0] c;
wire [SIZE-1:0] zLo, zHi;
yMux #(SIZE) lo(zLo, a0, a1, c[0]);
yMux #(SIZE) hi(zHi, a2, a3, c[0]);
yMux #(SIZE) final(z, zLo, zHi, c[1]);
endmodule
| 7.205232 |
module yAdder1 (
z,
cout,
a,
b,
cin
);
output z, cout;
input a, b, cin;
xor left_xor (tmp, a, b);
xor right_xor (z, cin, tmp);
and left_and (outL, a, b);
and right_and (outR, tmp, cin);
or my_or (cout, outR, outL);
endmodule
| 7.597836 |
module yAdder (
z,
cout,
a,
b,
cin
);
output [31:0] z;
output cout;
input [31:0] a, b;
input cin;
wire [31:0] in, out;
yAdder1 mine[31:0] (
z,
out,
a,
b,
in
);
assign in[0] = cin;
assign in[31:1] = out[30:0];
assign cout = out[31];
endmodule
| 8.270882 |
module yArith (
z,
cout,
a,
b,
ctrl
);
//add if ctrl=0, subtract if ctrl=1
output [31:0] z;
output cout;
input [31:0] a, b;
input ctrl;
wire [31:0] notB, tmp;
wire cin;
assign cin = ctrl;
not myNot[31:0] (notB, b);
yMux #(32) mymux (
tmp,
b,
notB,
cin
)... | 8.409021 |
module yEX (
z,
zero,
rd1,
rd2,
imm,
op,
ALUSrc
);
output [31:0] z;
output zero;
input [31:0] rd1, rd2, imm;
input [2:0] op;
input ALUSrc;
wire [31:0] b, a;
wire ex;
yMux #(32) mux_two (
b,
rd2,
imm,
ALUSrc
);
yAlu myAlu (
z,
zero,
... | 7.939177 |
module yIF (
ins,
PCp4,
PCin,
clk
);
output [31:0] ins, PC, PCp4;
input [31:0] PCin;
input clk;
wire zero;
wire read, write, enable;
wire [31:0] a, memIn;
wire [2:0] op;
register #(32) pcReg (
PC,
PCin,
clk,
enable
);
mem insMem (
ins,
PC,
m... | 7.667078 |
module yDM (
memOut,
exeOut,
rd2,
clk,
MemRead,
MemWrite
);
output [31:0] memOut;
input [31:0] exeOut, rd2;
input clk, MemRead, MemWrite;
mem DM (
memOut,
exeOut,
rd2,
clk,
MemRead,
MemWrite
);
endmodule
| 6.9123 |
module yWB (
wb,
exeOut,
memOut,
Mem2Reg
);
output [31:0] wb;
input [31:0] exeOut, memOut;
input Mem2Reg;
yMux #(32) WB (
wb,
exeOut,
memOut,
Mem2Reg
);
endmodule
| 7.055108 |
module yPC (
PCin,
PCp4,
INT,
entryPoint,
imm,
jTarget,
zero,
branch,
jump
);
output [31:0] PCin;
input [31:0] PCp4, entryPoint, imm;
input [25:0] jTarget;
input INT, zero, branch, jump;
wire [31:0] immX4, bTarget, jTargetX4, choiceA, choiceB;
wire doBranch, zf;
assign ... | 9.239454 |
module yC1 (
rtype,
lw,
sw,
jump,
branch,
opCode
);
output rtype, lw, sw, jump, branch;
input [5:0] opCode;
wire [0:0] not5, not4, not3, not2, not1, not0;
not (not5, opCode[5]);
not (not4, opCode[4]);
not (not3, opCode[3]);
not (not2, opCode[2]);
not (not1, opCode[1]);
not (not... | 6.842966 |
module yC2 (
RegDst,
ALUSrc,
RegWrite,
Mem2Reg,
MemRead,
MemWrite,
rtype,
lw,
sw,
branch
);
output RegDst, ALUSrc, RegWrite, Mem2Reg, MemRead, MemWrite;
input rtype, lw, sw, branch;
assign RegDst = rtype; //use [rd] field
nor (ALUSrc, rtype, branch); //0 - do calculatio... | 7.453007 |
module yC4 (
op,
ALUop,
fnCode
);
output [2:0] op;
input [5:0] fnCode;
input [1:0] ALUop;
wire y1, y2;
or (y1, fnCode[0], fnCode[3]);
and (y2, fnCode[1], ALUop[1]);
and (op[0], ALUop[1], y1);
nand (op[1], ALUop[1], fnCode[2]);
or (op[2], y2, ALUop[0]);
endmodule
| 6.67076 |
module yChip (
ins,
rd2,
wb,
entryPoint,
INT,
clk
);
output [31:0] ins, rd2, wb;
input [31:0] entryPoint;
input INT, clk;
wire [31:0] wd, rd1, rd2, imm, ins, PCp4, z, memOut, wb, PCin;
wire [25:0] jTarget;
wire [5:0] opCode, fnCode;
wire [2:0] op;
wire [1:0] ALUop;
wire zero, R... | 6.824448 |
module CPU16 (
input reset,
input clk,
input cen,
input SYNC,
input VB,
input RW,
input [15:0] ABI, // from CPU
output reg [15:0] ABO, // to PCB
input [ 7:0] CPU_DBI, // from CPU
output r... | 7.079045 |
module cpu (
input clock
); // CPU0-Mini 的快取版：cpu0mc 模組
parameter [3:0] LD = 4'h0, ADD = 4'h1, JMP = 4'h2, ST = 4'h3, CMP = 4'h4, JEQ = 4'h5;
reg signed [15:0] A; // 宣告暫存器 R[0..15] 等 16 個 32 位元暫存器
reg [15:0] IR; // 指令暫存器 IR
reg [15:0] SW; // 指令暫存器 IR
reg [15:0] PC; // 程式計數器
reg [15:0] pc0;
reg [7... | 6.869387 |
module alu (
DATA1,
DATA2,
RESULT,
SELECT,
ZERO,
ShiftOp
);
//declaration for inputs and output
input [7:0] DATA1;
input signed [7:0] DATA2;
input [2:0] SELECT;
input [1:0] ShiftOp;
output reg signed [7:0] RESULT;
output reg ZERO;
//declaration of wires that hold vlues of each ... | 6.675659 |
module
module FORWARD(DATA, OUT);
//declare input and output
input [7:0] DATA;
output [7:0] OUT;
assign #1 OUT = DATA;
endmodule
| 7.301976 |
module for addition
module ADD(DATA1, DATA2, OUT);
//declare inputs and output
input [7:0] DATA1;
input [7:0] DATA2;
output [7:0] OUT;
assign #2 OUT = DATA1 + DATA2;
endmodule
| 8.677164 |
module for and operation
module AND(DATA1, DATA2, OUT);
//declare inputs and output
input [7:0] DATA1;
input [7:0] DATA2;
output [7:0] OUT;
assign #1 OUT = DATA1 & DATA2;
endmodule
| 8.26136 |
module for or operation
module OR(DATA1, DATA2, OUT);
//declare inputs and output
input [7:0] DATA1;
input [7:0] DATA2;
output [7:0] OUT;
assign #1 OUT = DATA1 | DATA2;
endmodule
| 8.181301 |
module for 2's compliment
module twosCompliment(DATA, OUT);
//declare input and output
input [7:0] DATA;
output [7:0] OUT;
assign #1 OUT = ~DATA + 1;
endmodule
| 7.35975 |
module SHIFT (
DATA,
ShiftValue,
OUT,
shiftOP
);
input [7:0] DATA, ShiftValue;
output reg [7:0] OUT;
input [1:0] shiftOP;
always @(*) begin
#1
case (shiftOP)
2'b00: begin //logical right shift
case (ShiftValue)
8'd0: OUT = DATA;
8'd1: OUT = {{1{1'b0}},... | 7.612946 |
module MULTIPLY (
DATA1,
DATA2,
OUT
);
input [7:0] DATA1, DATA2;
output [7:0] OUT;
wire [7:0] p0, p1, p2, p3, p4, p5, p6, p7;
assign p0 = (DATA2[0] == 1) ? {DATA1} : 8'd0;
assign p1 = (DATA2[1] == 1) ? {DATA1, 1'd0} : 8'd0;
assign p2 = (DATA2[2] == 1) ? {DATA1, 2'd0} : 8'd0;
assign p3 = (DATA... | 7.226664 |
module
module and_gate(IN1, IN2, OUT);
input IN1, IN2;
output OUT;
and(OUT, IN1, IN2);
endmodule
| 7.543031 |
module
module or_gate(IN1, IN2, OUT);
input IN1, IN2;
output OUT;
or(OUT, IN1, IN2);
endmodule
| 7.595382 |
module branch_adder (
pcNext,
offset,
out
);
input [31:0] pcNext, offset;
output [31:0] out;
assign #2 out = pcNext + offset;
endmodule
| 7.088339 |
module for find next pc value
module pc_adder(IN, OUT);
input [31:0] IN; // input address/ current instruction
output [31:0] OUT; // output address/ next instruction
assign #1 OUT = IN + 32'd4;
endmodule
| 8.088831 |
module find_offset (
IN,
OUT
);
input [7:0] IN;
output [31:0] OUT;
assign OUT = {{24{IN[7]}}, IN[5:0], {2{1'b0}}}; // sign extended and shifted
endmodule
| 6.756672 |
module selectMUX (
IN1,
IN2,
OUT,
SELECT
);
input [7:0] IN1, IN2;
input SELECT;
output reg [7:0] OUT;
always @(*) begin
case (SELECT)
1'b1: OUT <= IN1;
1'b0: OUT <= IN2;
endcase
end
endmodule
| 7.086848 |
module for select right pc value
module PCmux(IN1, IN2, OUT, SELECT);
input [31:0] IN1, IN2;
input SELECT;
output reg [31:0] OUT;
always@(*) begin
case(SELECT)
1'b1: OUT <= IN1;
1'b0: OUT <= IN2;
endcase
end
endmodule
| 7.643532 |
module CPU (
clock,
WriteData,
InstrReg
);
input clock;
output [15:0] WriteData, InstrReg;
reg [15:0] PC;
reg [15:0] InstrMem[0:511], DataMem[0:511];
wire [15:0] InstrReg, SignExtend, NextPC, ReadData2, A, B, ALUOut, PCplus1, AluOrMem;
wire [1:0] WriteReg;
wire [3:0] op;
wire [2:0] ALUctl;
... | 6.928165 |
module CPU (
clock,
WriteData,
InstrReg
);
input clock;
output [15:0] WriteData, InstrReg;
reg [15:0] PC;
reg [15:0] InstrMem[0:511], DataMem[0:511];
wire [15:0] InstrReg, SignExtend, NextPC, ReadData2, A, B, ALUOut, PCplus1, AluOrMem;
wire [1:0] WriteReg;
wire [3:0] op;
wire [2:0] ALUctl;
... | 6.928165 |
module Addu (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = a + b;
tz = (tr == 32'b0) ? 1 : 0;
if (tr < a || tr < b) tc = 1;
else tc = 0;
t... | 7.771695 |
module Add (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
//output c,
output n,
output v
);
reg [31:0] tr;
reg tz;
//reg tc;
reg tn;
reg tv;
always @(*) begin
tr = a + b;
tz = (tr == 32'b0) ? 1 : 0;
tn = tr[31];
if (a[31] == b[31] && tr[31] != a[3... | 8.023242 |
module Subu (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = a - b;
tz = (tr == 32'b0) ? 1 : 0;
if (a < b) tc = 1;
else tc = 0;
tn = tr[31];... | 7.322025 |
module Sub (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
//output c,
output n,
output v
);
reg [31:0] tr;
reg tz;
//reg tc;
reg tn;
reg tv;
always @(*) begin
tr = a - b;
tz = (tr == 32'b0) ? 1 : 0;
tn = tr[31];
if (a[31] != b[31] && tr[31] != a[3... | 7.006921 |
module And (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
//output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
//reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = a & b;
tz = (tr == 32'b0) ? 1 : 0;
tn = tr[31];
end
assign r = tr;
assign z = t... | 7.717851 |
module Or (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
//output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
//reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = a | b;
tz = (tr == 32'b0) ? 1 : 0;
tn = tr[31];
end
assign r = tr;
assign z = tz... | 6.953311 |
module Xor (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
//output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
//reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = a ^ b;
tz = (tr == 32'b0) ? 1 : 0;
tn = tr[31];
end
assign r = tr;
assign z = t... | 6.839887 |
module Nor (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
//output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
//reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = ~(a | b);
tz = (tr == 32'b0) ? 1 : 0;
tn = tr[31];
end
assign r = tr;
assign z ... | 7.237741 |
module Slt (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
//output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
reg tc;
reg tn;
//reg tv;
always @(*) begin
if (a[31] == 0 && b[31] == 1) tr = 0;
else if (a[31] == 1 && b[31] == 0) tr = 1;
else if (a[31... | 7.360612 |
module Sltu (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = (a < b) ? 1 : 0;
tz = (a == b) ? 1 : 0;
tc = (a < b) ? 1 : 0;
tn = tr[31];
end
... | 6.504955 |
module Sra (
input [31:0] a,
input signed [31:0] b,
output [31:0] r,
output z,
output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = b >>> a;
tz = (tr == 32'b0) ? 1 : 0;
if (a == 0) tc = 0;
else if (a < 32'd33) ... | 7.995241 |
module Sl (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = b << a;
tz = (tr == 32'b0) ? 1 : 0;
if (a == 0) tc = 0;
else if (a < 32'd33) tc = b[32... | 7.196211 |
module Srl (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output z,
output c,
output n
//output v
);
reg [31:0] tr;
reg tz;
reg tc;
reg tn;
//reg tv;
always @(*) begin
tr = b >> a;
tz = (tr == 32'b0) ? 1 : 0;
if (a == 0) tc = 0;
else if (a < 32'd33) tc = b[a... | 7.395165 |
module mux32 (
input [31:0] a, //0
input [31:0] b, //1
input choose,
output [31:0] z
);
reg [31:0] temp;
always @(*) begin
if (choose == 0) temp = a;
else temp = b;
end
assign z = temp;
endmodule
| 8.8524 |
module mux5 (
input [4:0] a, //0
input [4:0] b, //1
input choose,
output [4:0] z
);
reg [4:0] temp;
always @(*) begin
if (choose == 0) temp = a;
else temp = b;
end
assign z = temp;
endmodule
| 8.378484 |
module regfile (
input [4:0] rna, //Rsc
input [4:0] rnb, //Rtc
input [4:0] wn, //Rdc
input [31:0] d, //Rd
input clk,
input we,
input clr,
output [31:0] qa, //Rs
output [31:0] qb //Rt
);
reg [31:0] register[0:31];
integer i;
assign qa = (rna == 0) ? 0 : regist... | 7.809308 |
module pc (
input [31:0] in,
input clk,
input pc0,
input rst,
output [31:0] out
);
reg [31:0] temp;
always @(posedge clk or posedge rst) begin
if (rst) temp = 0;
else begin
if (pc0) temp = in; //-32'h00400000;
else temp = in;
end
end
assign out = temp;
endmodule
| 7.068574 |
module npc (
input [31:0] in,
output [31:0] out
);
assign out = in + 32'h00000004;
endmodule
| 7.25161 |
module dmem (
input [31:0] datain,
input [31:0] addr,
input dm_w,
input dm_r,
input dm_cs,
//input rst,
output [31:0] dataout
);
reg [7:0] tab[0:1023];
wire [31:0] addr0 = addr; //-32'h10010000;
reg [31:0] temp;
//integer i;
always @(posedge dm_cs)// or posedge rst)
begin
... | 7.276583 |
module imem (
input [31:0] addr,
//input im_r,
//input rst,
output [31:0] instr
);
reg [31:0] tab[0:1023];
reg [31:0] temp;
integer i;
initial begin
for (i = 0; i < 1024; i = i + 1) tab[i] = 0;
$readmemh("E:\\cpu_input.txt", tab);
end
assign instr = tab[addr];
//assign instr[7:0]=... | 6.860817 |
module ext16 (
input [15:0] in,
input s,
output [31:0] out
);
reg [31:0] temp;
always @(*) begin
if (s) begin
temp = {(in[15] == 0 ? 16'b0 : 16'hffff), in};
end else begin
temp = {16'b0, in};
end
end
assign out = temp;
endmodule
| 7.508802 |
module CPU31_dataflow (
input clock,
input rst,
output [31:0] o_addr,
output [31:0] inst
);
wire rf_w, rf_clk, dm_cs, dm_r, dm_w, pc0, extsign;
wire [3:0] aluc;
wire [9:0] m;
wire [4:0] rsc, rtc, rdc;
wire [31:0] instr;
wire zero, carry, negetive, overflow;
wire [31:0] pc_in, pc_out, npc_o... | 6.828559 |
module CPU31_tb ();
reg clk;
reg reset;
integer file_output;
integer counter = 0;
cpu CPU (
clk,
reset
);
initial begin
clk <= 0;
reset <= 1;
file_output = $fopen("result.txt");
#30 reset <= 0;
end
always begin
#10 clk <= ~clk;
if (clk == 1'b0) begin
if (cou... | 7.614515 |
module CPU32_tb;
reg clk;
reg btn0_n;
// CPU instance
CPU32 CPU32_0 (
.clk(clk),
.btn0_n(btn0_n)
);
// clock
initial begin
clk = 0;
forever #`HCYCL clk = !clk;
end
// test
initial begin
// init regs
btn0_n = 1;
// reset
test_reset_button();
end
// task... | 6.827833 |
module memwbReg (
daddrbusIn,
daddrbusOut,
databusIn,
databusOut,
loadSelectIn,
loadSelectOut,
clk,
DselectIn,
DselectOut
);
input [31:0] daddrbusIn, databusIn, DselectIn;
input loadSelectIn, clk;
output reg [31:0] daddrbusOut, databusOut, DselectOut;
output reg loadSelectOut... | 7.108281 |
module triStateBuffer (
S,
in,
out
);
input [1:0] S;
input [31:0] in;
output [31:0] out;
assign out = (S == 2'b00 || S == 2'b10) ? in : 32'bz;
endmodule
| 7.116795 |
module exmemReg (
aluOut,
dSelectIn,
clk,
dbus,
dSelectOut,
loadSelectIn,
loadSelectOut,
databusIn,
databusOut
);
input [31:0] aluOut, dSelectIn, databusIn;
input clk;
input [1:0] loadSelectIn;
output reg [31:0] dbus, dSelectOut, databusOut;
output reg [1:0] loadSelectOut;
... | 7.168855 |
module lac2 (
c,
gout,
pout,
Cin,
g,
p
);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0 (
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1... | 7.041719 |
module lac3 (
c,
gout,
pout,
Cin,
g,
p
);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0 (
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 lea... | 7.493179 |
module lac4 (
c,
gout,
pout,
Cin,
g,
p
);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0 (
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 l... | 7.369679 |
module lac5 (
c,
gout,
pout,
Cin,
g,
p
);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0 (
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac... | 7.061106 |
module idexReg (
muxOut,
Imm,
S,
Cin,
clk,
out,
Immout,
Sout,
Cinout,
signExtIn,
signExtOut,
abusIn,
abusOut,
bbusIn,
bbusOut,
loadSelectIn,
loadSelectOut,
slInsIn,
slInsOut
);
input [31:0] muxOut, signExtIn, abusIn, bbusIn;
input Imm, Cin,... | 7.222671 |
module equalizer (
a,
b,
out,
DselectIn,
DselectOut,
en,
fxn
);
input [31:0] a, b, DselectIn;
// 0 is BEQ, 1 is BNE
input en, fxn;
output out;
output [31:0] DselectOut;
assign out = !en ? 0 : // default - not branching
(a == b && fxn == 0) ? 1 : // beq function
(a ... | 8.386922 |
module regfile (
Aselect,
Bselect,
Dselect,
dbus,
clk,
abus,
bbus
);
input [31:0] Aselect, Bselect, Dselect, dbus;
input clk;
output [31:0] abus, bbus;
assign abus = Aselect[0] ? 0 : 32'bz;
assign bbus = Bselect[0] ? 0 : 32'bz;
negdffcell register_cells[30:0] (
.Aselect(Ase... | 7.809308 |
module negdffcell (
Aselect,
Bselect,
clk,
Dselect,
dbus,
abus,
bbus
);
input Aselect, Bselect, clk, Dselect;
input [31:0] dbus;
output [31:0] abus, bbus;
wire [31:0] Q;
negdff flip (
.D(dbus),
.clk(clk),
.Dselect(Dselect),
.Q(Q)
);
buffer cellbuffer (
... | 6.666465 |
module negdff (
D,
clk,
Dselect,
Q
);
input [31:0] D;
input clk, Dselect;
output reg [31:0] Q;
wire newclk;
assign newclk = clk & Dselect;
always @(negedge newclk) begin
if (Dselect == 1'b1) Q = D;
end
endmodule
| 6.602183 |
module buffer (
Q,
Aselect,
Bselect,
abus,
bbus
);
input [31:0] Q;
input Aselect, Bselect;
output [31:0] abus, bbus;
assign abus = Aselect ? Q : 32'bz;
assign bbus = Bselect ? Q : 32'bz;
endmodule
| 6.861394 |
module mux2to1 (
abus,
bbus,
S,
out
);
input [31:0] abus, bbus;
input S;
output [31:0] out;
wire sWire;
assign sWire = (S === 1'bx) ? 0 : S;
assign out = sWire ? bbus : abus;
endmodule
| 7.107199 |
module dec5to32 (
in,
out
);
input [4:0] in;
output reg [31:0] out;
always @(in, out) begin
// out = 32'h00000001 << in;
case (in)
5'b00000: out = 32'b00000000000000000000000000000001;
5'b00001: out = 32'b00000000000000000000000000000010;
5'b00010: out = 32'b000000000000000000000... | 7.164931 |
module ifidReg (
ibusIn,
clk,
ibusOut,
iaddrbusIn,
iaddrbusOut
);
input [31:0] ibusIn, iaddrbusIn;
input clk;
output reg [31:0] ibusOut, iaddrbusOut;
always @(posedge clk) begin
ibusOut = ibusIn;
iaddrbusOut = iaddrbusIn;
end
endmodule
| 6.967215 |
module adder (
a,
b,
d
);
input [31:0] a, b;
output [31:0] d;
assign d = a + b;
endmodule
| 7.4694 |
module pcReg (
clk,
iaddrbusIn,
iaddrbusOut,
reset
);
input clk, reset;
input [31:0] iaddrbusIn;
output reg [31:0] iaddrbusOut;
initial begin
iaddrbusOut = 32'b0;
end
always @(posedge clk) begin
if (reset) iaddrbusOut = 32'b0;
else iaddrbusOut = iaddrbusIn;
end
endmodule
| 7.292771 |
module CPU54_regfiles (
input clock_in,
input reset_signal,
input enable,
input [4:0] read_data_ad1,
input [4:0] read_data_ad2,
input [4:0] write_data_ad1,
input [31:0] write_data,
output [31:0] outputdata1,
output [31:0] outputdata2
);
reg [31:0] array_reg[31:0];
always @(posedg... | 8.072472 |
module memwbReg (
daddrbusIn,
daddrbusOut,
databusIn,
databusOut,
loadSelectIn,
loadSelectOut,
clk,
DselectIn,
DselectOut
);
input [31:0] DselectIn;
input [63:0] daddrbusIn, databusIn;
input loadSelectIn, clk;
output reg [31:0] DselectOut;
output reg [63:0] daddrbusOut, dat... | 7.108281 |
module triStateBuffer (
S,
in,
out
);
input [1:0] S;
input [63:0] in;
output [63:0] out;
assign out = (S == 2'b00 || S == 2'b10) ? in : 64'bz;
endmodule
| 7.116795 |
module exmemReg (
aluResultIn,
aluResultOut,
clk,
dSelectIn,
dSelectOut,
loadSelectIn,
loadSelectOut,
databusIn,
databusOut
);
input [63:0] aluResultIn, databusIn;
input [31:0] dSelectIn;
input clk;
input [1:0] loadSelectIn;
output reg [63:0] aluResultOut, databusOut;
out... | 7.168855 |
module mux2to1_32bit (
abus,
bbus,
S,
out
);
input [31:0] abus, bbus;
input S;
output [31:0] out;
wire sWire;
assign sWire = (S === 1'bx) ? 0 : S;
assign out = sWire ? bbus : abus;
endmodule
| 7.746454 |
module mux2to1_64bit (
abus,
bbus,
S,
out
);
input [63:0] abus, bbus;
input S;
output [63:0] out;
wire sWire;
assign sWire = (S === 1'bx) ? 0 : S;
assign out = sWire ? bbus : abus;
endmodule
| 7.056817 |
module lac2 (
c,
gout,
pout,
Cin,
g,
p
);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0 (
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1... | 7.041719 |
module lac3 (
c,
gout,
pout,
Cin,
g,
p
);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0 (
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 lea... | 7.493179 |
module lac4 (
c,
gout,
pout,
Cin,
g,
p
);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0 (
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 l... | 7.369679 |
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