code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module lac5 (
c,
gout,
pout,
Cin,
g,
p
);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0 (
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac... | 7.061106 |
module lac6 (
c,
gout,
pout,
Cin,
g,
p
);
output [63:0] c;
output gout, pout;
input Cin;
input [63:0] g, p;
wire [1:0] cint, gint, pint;
lac5 leaf0 (
.c(c[31:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[31:0]),
.p(p[31:0])
);
lac... | 7.062709 |
module idexReg (
clk,
abusIn,
abusOut,
bbusIn,
bbusOut,
loadSelectIn,
loadSelectOut,
shiftInsIn,
shiftInsOut,
AluInsIn,
AluInsOut,
DselectIn,
DselectOut,
shamtIn,
shamtOut,
ImmIn,
ImmOut
);
input clk;
input [63:0] abusIn, bbusIn, shamtIn, ImmIn;
... | 7.222671 |
module shamtDecoder (
ibus,
out,
shiftIns
);
input [31:0] ibus;
input [2:0] shiftIns;
output [63:0] out;
// LSR and LSL shamt quad MOV amt
assign out = !shiftIns[2] ? ibus[15:10] : ibus[22:21] * 16;
endmodule
| 6.789341 |
module immDecoder (
ibus,
extOp,
out
);
input [31:0] ibus;
input [4:0] extOp;
output [63:0] out;
assign out = extOp[4] ? {52'b0, ibus[21:10]} : // ALUImm
extOp[3] ? {{55{ibus[20]}}, ibus[20:12]} : // DT_Addr
extOp[2] ? {48'b0, ibus[20:5]} : // MovImm
extOp[1] ? {{43{ibus[23]}}, ... | 7.02894 |
module checkBranch (
eqIn,
branchCode,
flags,
out,
cbOrB
);
input eqIn, cbOrB;
output out;
input [2:0] branchCode;
input [3:0] flags;
// {Negative,Zero,Overflow,CarryOver}
// eqIn from CBZ or CBNZ and cbOrB for Branch stmts
assign out = eqIn || cbOrB || (branchCode == 3'b001 && flags... | 7.351552 |
module equalizer (
DselectIn,
DselectOut,
rt,
en,
fxn,
out,
loadSelectIn
);
input [31:0] DselectIn;
input [63:0] rt;
input [1:0] loadSelectIn; // for setting Dselect to null register when STUR
// 10 = CBZ, 11 = CBNZ
input en, fxn;
output out;
output [31:0] DselectOut;
assign... | 8.386922 |
module regfile (
Aselect,
Bselect,
Dselect,
dbus,
clk,
abus,
bbus
);
input [31:0] Aselect, Bselect, Dselect;
input [63:0] dbus;
input clk;
output [63:0] abus, bbus;
// changed 0 reg from r0 to r31
negdffcell register_cells[30:0] (
.Aselect(Aselect[30:0]),
.Bse... | 7.809308 |
module negdffcell (
Aselect,
Bselect,
clk,
Dselect,
dbus,
abus,
bbus
);
input Aselect, Bselect, clk, Dselect;
input [63:0] dbus;
output [63:0] abus, bbus;
wire [63:0] Q;
negdff flip (
.D(dbus),
.clk(clk),
.Dselect(Dselect),
.Q(Q)
);
buffer cellbuffer (
... | 6.666465 |
module negdff (
D,
clk,
Dselect,
Q
);
input [63:0] D;
input clk, Dselect;
output reg [63:0] Q;
wire newclk;
assign newclk = clk & Dselect;
always @(negedge newclk) begin
if (Dselect == 1'b1) Q = D;
end
endmodule
| 6.602183 |
module buffer (
Q,
Aselect,
Bselect,
abus,
bbus
);
input [63:0] Q;
input Aselect, Bselect;
output [63:0] abus, bbus;
assign abus = Aselect ? Q : 64'bz;
assign bbus = Bselect ? Q : 64'bz;
endmodule
| 6.861394 |
module dec5to32 (
in,
out
);
input [4:0] in;
output reg [31:0] out;
always @(in, out) begin
case (in)
5'b00000: out = 32'b00000000000000000000000000000001;
5'b00001: out = 32'b00000000000000000000000000000010;
5'b00010: out = 32'b00000000000000000000000000000100;
5'b00011: out ... | 7.164931 |
module ifidReg (
ibusIn,
clk,
ibusOut,
iaddrbusIn,
iaddrbusOut
);
input [31:0] ibusIn;
input [63:0] iaddrbusIn;
input clk;
output reg [31:0] ibusOut;
output reg [63:0] iaddrbusOut;
always @(posedge clk) begin
ibusOut = ibusIn;
iaddrbusOut = iaddrbusIn;
end
endmodule
| 6.967215 |
module adder (
a,
b,
d
);
input [63:0] a, b;
output [63:0] d;
assign d = a + b;
endmodule
| 7.4694 |
module pcReg (
clk,
iaddrbusIn,
iaddrbusOut,
reset
);
input clk, reset;
input [63:0] iaddrbusIn;
output reg [63:0] iaddrbusOut;
always @(posedge clk) begin
if (reset) iaddrbusOut = 0;
else iaddrbusOut = iaddrbusIn;
end
endmodule
| 7.292771 |
module cpu6510 (
input clk, // CPU clock
input reset, // reset signal
output reg [15:0] AB, // address bus
input [ 7:0] DI, // data in, read bus
output reg [ 7:0] DO, // data out, write bus
output reg WE, // write enable
input ... | 6.501866 |
module Memory (
input wire clock,
input wire [18:0] address,
input wire write_en,
input wire [7:0] data_in,
output reg [7:0] data_out
);
reg [7:0] rom_cells[0:8191];
reg [7:0] ram_cells[0:4095];
reg [7:0] low_ram_cells[0:4095];
integer i;
initial begin
for (i = 0; i < 4096; i = i + 1... | 7.051739 |
module
//
// Finds arithmetic operations needed. Latches on the positive edge of the
// clock. There are 8 different types of operations, which come from bits
// 3-5 of the instruction.
//
module alu(res, opra, oprb, cin, cout, zout, sout, parity, auxcar, sel);
input [7:0] opra; // Input A
input [7:0] oprb;... | 7.196583 |
module CPUBus (
input clk,
input rst,
//CPU bus
input [31:0] addrBus,
input masterEN,
output reg [31:0] dataToCPU,
output nakDBus,
//BIOS memory, bfc00000-bfc04000, 4K word
output progMemEN,
input [31:0] progMemData,
input progMemNak,
//Character VRAM, bfc04000-bfc08000, ... | 7.729518 |
module cpuBusInterface (
input clk,
input memop,
input bus_ack,
input bus_wait,
output reg bus_req,
output pc_stall,
output reg data_out
);
parameter STATE_IDLE = 0;
parameter STATE_REQ = 1;
parameter STATE_ADDR = 2;
parameter STATE_WAIT = 3;
parameter STATE_DATA = 4;
parameter ... | 7.846397 |
module CpuBusSubInterface (
input clk_i,
input rst_i,
input cs_i,
input mem_req_i,
input mem_en_i,
input bus_ack_i,
input [31:0] bus_dat_i,
output sub_req_o,
output sub_stb_o,
output [31:0] sub_dat_o
);
reg sub_stb_reg;
reg sub_ack_reg;
reg [31:0] sub_dat_reg;
/* sub_st... | 7.198338 |
module cpuclk (
// Clock out ports
output clk_out1,
// Clock in ports
input clk_in1
);
cpuclk_clk_wiz inst (
// Clock out ports
.clk_out1(clk_out1),
// Clock in ports
.clk_in1 (clk_in1)
);
endmodule
| 6.606706 |
module cpuclk_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out1,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_cpuclk;
wire clk_in2_cpuclk;
IBUF clkin1_ibufg (
.O(clk_in1_cpuclk),
.I(clk_in1)
);
// Cl... | 7.938711 |
module cpuclk (
clk_out1,
clk_in1
);
output clk_out1;
input clk_in1;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
cpuclk_cpuclk_clk_wiz inst (
.clk_in1 (clk_in1),
.clk_out1(clk_out1)
);
endmodule
| 6.606706 |
module CPUControl (
input clk,
input [15:0] sw,
input btnL,
input btnR,
input btnC,
input btnU,
input btnD,
inout [3:0] JB,
output [15:0] led,
output [6:0] seg,
output [3:0] an,
output dp
);
// This makes me sad. Switch 14 is shorted with switch 13's value...
// Good... | 7.738631 |
module Comparator (
input [31:0] io_src1,
input [31:0] io_src2,
input [ 3:0] io_op,
output io_result
);
localparam CompareOp_EQ = 4'd0;
localparam CompareOp_NE = 4'd1;
localparam CompareOp_EQZ = 4'd2;
localparam CompareOp_NEZ = 4'd3;
localparam CompareOp_GE = 4'd4;
localparam Compa... | 8.939213 |
module BRU (
input io_predictJump,
input [31:0] io_predictAddr,
input io_isBranch,
input io_isJump,
input io_isJR,
input [31:0] io_pc,
input [25:0] io_inst,
input io_condition,
input [31:0] io_regSrc,
... | 7.902897 |
module cpuctrl ( /*AUTOARG*/
// Outputs
cpuctrl_apb_prdata,
cpuctrl_apb_pready,
cpuctrl_apb_pslverr,
cpuctrl_out_r,
// Inputs
apb_cpuctrl_psel,
apb_cpuctrl_paddr,
apb_cpuctrl_penable,
apb_cpuctrl_pwrite,
apb_cpuctrl_pwdata,
clk_apb,
rst_apb_n
);
parameter CPUCTRL_... | 7.247823 |
module: CPU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cpuDEBUG1;
// Inputs
reg Reset;
reg Clock;
// Outputs
wire [31:0] Result;
wire [31:0] Addr;
wire [31:0] ALUin11;
... | 6.741629 |
module SignExtension (
input [ 5:0] iOpcode,
input [15:0] iImmediate,
output [31:0] oExtendedImmediate
);
// assign oExtendedImmediate=iImmediate[15]?{16{1'b1}, iImmediate}:{16{1'b0}, iImmediate};
//andi, ori xori zeroExtensionI formatsignExtension
// sltiu ȡALUʵsltiu㷨
// 32λ-ext(16λ) ȻжϷţôչȽϺ
... | 6.562271 |
module Registers (
input iCpuClock,
iCpuReset, // ʱӺλ
input [ 4:0] iRegisterSource1, //iRegisterSource1
input [ 4:0] iRegisterSource2, //iRegisterSource2
input [ 4:0] iRegisterDestination, //iRegisterDestination
input [31:0] iWritingData, // the data being writt... | 7.405039 |
module cpu_0_custom_instruction_master_arbitrator (
// inputs:
clk,
cpu_0_custom_instruction_master_multi_start,
cpu_0_fpoint_s1_done_from_sa,
cpu_0_fpoint_s1_result_from_sa,
reset_n,
// outputs:
cpu_0_custom_instruction_master_multi_done,
cpu_0_custom_instruction_master_multi_resul... | 7.140805 |
module cpueffect_reset_cpu_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRES... | 6.941566 |
module cpueffect_reset_clk_50_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS... | 6.941566 |
module_tck.v"
`include "cpu_0_jtag_debug_module_sysclk.v"
`include "cpu_0_jtag_debug_module_wrapper.v"
`include "cpu_0.v"
`include "vibrato_on.v"
`include "clk.v"
`include "onchip_memory2_0.v"
`include "cpueffect_clock_0.v"
`include "adclrc.v"
`include "dataout.v"
`include "pll_0.v"
`include "altpllpll_0.v"
`timescale... | 6.847645 |
module cpueffect_clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0... | 7.706293 |
module cpueffect_clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \... | 7.706293 |
module CPUExecutionUnit (
input i_Clk,
input i_Rst,
//Control Signals
//Program Counter
input i_PCWrite,
//IReg
input i_IRegWR,
output [31:0] o_Instruction,
//Register file
input i_REGWriteEn,
input [1:0] i_REGWriteSrc,
//ALU
input [3:0] i_ALUOpCode,
input [1:... | 8.547046 |
module CPUExecutionUnit_tb ();
//The various ALU operations
parameter ALU_ADDITION = 2'b00;
parameter ALU_SUBTRACTION = 2'b01;
parameter ALU_AND = 2'b10;
parameter ALU_OR = 2'b11;
//ALU SRC A Mux Options
parameter ALU_SRCA_REG_1 = 1'd0;
parameter ALU_SRCA_PC = 1'd1;
//ALU SRC B Mux Options
paramet... | 8.547046 |
module cpuInternalMMU (
//Cpu 0000-FFFF
input [15:0] A_cpu,
output [ 7:0] Do_cpu,
input [ 7:0] Di_cpu,
input wr_cpu,
input rd_cpu,
//MMU 0000-FF7F
output [15:0] A_MMU,
output [7:0] Do_MMU,
input [7:0] Di_MMU,
output cs_MMU,
output wr_MMU,
... | 6.574691 |
module complimenter (
INPUT,
OUTPUT
);
/*This module compliments the input*/
input [7:0] INPUT; //This is the input
wire [7:0] OUT;
output [7:0] OUTPUT; //This is the complimented output
//Instatntiating 8 parallel NOT gates to negate the INPUT value
not n0 (OUT[0], INPUT[0]);
not n1 (OUT[1], I... | 7.489017 |
module decoder (
INSTRUCTION,
OPCODE,
WRITEREG,
READREG1,
READREG2,
IMMEDIATE,
JUMPADD,
BUSYWAIT
);
/*This module takes necessary parts out of the instruction*/
input [31:0] INSTRUCTION;
output reg [7:0] OPCODE, IMMEDIATE, JUMPADD;
output reg [2:0] WRITEREG, READREG1, READREG2;
... | 7.018254 |
module mux2 (
IMMEDIATE,
OPERAND2,
SELECT,
RESULT
);
/*This module works as a mux. If the current operation is a loading, this assigns the immediate value as the operand, otherwise the value taken from the register file*/
input [7:0] IMMEDIATE,OPERAND2,SELECT; //These are the inputs which takes imm... | 8.449287 |
module mux3 (
MUX2RESULT,
COM_IMMEDIATE,
isSRALEFT,
OPERAND2
);
//This module behaves as a mux. If control signal is 1, output is Complimented IMMEDIATE value. Otherwise the result of the MUX2
//This module supprts to the excecution of sra instruction (if it is sra instruction and if immediate value... | 7.796484 |
module alu (
DATA1,
DATA2,
RESULT,
SELECT
);
/*This module executes a mux which selects the correct answer to be sent
* according to the 'SELECT' input*/
input [7:0] DATA1, DATA2; //These are the two inputs operand 1 and 2
input [2:0] SELECT; //This is the input whch indicates the operation to b... | 6.675659 |
module Forward (
operand,
result
);
/*This module assigns the value of the operand to the result*/
input [7:0] operand; //This is the input
output [7:0] result; //This is the output
assign result = operand;
endmodule
| 6.779622 |
module Add (
operand1,
operand2,
result
);
/*This module assigns the sum of operand 1 and 2 to the result*/
input [7:0] operand1, operand2; //These are the inputs
output [7:0] result; //This is the output
assign result = operand1 + operand2;
endmodule
| 7.896949 |
module And (
operand1,
operand2,
result
);
/*This module assigns the bitwise and of operand 1.2 to the result*/
input [7:0] operand1, operand2; //These are the inputs
output [7:0] result; //This is the output
assign result = operand1 & operand2;
endmodule
| 7.915974 |
module Or (
operand1,
operand2,
result
);
/*This module assigns the bitwise or of operand 1,2 to the result*/
input [7:0] operand1, operand2; //These are the inputs
output [7:0] result; //This is the input
assign result = operand1 | operand2;
endmodule
| 8.06812 |
module atomic_mux (
INPUT0,
INPUT1,
SELECT,
OUTPUT
);
//This is a simple 2to1 mux
input INPUT0,INPUT1,SELECT; //INPUT0 and INPUT1 are the inputs and SELECT is the selecting input
output reg OUTPUT; //OUTPUT is the output of the mux
always @* begin
if (SELECT) OUTPUT = INPUT1;
el... | 7.474683 |
module Mlt (
IN,
OPERAND,
OUTPUT
);
//This module generates the multiple of two given binary values
input [7:0] IN, OPERAND; //These are the two operands
output [7:0] OUTPUT; //This is the output
//These below wires are used to hold the outputs of AND gate layers
wire [7:0] o1, o2, o3, o4, o5, o... | 7.474758 |
module and_layer (
IN1,
IN2,
IN3,
IN4,
IN5,
IN6,
IN7,
IN8,
SELECT,
OUT1,
OUT2,
OUT3,
OUT4,
OUT5,
OUT6,
OUT7,
OUT8
);
//This is an AND gate layer which includes 8 parallel AND gates. A particular one input is common for all the gatese and rest are dif... | 6.923715 |
module ADD (
op1,
op2,
result
);
/*This module executes 8-Bit adding operation using fulladders*/
input [7:0] op1, op2; //These are two inputs,operand 1 and 2
output [7:0] result; //This is the outputs which sends the SUM
wire cout1,cout2,cout3,cout4,cout5,cout6,cout7,cout8; //These wires delivers... | 7.715009 |
module fulladder (
op1,
op2,
CarryIN,
Answer,
CarryOUT
);
//This module is a full adder which adds two bits
input op1,op2,CarryIN; //These are two operands and CarryIN is the carry in to the operation from previous operation
output Answer, CarryOUT; //These are the two outsouts answer and ca... | 7.454465 |
module reg_file (
IN,
OUT1,
OUT2,
INADDRESS,
OUT1ADDRESS,
OUT2ADDRESS,
WRITE,
CLK,
RESET
);
/*This module executes Register File which stores eight 8-bit values*/
input [2:0] INADDRESS,OUT1ADDRESS,OUT2ADDRESS; //These are inputs which takes addresses of registers
input [7:0] I... | 7.294051 |
module complimenter (
INPUT,
OUTPUT
);
/*This module compliments the input*/
input [7:0] INPUT; //This is the input
wire [7:0] OUT;
output [7:0] OUTPUT; //This is the complimented output
//Instatntiating 8 parallel NOT gates to negate the INPUT value
not n0 (OUT[0], INPUT[0]);
not n1 (OUT[1], I... | 7.489017 |
module decoder (
INSTRUCTION,
OPCODE,
WRITEREG,
READREG1,
READREG2,
IMMEDIATE,
JUMPADD,
BUSYWAIT
);
/*This module takes necessary parts out of the instruction*/
input [31:0] INSTRUCTION;
output reg [7:0] OPCODE, IMMEDIATE, JUMPADD;
output reg [2:0] WRITEREG, READREG1, READREG2;
... | 7.018254 |
module mux2 (
IMMEDIATE,
OPERAND2,
SELECT,
RESULT
);
/*This module works as a mux. If the current operation is a loading, this assigns the immediate value as the operand, otherwise the value taken from the register file*/
input [7:0] IMMEDIATE,OPERAND2,SELECT; //These are the inputs which takes imm... | 8.449287 |
module mux3 (
MUX2RESULT,
COM_IMMEDIATE,
isSRALEFT,
OPERAND2
);
//This module behaves as a mux. If control signal is 1, output is Complimented IMMEDIATE value. Otherwise the result of the MUX2
//This module supprts to the excecution of sra instruction (if it is sra instruction and if immediate value... | 7.796484 |
module alu (
DATA1,
DATA2,
RESULT,
SELECT
);
/*This module executes a mux which selects the correct answer to be sent
* according to the 'SELECT' input*/
input [7:0] DATA1, DATA2; //These are the two inputs operand 1 and 2
input [2:0] SELECT; //This is the input whch indicates the operation to b... | 6.675659 |
module Forward (
operand,
result
);
/*This module assigns the value of the operand to the result*/
input [7:0] operand; //This is the input
output [7:0] result; //This is the output
assign result = operand;
endmodule
| 6.779622 |
module Add (
operand1,
operand2,
result
);
/*This module assigns the sum of operand 1 and 2 to the result*/
input [7:0] operand1, operand2; //These are the inputs
output [7:0] result; //This is the output
assign result = operand1 + operand2;
endmodule
| 7.896949 |
module And (
operand1,
operand2,
result
);
/*This module assigns the bitwise and of operand 1.2 to the result*/
input [7:0] operand1, operand2; //These are the inputs
output [7:0] result; //This is the output
assign result = operand1 & operand2;
endmodule
| 7.915974 |
module Or (
operand1,
operand2,
result
);
/*This module assigns the bitwise or of operand 1,2 to the result*/
input [7:0] operand1, operand2; //These are the inputs
output [7:0] result; //This is the input
assign result = operand1 | operand2;
endmodule
| 8.06812 |
module atomic_mux (
INPUT0,
INPUT1,
SELECT,
OUTPUT
);
//This is a simple 2to1 mux
input INPUT0,INPUT1,SELECT; //INPUT0 and INPUT1 are the inputs and SELECT is the selecting input
output reg OUTPUT; //OUTPUT is the output of the mux
always @* begin
if (SELECT) OUTPUT = INPUT1;
el... | 7.474683 |
module Mlt (
IN,
OPERAND,
OUTPUT
);
//This module generates the multiple of two given binary values
input [7:0] IN, OPERAND; //These are the two operands
output [7:0] OUTPUT; //This is the output
//These below wires are used to hold the outputs of AND gate layers
wire [7:0] o1, o2, o3, o4, o5, o... | 7.474758 |
module and_layer (
IN1,
IN2,
IN3,
IN4,
IN5,
IN6,
IN7,
IN8,
SELECT,
OUT1,
OUT2,
OUT3,
OUT4,
OUT5,
OUT6,
OUT7,
OUT8
);
//This is an AND gate layer which includes 8 parallel AND gates. A particular one input is common for all the gatese and rest are dif... | 6.923715 |
module ADD (
op1,
op2,
result
);
/*This module executes 8-Bit adding operation using fulladders*/
input [7:0] op1, op2; //These are two inputs,operand 1 and 2
output [7:0] result; //This is the outputs which sends the SUM
wire cout1,cout2,cout3,cout4,cout5,cout6,cout7,cout8; //These wires delivers... | 7.715009 |
module fulladder (
op1,
op2,
CarryIN,
Answer,
CarryOUT
);
//This module is a full adder which adds two bits
input op1,op2,CarryIN; //These are two operands and CarryIN is the carry in to the operation from previous operation
output Answer, CarryOUT; //These are the two outsouts answer and ca... | 7.454465 |
module reg_file (
IN,
OUT1,
OUT2,
INADDRESS,
OUT1ADDRESS,
OUT2ADDRESS,
WRITE,
CLK,
RESET
);
/*This module executes Register File which stores eight 8-bit values*/
input [2:0] INADDRESS,OUT1ADDRESS,OUT2ADDRESS; //These are inputs which takes addresses of registers
input [7:0] I... | 7.294051 |
module tagcmp (
tag1,
tag2,
isEqual
);
input [2:0] tag1, tag2;
output isEqual;
wire w1, w2, w3;
xnor g1 (w1, tag1[0], tag2[0]);
xnor g2 (w2, tag1[1], tag2[1]);
xnor g3 (w3, tag1[2], tag2[2]);
assign #0.9 isEqual = w1 && w2 && w3;
endmodule
| 7.353774 |
module selectionMUX (
ALLDATA,
select,
OUTDATA,
IsRead
);
input [31:0] ALLDATA;
input [1:0] select; // Address offset
input IsRead;
output reg [7:0] OUTDATA;
always @(*) begin
if (IsRead) begin
case (select)
2'b00: begin
#1 OUTDATA = ALLDATA[7:0];
end
... | 8.174491 |
module complimenter (
INPUT,
OUTPUT
);
/*This module compliments the input*/
input [7:0] INPUT; //This is the input
wire [7:0] OUT;
output [7:0] OUTPUT; //This is the complimented output
//Instatntiating 8 parallel NOT gates to negate the INPUT value
not n0 (OUT[0], INPUT[0]);
not n1 (OUT[1], I... | 7.489017 |
module decoder (
INSTRUCTION,
OPCODE,
WRITEREG,
READREG1,
READREG2,
IMMEDIATE,
JUMPADD,
BUSYWAIT
);
/*This module takes necessary parts out of the instruction*/
input [31:0] INSTRUCTION;
output reg [7:0] OPCODE, IMMEDIATE, JUMPADD;
output reg [2:0] WRITEREG, READREG1, READREG2;
... | 7.018254 |
module mux2 (
IMMEDIATE,
OPERAND2,
SELECT,
RESULT
);
/*This module works as a mux. If the current operation is a loading, this assigns the immediate value as the operand, otherwise the value taken from the register file*/
input [7:0] IMMEDIATE,OPERAND2,SELECT; //These are the inputs which takes imm... | 8.449287 |
module mux3 (
MUX2RESULT,
COM_IMMEDIATE,
isSRALEFT,
OPERAND2
);
//This module behaves as a mux. If control signal is 1, output is Complimented IMMEDIATE value. Otherwise the result of the MUX2
//This module supprts to the excecution of sra instruction (if it is sra instruction and if immediate value... | 7.796484 |
module alu (
DATA1,
DATA2,
RESULT,
SELECT
);
/*This module executes a mux which selects the correct answer to be sent
* according to the 'SELECT' input*/
input [7:0] DATA1, DATA2; //These are the two inputs operand 1 and 2
input [2:0] SELECT; //This is the input whch indicates the operation to b... | 6.675659 |
module Forward (
operand,
result
);
/*This module assigns the value of the operand to the result*/
input [7:0] operand; //This is the input
output [7:0] result; //This is the output
assign result = operand;
endmodule
| 6.779622 |
module Add (
operand1,
operand2,
result
);
/*This module assigns the sum of operand 1 and 2 to the result*/
input [7:0] operand1, operand2; //These are the inputs
output [7:0] result; //This is the output
assign result = operand1 + operand2;
endmodule
| 7.896949 |
module And (
operand1,
operand2,
result
);
/*This module assigns the bitwise and of operand 1.2 to the result*/
input [7:0] operand1, operand2; //These are the inputs
output [7:0] result; //This is the output
assign result = operand1 & operand2;
endmodule
| 7.915974 |
module Or (
operand1,
operand2,
result
);
/*This module assigns the bitwise or of operand 1,2 to the result*/
input [7:0] operand1, operand2; //These are the inputs
output [7:0] result; //This is the input
assign result = operand1 | operand2;
endmodule
| 8.06812 |
module atomic_mux (
INPUT0,
INPUT1,
SELECT,
OUTPUT
);
//This is a simple 2to1 mux
input INPUT0,INPUT1,SELECT; //INPUT0 and INPUT1 are the inputs and SELECT is the selecting input
output reg OUTPUT; //OUTPUT is the output of the mux
always @* begin
if (SELECT) OUTPUT = INPUT1;
el... | 7.474683 |
module Mlt (
IN,
OPERAND,
OUTPUT
);
//This module generates the multiple of two given binary values
input [7:0] IN, OPERAND; //These are the two operands
output [7:0] OUTPUT; //This is the output
//These below wires are used to hold the outputs of AND gate layers
wire [7:0] o1, o2, o3, o4, o5, o... | 7.474758 |
module and_layer (
IN1,
IN2,
IN3,
IN4,
IN5,
IN6,
IN7,
IN8,
SELECT,
OUT1,
OUT2,
OUT3,
OUT4,
OUT5,
OUT6,
OUT7,
OUT8
);
//This is an AND gate layer which includes 8 parallel AND gates. A particular one input is common for all the gatese and rest are dif... | 6.923715 |
module ADD (
op1,
op2,
result
);
/*This module executes 8-Bit adding operation using fulladders*/
input [7:0] op1, op2; //These are two inputs,operand 1 and 2
output [7:0] result; //This is the outputs which sends the SUM
wire cout1,cout2,cout3,cout4,cout5,cout6,cout7,cout8; //These wires delivers... | 7.715009 |
module fulladder (
op1,
op2,
CarryIN,
Answer,
CarryOUT
);
//This module is a full adder which adds two bits
input op1,op2,CarryIN; //These are two operands and CarryIN is the carry in to the operation from previous operation
output Answer, CarryOUT; //These are the two outsouts answer and ca... | 7.454465 |
module reg_file (
IN,
OUT1,
OUT2,
INADDRESS,
OUT1ADDRESS,
OUT2ADDRESS,
WRITE,
CLK,
RESET
);
/*This module executes Register File which stores eight 8-bit values*/
input [2:0] INADDRESS,OUT1ADDRESS,OUT2ADDRESS; //These are inputs which takes addresses of registers
input [7:0] I... | 7.294051 |
module tagcmp (
tag1,
tag2,
isEqual
);
input [2:0] tag1, tag2;
output isEqual;
wire w1, w2, w3;
xnor g1 (w1, tag1[0], tag2[0]);
xnor g2 (w2, tag1[1], tag2[1]);
xnor g3 (w3, tag1[2], tag2[2]);
assign #0.9 isEqual = w1 && w2 && w3;
endmodule
| 7.353774 |
module selectionMUX (
ALLDATA,
select,
OUTDATA,
IsRead
);
input [31:0] ALLDATA;
input [1:0] select; // Address offset
input IsRead;
output reg [7:0] OUTDATA;
always @(*) begin
if (IsRead) begin
case (select)
2'b00: begin
#1 OUTDATA = ALLDATA[7:0];
end
... | 8.174491 |
module. This is one of the three queues used in
pingpangpungcontroller.v (refer to that file for details)
*/
module cpuqueue (
input wire clk,
input wire [1:0] token_from_sn,
input wire en_from_sn,
input wire deq,
output wire [1:0] head
);
reg [1:0] first = 0, second = 0, third = 0;
wire [1:0] first_n, sec... | 6.833535 |
module cpureg #(
parameter REGISTER_INITIAL_VALUE = 0
) (
input clk,
input [4:0] rd_addr0,
input [4:0] rd_addr1,
output [31:0] rd_rs1,
output [31:0] rd_rs2,
input [4:0] wr_addr,
input [31:0] wr_data,
input wr_en,
input o_next
);
reg [31:0] cpu_reg[0:31];
assign rd_rs1 = cpu... | 7.402371 |
module cpuregs (
input [5:0] raddr,
input [5:0] waddr,
input [15:0] d,
output [15:0] o,
input we,
input clk
);
// выделение памяти под регистровый файл
reg [15:0] regs[15:0];
// локальные адреса в массиве регистров
wire [3:0] loc_raddr;
wire [3:0] loc_waddr;
// Формат входящего ... | 6.77118 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module adder (
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
assign out = OUT(a, b);
function [31:0] OUT;
input [31:0] a, b;
begin
casex (b[31])
1'b1: begin
b = ~b;
b = b + 1'b1;
OUT = a - b;
end
default: OUT = a + b;
... | 7.4694 |
module alu (
a,
b,
aluctrl,
aluOut,
zero,
LSb_aluresult
);
input [31:0] a, b;
input [3:0] aluctrl;
output [31:0] aluOut;
output zero, LSb_aluresult;
reg [31:0] aluOut;
assign zero = (aluOut == 0) ? 1 : 0;
assign LSb_aluresult = aluOut[0];
always @(aluctrl or a or b)
casex (al... | 6.634214 |
module datapath (
clock,
reset_,
memtoreg,
regwrite,
aluControl,
instr,
readDataDMem,
zero,
pc,
aluOut,
readData2,
selBranch,
alusrcA,
alusrcB,
jump,
LSb_aluresult
);
input clock, reset_, memtoreg, selBranch, alusrcA, alusrcB, regwrite, jump;
input [3:... | 6.91752 |
module Cpu_testbench;
reg reset_;
initial begin
reset_ = 0;
#22 reset_ = 1;
#320 $stop;
end
reg clock;
initial clock = 0;
always #5 clock <= (!clock);
wire [31:0] PC, IR, D, Q, A, B, RESULT, SELBRANCH, ZERO, LSB, PCBRANCH, PCNEXT, PCMUX;
wire RESET;
assign PC = Cpu.mycore.DP.pc, IR = Cpu.... | 6.799952 |
module risc_v (
clock,
reset_
);
input clock, reset_;
wire memwrite;
wire [31:0] readDataDMem, instr, pc, aluOut, readData2;
core mycore (
clock,
reset_,
readDataDMem,
instr,
pc,
memwrite,
memread,
aluOut,
readData2
);
instructionMemory imem (
... | 6.579949 |
module datapath (
clock,
reset_,
memtoreg,
regwrite,
aluControl,
instr,
readDataDMem,
zero,
pc,
aluOut,
readData2,
selBranch,
alusrcA,
alusrcB,
jump,
LSb_aluresult
);
input clock, reset_, memtoreg, selBranch, alusrcA, alusrcB, regwrite, jump;
input [3:... | 6.91752 |
module regfile (
clock,
regWrite,
readReg1,
readReg2,
regDest,
writeData,
readData1,
readData2
);
input clock, regWrite;
input [4:0] readReg1, readReg2, regDest;
input [31:0] writeData;
output [31:0] readData1, readData2;
reg [31:0] readData1, readData2;
reg [31:0] regFile[0:... | 7.809308 |
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