code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adder (
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
assign out = OUT(a, b);
function [31:0] OUT;
input [31:0] a, b;
begin
casex (b[31])
1'b1: begin
b = ~b;
b = b + 1'b1;
OUT = a - b;
end
default: OUT = a + b;
... | 7.4694 |
module alu (
a,
b,
aluctrl,
aluOut,
zero,
LSb_aluresult
);
input [31:0] a, b;
input [3:0] aluctrl;
output [31:0] aluOut;
output zero, LSb_aluresult;
reg [31:0] aluOut;
assign zero = (aluOut == 0) ? 1 : 0;
assign LSb_aluresult = aluOut[0];
always @(aluctrl or a or b)
casex (al... | 6.634214 |
module FFD_resettable (
clock,
reset_,
d,
q
);
parameter WIDTH = 32;
input [WIDTH-1:0] d;
input clock, reset_;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clock)
#1.2
if (!reset_) q <= 0;
else q <= d;
endmodule
| 6.9624 |
module mux (
data0,
data1,
sel,
out
);
parameter WIDTH = 32;
input [WIDTH-1:0] data0, data1;
input sel;
output [WIDTH-1:0] out;
assign out = (sel == 1) ? data1 : data0;
endmodule
| 8.660487 |
module instructionMemory (
address,
readData
);
input [5:0] address;
output [31:0] readData;
reg [31:0] RAM[0:63];
initial $readmemh("factorial.dat", RAM);
assign readData = RAM[address];
endmodule
| 8.458827 |
module Cpu_testbench;
reg reset_;
initial begin
reset_ = 0;
#22 reset_ = 1;
#450 $stop;
end
reg clock;
initial clock = 0;
always #5 clock <= (!clock);
wire [31:0] PC, IR, D, Q, A, B, RESULT, SELBRANCH, ZERO, LSB, PCBRANCH, PCNEXT, PCMUX, R6;
wire RESET;
assign PC = Cpu.mycore.DP.pc, IR = ... | 6.799952 |
module risc_v (
clock,
reset_
);
input clock, reset_;
wire memwrite;
wire [31:0] readDataDMem, instr, pc, aluOut, readData2;
core mycore (
clock,
reset_,
readDataDMem,
instr,
pc,
memwrite,
memread,
aluOut,
readData2
);
instructionMemory imem (
... | 6.579949 |
module datapath (
clock,
reset_,
memtoreg,
regwrite,
aluControl,
instr,
readDataDMem,
zero,
pc,
aluOut,
readData2,
selBranch,
alusrcA,
alusrcB,
jump,
LSb_aluresult
);
input clock, reset_, memtoreg, selBranch, alusrcA, alusrcB, regwrite, jump;
input [3:... | 6.91752 |
module regfile (
clock,
regWrite,
readReg1,
readReg2,
regDest,
writeData,
readData1,
readData2
);
input clock, regWrite;
input [4:0] readReg1, readReg2, regDest;
input [31:0] writeData;
output [31:0] readData1, readData2;
reg [31:0] readData1, readData2;
reg [31:0] regFile[0:... | 7.809308 |
module adder (
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
assign out = OUT(a, b);
function [31:0] OUT;
input [31:0] a, b;
begin
casex (b[31])
1'b1: begin
b = ~b;
b = b + 1'b1;
OUT = a - b;
end
default: OUT = a + b;
... | 7.4694 |
module alu (
a,
b,
aluctrl,
aluOut,
zero,
LSb_aluresult
);
input [31:0] a, b;
input [3:0] aluctrl;
output [31:0] aluOut;
output zero, LSb_aluresult;
reg [31:0] aluOut;
assign zero = (aluOut == 0) ? 1 : 0;
assign LSb_aluresult = aluOut[0];
always @(aluctrl or a or b)
casex (al... | 6.634214 |
module FFD_resettable (
clock,
reset_,
d,
q
);
parameter WIDTH = 32;
input [WIDTH-1:0] d;
input clock, reset_;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clock)
#1.2
if (!reset_) q <= 0;
else q <= d;
endmodule
| 6.9624 |
module mux (
data0,
data1,
sel,
out
);
parameter WIDTH = 32;
input [WIDTH-1:0] data0, data1;
input sel;
output [WIDTH-1:0] out;
assign out = (sel == 1) ? data1 : data0;
endmodule
| 8.660487 |
module instructionMemory (
address,
readData
);
input [5:0] address;
output [31:0] readData;
reg [31:0] RAM[0:63];
initial $readmemh("summation.dat", RAM);
assign readData = RAM[address];
endmodule
| 8.458827 |
module Cpu_testbench;
reg reset_;
initial begin
reset_ = 0;
#22 reset_ = 1;
#140 $stop;
end
reg clock;
initial clock = 0;
always #5 clock <= (!clock);
wire [31:0] PC, IR, D, Q, A, B, RESULT, SELBRANCH, ZERO, LSB, PCBRANCH, PCNEXT, PCMUX;
wire RESET;
assign PC = Cpu.mycore.DP.pc, IR = Cpu.... | 6.799952 |
module risc_v (
clock,
reset_
);
input clock, reset_;
wire memwrite;
wire [31:0] readDataDMem, instr, pc, aluOut, readData2;
core mycore (
clock,
reset_,
readDataDMem,
instr,
pc,
memwrite,
memread,
aluOut,
readData2
);
instructionMemory imem (
... | 6.579949 |
module datapath (
clock,
reset_,
memtoreg,
regwrite,
aluControl,
instr,
readDataDMem,
zero,
pc,
aluOut,
readData2,
selBranch,
alusrcA,
alusrcB,
jump,
LSb_aluresult
);
input clock, reset_, memtoreg, selBranch, alusrcA, alusrcB, regwrite, jump;
input [3:... | 6.91752 |
module regfile (
clock,
regWrite,
readReg1,
readReg2,
regDest,
writeData,
readData1,
readData2
);
input clock, regWrite;
input [4:0] readReg1, readReg2, regDest;
input [31:0] writeData;
output [31:0] readData1, readData2;
reg [31:0] readData1, readData2;
reg [31:0] regFile[0:... | 7.809308 |
module adder (
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
assign out = OUT(a, b);
function [31:0] OUT;
input [31:0] a, b;
begin
casex (b[31])
1'b1: begin
b = ~b;
b = b + 1'b1;
OUT = a - b;
end
default: OUT = a + b;
... | 7.4694 |
module alu (
a,
b,
aluctrl,
aluOut,
zero,
LSb_aluresult
);
input [31:0] a, b;
input [3:0] aluctrl;
output [31:0] aluOut;
output zero, LSb_aluresult;
reg [31:0] aluOut;
assign zero = (aluOut == 0) ? 1 : 0;
assign LSb_aluresult = aluOut[0];
always @(aluctrl or a or b)
casex (al... | 6.634214 |
module FFD_resettable (
clock,
reset_,
d,
q
);
parameter WIDTH = 32;
input [WIDTH-1:0] d;
input clock, reset_;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clock)
#1.2
if (!reset_) q <= 0;
else q <= d;
endmodule
| 6.9624 |
module mux (
data0,
data1,
sel,
out
);
parameter WIDTH = 32;
input [WIDTH-1:0] data0, data1;
input sel;
output [WIDTH-1:0] out;
assign out = (sel == 1) ? data1 : data0;
endmodule
| 8.660487 |
module instructionMemory (
address,
readData
);
input [5:0] address;
output [31:0] readData;
reg [31:0] RAM[0:63];
initial $readmemh("test.dat", RAM);
assign readData = RAM[address];
endmodule
| 8.458827 |
module datapath (
clock,
reset_,
memtoreg,
regwrite,
aluControl,
instr,
readDataDMem,
zero,
pc,
aluOut,
readData2,
selBranch,
alusrcA,
alusrcB,
jump,
LSb_aluresult
);
input clock, reset_, memtoreg, selBranch, alusrcA, alusrcB, regwrite, jump;
input [3:... | 6.91752 |
module regfile (
clock,
regWrite,
readReg1,
readReg2,
regDest,
writeData,
readData1,
readData2
);
input clock, regWrite;
input [4:0] readReg1, readReg2, regDest;
input [31:0] writeData;
output [31:0] readData1, readData2;
reg [31:0] readData1, readData2;
reg [31:0] regFile[0:... | 7.809308 |
module adder (
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
assign out = OUT(a, b);
function [31:0] OUT;
input [31:0] a, b;
begin
casex (b[31])
1'b1: begin
b = ~b;
b = b + 1'b1;
OUT = a - b;
end
default: OUT = a + b;
... | 7.4694 |
module alu (
a,
b,
aluctrl,
aluOut,
zero,
LSb_aluresult
);
input [31:0] a, b;
input [3:0] aluctrl;
output [31:0] aluOut;
output zero, LSb_aluresult;
reg [31:0] aluOut;
assign zero = (aluOut == 0) ? 1 : 0;
assign LSb_aluresult = aluOut[0];
always @(aluctrl or a or b)
casex (al... | 6.634214 |
module FFD_resettable (
clock,
reset_,
d,
q
);
parameter WIDTH = 32;
input [WIDTH-1:0] d;
input clock, reset_;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clock)
#1.2
if (!reset_) q <= 0;
else q <= d;
endmodule
| 6.9624 |
module mux (
data0,
data1,
sel,
out
);
parameter WIDTH = 32;
input [WIDTH-1:0] data0, data1;
input sel;
output [WIDTH-1:0] out;
assign out = (sel == 1) ? data1 : data0;
endmodule
| 8.660487 |
module FFD_resettable (
clock,
reset_,
d,
q
);
parameter WIDTH = 32;
input [WIDTH-1:0] d;
input clock, reset_;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clock)
#1.2
if (!reset_) q <= 0;
else q <= d;
endmodule
| 6.9624 |
module instructionMemory (
address,
readData
);
input [5:0] address;
output [31:0] readData;
reg [31:0] RAM[0:63];
initial $readmemh("instruction_memory_testbench.dat", RAM);
assign readData = RAM[address];
endmodule
| 8.458827 |
module mux (
data0,
data1,
sel,
out
);
parameter WIDTH = 32;
input [WIDTH-1:0] data0, data1;
input sel;
output [WIDTH-1:0] out;
assign out = (sel == 1) ? data1 : data0;
endmodule
| 8.660487 |
module regfile (
clock,
regWrite,
readReg1,
readReg2,
regDest,
writeData,
readData1,
readData2
);
input clock, regWrite;
input [4:0] readReg1, readReg2, regDest;
input [31:0] writeData;
output [31:0] readData1, readData2;
reg [31:0] readData1, readData2;
reg [31:0] regFile[0:... | 7.809308 |
module CPUsc (
clk,
rst
); //single-cycle CPU
input clk;
input rst;
// wire addr;
wire [31:0] Instru;
wire [31:0] NPC;
wire [31:0] PC;
wire [31:0] A;
wire [31:0] B;
wire [31:0] C;
wire Zero;
wire [ 1:0] RegDst;
wire Memread;
wire [ 1:0] MemtoReg;
wire MemWr... | 6.876442 |
module CPUsc_tb (); //test-branch
reg clk;
reg rst;
CPUsc cpusc (
.clk(clk),
.rst(rst)
);
initial begin
clk = 0;
assign rst = 1;
#40 clk = 1;
assign rst = 0;
forever #20 clk = !clk;
#1000 $stop;
end
endmodule
| 6.544875 |
module cpusim ();
reg clk, rstn;
reg [15:0] SW;
reg [ 4:0] BTN_y;
initial begin
rstn = 0;
BTN_y[4:0] = 1;
SW[15:0] = 0;
#1020;
rstn = 1;
BTN_y[4:0] = 0;
#20;
end
always begin
clk = 1;
#10;
clk = 0;
#10;
end
CPU_SOC cpu (
.clk_100mhz(clk),
.RSTN(... | 6.973467 |
module CPUSubsys (
input acr_clk,
input acr_rst,
output [31:0] axi_awaddr,
output [3:0] axi_awlen,
output [2:0] axi_awsize,
output [1:0] axi_awburst,
output axi_awlock,
output [3:0] axi_awcache,
output [2:0] axi_awprot,
output axi_awvalid,
input axi_awready,
output [63:0]... | 6.946603 |
module: CPU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cpuTB;
// Inputs
reg Reset;
reg Clock;
// Outputs
wire [31:0] Result;
wire [31:0] Addr;
// Instantiate the Unit ... | 6.741629 |
module CPUultraProgRAM #(
parameter ADDRS_WIDTH = 12
) ( //"true" dual port RAM build from ultraRAM
CLK,
wren,
wraddrs,
wrdata,
rdenA,
rdaddrsA,
rddataA,
rdenB,
rdaddrsB,
rddataB
);
input CLK;
input wren;
input [ADDRS_WIDTH-1:0] wraddrs;
input [63:0] wrdata;
input... | 8.375142 |
module cpu_0_fpoint (
// inputs:
clk,
clk_en,
dataa,
datab,
n,
reset,
start,
// outputs:
done,
result
);
output done;
output [31:0] result;
input clk;
input clk_en;
input [31:0] dataa;
input [31:0] datab;
input [1:0] n;
input reset;
input start;
wire ... | 6.824042 |
module CPU_6502_tb ();
reg clk = 1'b0;
reg rst_n = 1'b1;
//inout [7:0] data_bus;
//wire [7:0] data_bus_read;
//reg [7:0] data_bus_write;
// If the CPU is reading (rw is high), data_bus takes the value of data_bus_write
//assign data_bus = rw ? data_bus_write : 8'bz;
wire [15:0] address_bus;
wire [... | 6.66394 |
module cpu_6502_uop_entry (
input [ 7:0] i_opcode,
output [10:0] o_uop_entry
);
assign o_uop_entry = {3'b0, i_opcode};
endmodule
| 6.618804 |
module cpu_alu (
input [ 6:0] funct7,
input [ 2:0] funct3,
input [ 6:0] opcode,
input [31:0] a,
input [31:0] b,
output [31:0] result
);
wire is_sub = funct7[5] & opcode[5];
wire [31:0] add_sub_result = a + (is_sub ? ~b : b) + is_sub;
wire [31:0] shift_left_result = a << b[4:0];
wir... | 7.98099 |
module Cpu_and_io (
input Reset,
Clock,
//output [31:0] IO_addr , IO_Result,
//IO
input BtnIn, //
output [7:0] seg, //7
output [5:0] AN_SEL,
output LED0,
LED1
);
reg [31:0] clockdiv = 0;
wire BtnOut;
wire ClkIn;
wire [31:0] PC;
wire [31:0] AluResu... | 6.65918 |
module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:35 Nathan
// Original from OpenCores
//
// Revision 1.4 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.3 2004... | 9.826408 |
module cpu_bfm_usbspi (
input wire spi_cs,
input wire spi_clk,
input wire spi_mosi,
output wire spi_miso,
input wire up_clk,
output wire up_wr,
output wire up_rd,
output wire [31:0] up_addr,
output wire [31:0] up_data_wr,
input wire [31:0] up_data_rd
);... | 7.99353 |
module decoder (
in,
out
);
// I/O port declarations
input [4:0] in;
output [31:0] out;
wire [4:0] nn;
not (nn[0], in[0]);
not (nn[1], in[1]);
not (nn[2], in[2]);
not (nn[3], in[3]);
not (nn[4], in[4]);
and (out[0], nn[4], nn[3], nn[2], nn[1], nn[0]);
and (out[1], nn[4], nn[3], nn[2], n... | 7.018254 |
module tristate (
in,
select,
out
);
// I/O declarations
input in, select;
output out;
tri out;
//Tristate buffer logic
bufif1 b1 (out, in, select);
endmodule
| 6.741184 |
module tristate_32 (
in,
select,
out
);
// I/O declarations
input [31:0] in;
input select;
output [31:0] out;
wire select_w;
assign select_w = select;
//Calling 1 bit tristate buffer module for each bit of byte
tristate t0 (
in[0],
select_w,
out[0]
);
tristate t1 (
... | 6.851376 |
module dreg_2bit (
d,
clk,
qout
);
input [1:0] d;
input clk;
output [1:0] qout;
dreg m0 (
d[0],
clk,
qout[0]
);
dreg m1 (
d[1],
clk,
qout[1]
);
endmodule
| 7.034823 |
module dreg_32bit (
d,
clk,
qout
);
// I/O port declarations
input [31:0] d;
input clk;
output [31:0] qout;
//Calling 1 bit D-register for each bit of byte
dreg me0 (
d[0],
clk,
qout[0]
);
dreg me1 (
d[1],
clk,
qout[1]
);
dreg me2 (
d[2],
c... | 6.819182 |
module mux2to1 (
in0,
in1,
outsel,
out
);
// I/O port declarations
input in0, in1, outsel;
output out;
assign out = outsel ? in1 : in0;
endmodule
| 7.107199 |
module memory_32bit (
sel_a,
sel_b,
sel_b_p,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input clk, sel_a, sel_b, sel_b_p;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] out, mux_out;
//Calling 8 bit 2to1 MUX module
mux2to1_32 m0 (
out,
a... | 8.178896 |
module memory_file (
in_a,
in_b,
in_bb,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input [4:0] in_a, in_b, in_bb;
input clk;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] sel_a, sel_b, sel_b_p;
//Decoding address line
decoder da (
in_a,
... | 6.848432 |
module memoryBlock (
addrA,
addrB,
Bback,
Out,
dataIn,
asel,
bsel,
clk,
outA,
outB
);
input [4:0] addrA, addrB, Bback;
input [31:0] dataIn, Out;
input asel, bsel, clk;
output [31:0] outA, outB;
wire [31:0] logic0 = 32'd0;
wire [31:0] out_a, out_b;
memory_file ram... | 7.272901 |
module and_32bit (
out,
in1,
in2
);
//Output variables
output [31:0] out;
//Input variables
input [31:0] in1, in2;
//AND logic for 8 bit
and a1[31:0] (out, in1, in2);
endmodule
| 7.109306 |
module logic_fn (
OUT_FN,
A,
B,
SEL
);
//Output variables
output [31:0] OUT_FN;
//Input variables
input [31:0] A, B;
input [1:0] SEL;
//Wire
wire [31:0] OUT_XOR, OUT_XNOR, OUT_OR, OUT_AND;
reg [31:0] OUT_FN;
//Calling XOR, XNOR, OR, AND 8 BIT LOGIC MODULES
xor_32bit value (
OUT... | 6.684973 |
module fa (
sum,
c_out,
a,
b,
c_in
);
// I/O port declarations
input a, b, c_in;
output sum, c_out;
// internal nets
wire s1, c1, c2;
// instant logic gate primitives
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
xor (c_out, c2, c1);
endmodule
| 7.378012 |
module pfa (
s,
a,
b,
c,
p,
g
);
output s, p, g;
input a, b, c;
assign s = a ^ b ^ c;
assign p = a ^ b; //propagate of 1-bit pfa
assign g = a & b; //generate of 1-bit pfa
endmodule
| 7.839039 |
module of 1-bit pfa
module carry(cout, p_in, g_in, cin);
output cout;
input p_in, g_in;
input cin;
assign cout = (cin & p_in) | g_in;
endmodule
| 7.474047 |
module carrylookahead_4 (
s,
c4,
g_4,
p_4,
over,
a,
b,
c0
);
output [3:0] s;
output g_4, p_4; //g0_3, p0_3
output c4, over;
input [3:0] a, b;
input c0;
wire c1, c2, c3;
wire [3:0] p, g;
pfa pfa0 (
.s(s[0]),
.a(a[0]),
.b(b[0]),
.c(c0),
.p(... | 6.775787 |
module carrylookahead_16 (
s,
c16,
g_16,
p_16,
over,
a,
b,
c0
);
output [15:0] s;
output g_16, p_16;
output c16, over;
input [15:0] a, b;
input c0;
wire c4, c8, c12;
//wire [3:0] s3_0, s7_4, s11_8, s15_12;
wire [3:0] p, g;
carrylookahead_4 CLA0 (
.s (s[3:0]),
... | 6.775787 |
module ha (
sum,
c_out,
a,
b
);
input a, b;
output sum, c_out;
xor (sum, a, b);
and (c_out, a, b);
endmodule
| 7.11979 |
module alu (
aluout,
a,
b,
opsel,
outsel,
clk,
over
);
//Output variables
output [31:0] aluout;
output over;
//Input variables
input [31:0] a, b;
input [1:0] opsel, outsel;
input clk;
reg [31:0] aluout;
//Wire
wire [31:0] OUT_LOGIC, OUT_ADD_SUB, OUT_MUL_MSB, OUT_MUL_LSB... | 7.145461 |
module writeBackAddr (
addressB,
clk,
addrB
);
input [4:0] addressB;
input clk;
output [4:0] addrB;
//wire [4:0] addrB;
dreg_5bit bd (
addressB,
clk,
addrB
);
endmodule
| 7.179553 |
module ALUoperation (
opsel,
outsel,
oen,
clk,
OPSEL,
OUTSEL,
OEN
);
input clk, oen;
input [1:0] opsel, outsel;
output [1:0] OPSEL, OUTSEL;
output OEN;
//reg [1:0] OPSEL, OUTSEL;
dreg_2bit ops (
opsel,
clk,
OPSEL
);
dreg_2bit outs (
outsel,
clk... | 7.540537 |
module cpu_clock ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
//IBUFG clkin1_buf
// (.O (clkin1),
// .I (CLK_IN1));
// Clocking primitive
//---------... | 7.034229 |
module decoder (
in,
out
);
// I/O port declarations
input [4:0] in;
output [31:0] out;
wire [4:0] nn;
not (nn[0], in[0]);
not (nn[1], in[1]);
not (nn[2], in[2]);
not (nn[3], in[3]);
not (nn[4], in[4]);
and (out[0], nn[4], nn[3], nn[2], nn[1], nn[0]);
and (out[1], nn[4], nn[3], nn[2], n... | 7.018254 |
module tristate (
in,
select,
out
);
// I/O declarations
input in, select;
output out;
tri out;
//Tristate buffer logic
bufif1 b1 (out, in, select);
endmodule
| 6.741184 |
module tristate_32 (
in,
select,
out
);
// I/O declarations
input [31:0] in;
input select;
output [31:0] out;
wire select_w;
assign select_w = select;
//Calling 1 bit tristate buffer module for each bit of byte
tristate t0 (
in[0],
select_w,
out[0]
);
tristate t1 (
... | 6.851376 |
module dreg_2bit (
d,
clk,
qout
);
input [1:0] d;
input clk;
output [1:0] qout;
dreg m0 (
d[0],
clk,
qout[0]
);
dreg m1 (
d[1],
clk,
qout[1]
);
endmodule
| 7.034823 |
module dreg_3bit (
d,
clk,
qout
);
input [2:0] d;
input clk;
output [2:0] qout;
dreg m0 (
d[0],
clk,
qout[0]
);
dreg m1 (
d[1],
clk,
qout[1]
);
dreg m2 (
d[2],
clk,
qout[2]
);
endmodule
| 6.798589 |
module dreg_32bit (
d,
clk,
qout
);
// I/O port declarations
input [31:0] d;
input clk;
output [31:0] qout;
//Calling 1 bit D-register for each bit of byte
dreg me0 (
d[0],
clk,
qout[0]
);
dreg me1 (
d[1],
clk,
qout[1]
);
dreg me2 (
d[2],
c... | 6.819182 |
module mux2to1 (
in0,
in1,
outsel,
out
);
// I/O port declarations
input in0, in1, outsel;
output out;
assign out = outsel ? in1 : in0;
endmodule
| 7.107199 |
module memory_32bit (
sel_a,
sel_b,
sel_b_p,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input clk, sel_a, sel_b, sel_b_p;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] out, mux_out;
//Calling 8 bit 2to1 MUX module
mux2to1_32 m0 (
out,
a... | 8.178896 |
module memory_file (
in_a,
in_b,
in_bb,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input [4:0] in_a, in_b, in_bb;
input clk;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] sel_a, sel_b, sel_b_p;
//Decoding address line
decoder da (
in_a,
... | 6.848432 |
module memoryBlock (
addrA,
addrB,
Bback,
Out,
dataIn,
asel,
bsel,
clk,
outA,
outB
);
input [4:0] addrA, addrB, Bback;
input [31:0] dataIn, Out;
input asel, bsel, clk;
output [31:0] outA, outB;
wire [31:0] logic0 = 32'd0;
wire [31:0] out_a, out_b;
memory_file ram... | 7.272901 |
module and_32bit (
out,
in1,
in2
);
//Output variables
output [31:0] out;
//Input variables
input [31:0] in1, in2;
//AND logic for 8 bit
and a1[31:0] (out, in1, in2);
endmodule
| 7.109306 |
module logic_fn (
OUT_FN,
A,
B,
SEL
);
//Output variables
output [31:0] OUT_FN;
//Input variables
input [31:0] A, B;
input [1:0] SEL;
//Wire
wire [31:0] OUT_XOR, OUT_XNOR, OUT_OR, OUT_AND;
reg [31:0] OUT_FN;
//Calling XOR, XNOR, OR, AND 8 BIT LOGIC MODULES
xor_32bit value (
OUT... | 6.684973 |
module fa (
sum,
c_out,
a,
b,
c_in
);
// I/O port declarations
input a, b, c_in;
output sum, c_out;
// internal nets
wire s1, c1, c2;
// instant logic gate primitives
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
xor (c_out, c2, c1);
endmodule
| 7.378012 |
module pfa (
s,
a,
b,
c,
p,
g
);
output s, p, g;
input a, b, c;
assign s = a ^ b ^ c;
assign p = a ^ b; //propagate of 1-bit pfa
assign g = a & b; //generate of 1-bit pfa
endmodule
| 7.839039 |
module of 1-bit pfa
module carry(cout, p_in, g_in, cin);
output cout;
input p_in, g_in;
input cin;
assign cout = (cin & p_in) | g_in;
endmodule
| 7.474047 |
module carrylookahead_4 (
s,
c4,
g_4,
p_4,
over,
a,
b,
c0
);
output [3:0] s;
output g_4, p_4; //g0_3, p0_3
output c4, over;
input [3:0] a, b;
input c0;
wire c1, c2, c3;
wire [3:0] p, g;
pfa pfa0 (
.s(s[0]),
.a(a[0]),
.b(b[0]),
.c(c0),
.p(... | 6.775787 |
module carrylookahead_16 (
s,
c16,
g_16,
p_16,
over,
a,
b,
c0
);
output [15:0] s;
output g_16, p_16;
output c16, over;
input [15:0] a, b;
input c0;
wire c4, c8, c12;
//wire [3:0] s3_0, s7_4, s11_8, s15_12;
wire [3:0] p, g;
carrylookahead_4 CLA0 (
.s (s[3:0]),
... | 6.775787 |
module ha (
sum,
c_out,
a,
b
);
input a, b;
output sum, c_out;
xor (sum, a, b);
and (c_out, a, b);
endmodule
| 7.11979 |
module alu (
aluout,
a,
b,
opsel,
outsel,
clk,
over
);
//Output variables
output [31:0] aluout;
output over;
//Input variables
input [31:0] a, b;
input [1:0] opsel;
input [2:0] outsel;
input clk;
reg [31:0] aluout;
//Wire
wire [31:0] OUT_LOGIC, OUT_ADD_SUB, OUT_MUL_MS... | 7.145461 |
module writeBackAddr (
addressB,
clk,
addrB
);
input [4:0] addressB;
input clk;
output [4:0] addrB;
//wire [4:0] addrB;
dreg_5bit bd (
addressB,
clk,
addrB
);
endmodule
| 7.179553 |
module ALUoperation (
opsel,
outsel,
oen,
clk,
OPSEL,
OUTSEL,
OEN
);
input clk, oen;
input [1:0] opsel;
input [2:0] outsel;
output [1:0] OPSEL;
output [2:0] OUTSEL;
output OEN;
dreg_2bit ops (
opsel,
clk,
OPSEL
);
dreg_3bit outs (
outsel,
clk... | 7.540537 |
modules to add Comparator in the ALU//
// //
// Please check the "//write your code here" part in the source //
// //
////////////////////////////////////////////////////////////////////////////////
//one bit comparator
module one_bit_comp(a, b, f1, f0);
input a, b;
output f1,... | 8.145902 |
module tree_comp (
A,
B,
f1,
f0
);
input [31 : 0] A, B;
output f1, f0;
wire [31 : 0] f1_L5, f0_L5;
wire [15 : 0] f1_L4, f0_L4;
wire [7 : 0] f1_L3, f0_L3;
wire [3 : 0] f1_L2, f0_L2;
wire [1 : 0] f1_L1, f0_L1;
//write your code here
//Level 5: 32 one_bit_comp go here
//Level 4: 16 ... | 6.762697 |
module address_mux #(
parameter WIDTH = 5
) (
input [WIDTH - 1 : 0] in0,
input [WIDTH - 1 : 0] in1,
input sel,
output [WIDTH - 1 : 0] out
);
assign out = (sel) ? in1 : in0;
endmodule
| 7.996417 |
module bus_driver #(
parameter WIDTH = 8
) (
input [WIDTH - 1 : 0] data_in,
input data_en,
output [WIDTH - 1 : 0] data_out
);
assign data_out = (data_en) ? data_in : {WIDTH{1'hz}};
endmodule
| 7.269292 |
module alu #(
parameter WIDTH = 8
) (
input [WIDTH - 1 : 0] in_a,
input [WIDTH - 1 : 0] in_b,
input [$clog2(WIDTH) -1 : 0] opcode,
output [WIDTH - 1 : 0] alu_out,
output a_is_zero
);
reg [WIDTH - 1 : 0] result;
always @(in_a, in_b, opcode) begin
case (opcode)
3'b000: result = ... | 6.7799 |
module register #(
parameter WIDTH = 8
) (
input clk,
input rst,
input [WIDTH - 1 : 0] data_in,
input load,
output [WIDTH - 1 : 0] data_out
);
reg [WIDTH - 1 : 0] data_out_;
always @(posedge clk) begin
if (rst) data_out_ <= {WIDTH{1'b0}};
else begin
if (load) data_out_ <= dat... | 8.732583 |
module memory #(
parameter A_WIDTH = 5,
D_WIDTH = 8
) (
input clk,
input wr,
input rd,
input [A_WIDTH -1 : 0] addr,
inout [D_WIDTH -1 : 0] data
);
reg [D_WIDTH -1 : 0] data_;
reg [D_WIDTH - 1 : 0] mem[2**A_WIDTH -1 : 0];
always @(posedge clk) begin
if (wr) mem[addr] <= data_;
... | 8.490316 |
module CPU_Controller (
SW1,
SW2,
CPU_state
);
input SW1, SW2;
output [1:0] CPU_state;
assign CPU_state = {SW2, SW1};
endmodule
| 7.385311 |
module decoder (
in,
out
);
// I/O port declarations
input [4:0] in;
output [31:0] out;
wire [4:0] nn;
not (nn[0], in[0]);
not (nn[1], in[1]);
not (nn[2], in[2]);
not (nn[3], in[3]);
not (nn[4], in[4]);
and (out[0], nn[4], nn[3], nn[2], nn[1], nn[0]);
and (out[1], nn[4], nn[3], nn[2], n... | 7.018254 |
module tristate (
in,
select,
out
);
// I/O declarations
input in, select;
output out;
tri out;
//Tristate buffer logic
bufif1 b1 (out, in, select);
endmodule
| 6.741184 |
module tristate_32 (
in,
select,
out
);
// I/O declarations
input [31:0] in;
input select;
output [31:0] out;
wire select_w;
assign select_w = select;
//Calling 1 bit tristate buffer module for each bit of byte
tristate t0 (
in[0],
select_w,
out[0]
);
tristate t1 (
... | 6.851376 |
module dreg_2bit (
d,
clk,
qout
);
input [1:0] d;
input clk;
output [1:0] qout;
dreg m0 (
d[0],
clk,
qout[0]
);
dreg m1 (
d[1],
clk,
qout[1]
);
endmodule
| 7.034823 |
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