code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dreg_32bit (
d,
clk,
qout
);
// I/O port declarations
input [31:0] d;
input clk;
output [31:0] qout;
//Calling 1 bit D-register for each bit of byte
dreg me0 (
d[0],
clk,
qout[0]
);
dreg me1 (
d[1],
clk,
qout[1]
);
dreg me2 (
d[2],
c... | 6.819182 |
module mux2to1 (
in0,
in1,
outsel,
out
);
// I/O port declarations
input in0, in1, outsel;
output out;
assign out = outsel ? in1 : in0;
endmodule
| 7.107199 |
module memory_32bit (
sel_a,
sel_b,
sel_b_p,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input clk, sel_a, sel_b, sel_b_p;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] out, mux_out;
//Calling 8 bit 2to1 MUX module
mux2to1_32 m0 (
out,
a... | 8.178896 |
module memory_file (
in_a,
in_b,
in_bb,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input [4:0] in_a, in_b, in_bb;
input clk;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] sel_a, sel_b, sel_b_p;
//Decoding address line
decoder da (
in_a,
... | 6.848432 |
module memoryBlock (
addrA,
addrB,
Bback,
Out,
dataIn,
asel,
bsel,
clk,
outA,
outB
);
input [4:0] addrA, addrB, Bback;
input [31:0] dataIn, Out;
input asel, bsel, clk;
output [31:0] outA, outB;
wire [31:0] logic0 = 32'd0;
wire [31:0] out_a, out_b;
memory_file ram... | 7.272901 |
module and_32bit (
out,
in1,
in2
);
//Output variables
output [31:0] out;
//Input variables
input [31:0] in1, in2;
//AND logic for 8 bit
and a1[31:0] (out, in1, in2);
endmodule
| 7.109306 |
module logic_fn (
OUT_FN,
A,
B,
SEL
);
//Output variables
output [31:0] OUT_FN;
//Input variables
input [31:0] A, B;
input [1:0] SEL;
//Wire
wire [31:0] OUT_XOR, OUT_XNOR, OUT_OR, OUT_AND;
reg [31:0] OUT_FN;
//Calling XOR, XNOR, OR, AND 8 BIT LOGIC MODULES
xor_32bit value (
OUT... | 6.684973 |
module fa (
sum,
c_out,
a,
b,
c_in
);
// I/O port declarations
input a, b, c_in;
output sum, c_out;
// internal nets
wire s1, c1, c2;
// instant logic gate primitives
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
xor (c_out, c2, c1);
endmodule
| 7.378012 |
module fa8 (
sum,
c_out,
over,
a,
b,
c_in
);
// I/O port declaration
output [7:0] sum;
output c_out, over;
input [7:0] a, b;
input c_in;
//internal nets
wire c1, c2, c3, c4, c5, c6, c7;
//instantiate eight 1-bit full adders
fa f0 (
sum[0],
c1,
a[0],
b... | 6.74702 |
module fa32 (
sum,
c_out,
over,
a,
b,
c_in
);
output [31:0] sum;
output c_out, over;
input c_in;
input [31:0] a, b;
wire c7, c15, c23;
fa8 cra0 (
.sum(sum[7:0]),
.c_out(c7),
.a(a[7:0]),
.b(b[7:0]),
.c_in(c_in)
);
fa8 cra1 (
.sum(sum[15:8]),
... | 6.792713 |
module ha (
sum,
c_out,
a,
b
);
input a, b;
output sum, c_out;
xor (sum, a, b);
and (c_out, a, b);
endmodule
| 7.11979 |
module alu (
aluout,
a,
b,
opsel,
outsel,
clk,
over
);
//Output variables
output [31:0] aluout;
output over;
//Input variables
input [31:0] a, b;
input [1:0] opsel, outsel;
input clk;
reg [31:0] aluout;
//Wire
wire [31:0] OUT_LOGIC, OUT_ADD_SUB, OUT_MUL_MSB, OUT_MUL_LSB... | 7.145461 |
module writeBackAddr (
addressB,
clk,
addrB
);
input [4:0] addressB;
input clk;
output [4:0] addrB;
//wire [4:0] addrB;
dreg_5bit bd (
addressB,
clk,
addrB
);
endmodule
| 7.179553 |
module ALUoperation (
opsel,
outsel,
oen,
clk,
OPSEL,
OUTSEL,
OEN
);
input clk, oen;
input [1:0] opsel, outsel;
output [1:0] OPSEL, OUTSEL;
output OEN;
//reg [1:0] OPSEL, OUTSEL;
dreg_2bit ops (
opsel,
clk,
OPSEL
);
dreg_2bit outs (
outsel,
clk... | 7.540537 |
module decoder (
in,
out
);
// I/O port declarations
input [4:0] in;
output [31:0] out;
wire [4:0] nn;
not (nn[0], in[0]);
not (nn[1], in[1]);
not (nn[2], in[2]);
not (nn[3], in[3]);
not (nn[4], in[4]);
and (out[0], nn[4], nn[3], nn[2], nn[1], nn[0]);
and (out[1], nn[4], nn[3], nn[2], n... | 7.018254 |
module tristate (
in,
select,
out
);
// I/O declarations
input in, select;
output out;
tri out;
//Tristate buffer logic
bufif1 b1 (out, in, select);
endmodule
| 6.741184 |
module tristate_32 (
in,
select,
out
);
// I/O declarations
input [31:0] in;
input select;
output [31:0] out;
wire select_w;
assign select_w = select;
//Calling 1 bit tristate buffer module for each bit of byte
tristate t0 (
in[0],
select_w,
out[0]
);
tristate t1 (
... | 6.851376 |
module dreg_2bit (
d,
clk,
qout
);
input [1:0] d;
input clk;
output [1:0] qout;
dreg m0 (
d[0],
clk,
qout[0]
);
dreg m1 (
d[1],
clk,
qout[1]
);
endmodule
| 7.034823 |
module dreg_32bit (
d,
clk,
qout
);
// I/O port declarations
input [31:0] d;
input clk;
output [31:0] qout;
//Calling 1 bit D-register for each bit of byte
dreg me0 (
d[0],
clk,
qout[0]
);
dreg me1 (
d[1],
clk,
qout[1]
);
dreg me2 (
d[2],
c... | 6.819182 |
module mux2to1 (
in0,
in1,
outsel,
out
);
// I/O port declarations
input in0, in1, outsel;
output out;
assign out = outsel ? in1 : in0;
endmodule
| 7.107199 |
module memory_32bit (
sel_a,
sel_b,
sel_b_p,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input clk, sel_a, sel_b, sel_b_p;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] out, mux_out;
//Calling 8 bit 2to1 MUX module
mux2to1_32 m0 (
out,
a... | 8.178896 |
module memory_file (
in_a,
in_b,
in_bb,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input [4:0] in_a, in_b, in_bb;
input clk;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] sel_a, sel_b, sel_b_p;
//Decoding address line
decoder da (
in_a,
... | 6.848432 |
module memoryBlock (
addrA,
addrB,
Bback,
Out,
dataIn,
asel,
bsel,
clk,
outA,
outB
);
input [4:0] addrA, addrB, Bback;
input [31:0] dataIn, Out;
input asel, bsel, clk;
output [31:0] outA, outB;
wire [31:0] logic0 = 32'd0;
wire [31:0] out_a, out_b;
memory_file ram... | 7.272901 |
module and_32bit (
out,
in1,
in2
);
//Output variables
output [31:0] out;
//Input variables
input [31:0] in1, in2;
//AND logic for 8 bit
and a1[31:0] (out, in1, in2);
endmodule
| 7.109306 |
module logic_fn (
OUT_FN,
A,
B,
SEL
);
//Output variables
output [31:0] OUT_FN;
//Input variables
input [31:0] A, B;
input [1:0] SEL;
//Wire
wire [31:0] OUT_XOR, OUT_XNOR, OUT_OR, OUT_AND;
reg [31:0] OUT_FN;
//Calling XOR, XNOR, OR, AND 8 BIT LOGIC MODULES
xor_32bit value (
OUT... | 6.684973 |
module fa (
sum,
c_out,
a,
b,
c_in
);
// I/O port declarations
input a, b, c_in;
output sum, c_out;
// internal nets
wire s1, c1, c2;
// instant logic gate primitives
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
xor (c_out, c2, c1);
endmodule
| 7.378012 |
module CSA_4 (
s,
cout,
c_over_1,
c_over_2,
a,
b,
cin
); // 4-bit carry-skip adder
output cout, c_over_1, c_over_2;
output [3:0] s;
input cin;
input [3:0] a, b;
wire [3:0] c;
wire bp;
fa cs0 (
.sum(s[0]),
.c_out(c[0]),
.a(a[0]),
.b(b[0]),
.c_in... | 6.782871 |
module CSA_16 (
s,
cout,
c_over_1,
c_over_2,
a,
b,
cin
); //16-bit carry-skip adder
output cout, c_over_1, c_over_2;
output [15:0] s;
input cin;
input [15:0] a, b;
wire [2:0] c;
CSA_4 cs0_3 (
.s(s[3:0]),
.cout(c[0]),
.a(a[3:0]),
.b(b[3:0]),
.cin(c... | 6.969422 |
module CSA_32 (
s,
cout,
over,
a,
b,
cin
); //32-bit carry-skip adder
output cout, over;
output [31:0] s;
input cin;
input [31:0] a, b;
wire c;
wire bp, c_over_1, c_over_2;
CSA_16 cs0_15 (
.s(s[15:0]),
.cout(c),
.a(a[15:0]),
.b(b[15:0]),
.cin(cin)
... | 7.144556 |
module ha (
sum,
c_out,
a,
b
);
input a, b;
output sum, c_out;
xor (sum, a, b);
and (c_out, a, b);
endmodule
| 7.11979 |
module alu (
aluout,
a,
b,
opsel,
outsel,
clk,
over
);
//Output variables
output [31:0] aluout;
output over;
//Input variables
input [31:0] a, b;
input [1:0] opsel, outsel;
input clk;
reg [31:0] aluout;
//Wire
wire [31:0] OUT_LOGIC, OUT_ADD_SUB, OUT_MUL_MSB, OUT_MUL_LSB... | 7.145461 |
module writeBackAddr (
addressB,
clk,
addrB
);
input [4:0] addressB;
input clk;
output [4:0] addrB;
//wire [4:0] addrB;
dreg_5bit bd (
addressB,
clk,
addrB
);
endmodule
| 7.179553 |
module ALUoperation (
opsel,
outsel,
oen,
clk,
OPSEL,
OUTSEL,
OEN
);
input clk, oen;
input [1:0] opsel, outsel;
output [1:0] OPSEL, OUTSEL;
output OEN;
//reg [1:0] OPSEL, OUTSEL;
dreg_2bit ops (
opsel,
clk,
OPSEL
);
dreg_2bit outs (
outsel,
clk... | 7.540537 |
module decoder (
in,
out
);
// I/O port declarations
input [4:0] in;
output [31:0] out;
wire [4:0] nn;
not (nn[0], in[0]);
not (nn[1], in[1]);
not (nn[2], in[2]);
not (nn[3], in[3]);
not (nn[4], in[4]);
and (out[0], nn[4], nn[3], nn[2], nn[1], nn[0]);
and (out[1], nn[4], nn[3], nn[2], n... | 7.018254 |
module tristate (
in,
select,
out
);
// I/O declarations
input in, select;
output out;
tri out;
//Tristate buffer logic
bufif1 b1 (out, in, select);
endmodule
| 6.741184 |
module tristate_32 (
in,
select,
out
);
// I/O declarations
input [31:0] in;
input select;
output [31:0] out;
wire select_w;
assign select_w = select;
//Calling 1 bit tristate buffer module for each bit of byte
tristate t0 (
in[0],
select_w,
out[0]
);
tristate t1 (
... | 6.851376 |
module dreg_2bit (
d,
clk,
qout
);
input [1:0] d;
input clk;
output [1:0] qout;
dreg m0 (
d[0],
clk,
qout[0]
);
dreg m1 (
d[1],
clk,
qout[1]
);
endmodule
| 7.034823 |
module dreg_32bit (
d,
clk,
qout
);
// I/O port declarations
input [31:0] d;
input clk;
output [31:0] qout;
//Calling 1 bit D-register for each bit of byte
dreg me0 (
d[0],
clk,
qout[0]
);
dreg me1 (
d[1],
clk,
qout[1]
);
dreg me2 (
d[2],
c... | 6.819182 |
module mux2to1 (
in0,
in1,
outsel,
out
);
// I/O port declarations
input in0, in1, outsel;
output out;
assign out = outsel ? in1 : in0;
endmodule
| 7.107199 |
module memory_32bit (
sel_a,
sel_b,
sel_b_p,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input clk, sel_a, sel_b, sel_b_p;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] out, mux_out;
//Calling 8 bit 2to1 MUX module
mux2to1_32 m0 (
out,
a... | 8.178896 |
module memory_file (
in_a,
in_b,
in_bb,
clk,
alu_out,
out_a,
out_b
);
// I/O port declarations
input [4:0] in_a, in_b, in_bb;
input clk;
input [31:0] alu_out;
output [31:0] out_a, out_b;
wire [31:0] sel_a, sel_b, sel_b_p;
//Decoding address line
decoder da (
in_a,
... | 6.848432 |
module memoryBlock (
addrA,
addrB,
Bback,
Out,
dataIn,
asel,
bsel,
clk,
outA,
outB
);
input [4:0] addrA, addrB, Bback;
input [31:0] dataIn, Out;
input asel, bsel, clk;
output [31:0] outA, outB;
wire [31:0] logic0 = 32'd0;
wire [31:0] out_a, out_b;
memory_file ram... | 7.272901 |
module and_32bit (
out,
in1,
in2
);
//Output variables
output [31:0] out;
//Input variables
input [31:0] in1, in2;
//AND logic for 8 bit
and a1[31:0] (out, in1, in2);
endmodule
| 7.109306 |
module logic_fn (
OUT_FN,
A,
B,
SEL
);
//Output variables
output [31:0] OUT_FN;
//Input variables
input [31:0] A, B;
input [1:0] SEL;
//Wire
wire [31:0] OUT_XOR, OUT_XNOR, OUT_OR, OUT_AND;
reg [31:0] OUT_FN;
//Calling XOR, XNOR, OR, AND 8 BIT LOGIC MODULES
xor_32bit value (
OUT... | 6.684973 |
module fa (
sum,
c_out,
a,
b,
c_in
);
// I/O port declarations
input a, b, c_in;
output sum, c_out;
// internal nets
wire s1, c1, c2;
// instant logic gate primitives
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
xor (c_out, c2, c1);
endmodule
| 7.378012 |
module CSeA_4 (
s,
cout,
over,
a,
b,
cin
); //4-bit carry-select adder
output cout, over;
output [3:0] s;
input cin;
input [3:0] a, b;
wire [3:0] s_h, s_l;
wire [3:0] c_h, c_l;
wire cout_h, cout_l;
assign c_l[0] = 1'b0;
assign c_h[0] = 1'b1;
fa l_a0 (
.sum(s_l[0])... | 7.479041 |
module CSeA_16 (
s,
cout,
over,
a,
b,
cin
); //16-bit carry-select adder
output cout, over;
output [15:0] s;
input cin;
input [15:0] a, b;
wire [3:0] c;
CSeA_4 c1 (
.s(s[3:0]),
.cout(c[1]),
.a(a[3:0]),
.b(b[3:0]),
.cin(cin)
);
CSeA_4 c2 (
.s... | 7.516606 |
module CSeA_32 (
s,
cout,
over,
a,
b,
cin
); //32-bit carry-select adder
output cout, over;
output [31:0] s;
input cin;
input [31:0] a, b;
wire c;
CSeA_16 cse1 (
.s(s[15:0]),
.cout(c),
.a(a[15:0]),
.b(b[15:0]),
.cin(cin)
);
CSeA_16 cse2 (
.s... | 8.096041 |
module ha (
sum,
c_out,
a,
b
);
input a, b;
output sum, c_out;
xor (sum, a, b);
and (c_out, a, b);
endmodule
| 7.11979 |
module alu (
aluout,
a,
b,
opsel,
outsel,
clk,
over
);
//Output variables
output [31:0] aluout;
output over;
//Input variables
input [31:0] a, b;
input [1:0] opsel, outsel;
input clk;
reg [31:0] aluout;
//Wire
wire [31:0] OUT_LOGIC, OUT_ADD_SUB, OUT_MUL_MSB, OUT_MUL_LSB... | 7.145461 |
module writeBackAddr (
addressB,
clk,
addrB
);
input [4:0] addressB;
input clk;
output [4:0] addrB;
//wire [4:0] addrB;
dreg_5bit bd (
addressB,
clk,
addrB
);
endmodule
| 7.179553 |
module ALUoperation (
opsel,
outsel,
oen,
clk,
OPSEL,
OUTSEL,
OEN
);
input clk, oen;
input [1:0] opsel, outsel;
output [1:0] OPSEL, OUTSEL;
output OEN;
//reg [1:0] OPSEL, OUTSEL;
dreg_2bit ops (
opsel,
clk,
OPSEL
);
dreg_2bit outs (
outsel,
clk... | 7.540537 |
module CPU_Ctr (
input wire [31:0] instruction,
output wire regdst_flag,
output wire [ 1:0] jump_flag,
output wire [ 1:0] branch_flag,
output wire memread_flag,
output wire memtoReg_flag,
output wire [ 1:0] ALUOp,
output wire memwrite_flag,
output wire ... | 6.784965 |
module cpu_dataflow (
input clk,
rst,
input [31:0] Inst,
MemOut,
RegWriteData,
output [31:0] pc,
Read2,
ALUOut,
output [1:0] MemWrite
);
wire [1:0] RegDst, NPCOp, MemtoReg;
wire [2:0] RegWrite;
wire ALUsrc1, ALUsrc2, EXTOp;
wire [3:0] ALUOp;
wire Zero, Sign, BranchZ;
wir... | 7.223468 |
module CPU_Datapath (
input clk,
input [15:0] M,
input [15:0] ins,
input [6:0] ctrlWord,
output [15:0] ALU_out,
output [14:0] A_value,
output [14:0] PC_out,
output zr,
ng
);
wire A_or_C, A_or_M, loadA, loadD, loadPC, PC_inc, PC_rst;
wire [15:0] inA, inD, outA, outD, ALU_x, ALU_y,... | 7.304045 |
modulename>cpu_data_transmitter</modulename>
/// <filedescription>CPU ݴ</filedescription>
/// <version>
/// 0.0.1 (UnnamedOrange) : First commit.
/// 0.0.2 (UnnamedOrange) : СΪͬ
/// 0.0.3 (UnnamedOrange) : һЩ
/// 0.0.4 (UnnamedOrange) : ˵ģʽʹµı롣
/// 0.0.5 (UnnamedOrange) : źŵΪͬġ
/// 0.0.6 (UnnamedOrange) : ֹ RESTART ... | 6.519907 |
modulename>cpu_data_transmitter_v1_0</modulename>
/// <filedescription>CPU ݴ</filedescription>
/// <version>
/// 0.0.1 (UnnamedOrange) : First commit.
/// </version>
`timescale 1 ns / 1 ps
module cpu_data_transmitter_v1_0 #
(
// Users to add parameters here
parameter output_data_width = 8,
// User parameters ends
... | 6.519907 |
module CPU_DeInstruction (
input [31:0] instruction,
output [ 5:0] ins
);
wire [12:0] temp_ins;
reg [ 5:0] reg_ins;
assign temp_ins = {instruction[31:26], instruction[5:0], instruction[23]};
always @(*) begin
casex (temp_ins)
//R指令
13'b000000_100000x: reg_ins <= 0; //addu
13'b00... | 8.135044 |
module CPU_Basy3 (
input clk,
input button,
input Reset,
input [2:0] sw,
output reg [6:0] seg,
output reg [3:0] AN
);
wire CLK;
reg [15:0] display;
initial begin
display = 0;
end
wire [6:0] w1;
wire [3:0] w2;
wire [2:0] w3;
wire [31:0] curPC, nextPC, ALUResult, DB, ReadData1... | 6.666274 |
module CPU_display7seg (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31... | 6.934405 |
module utilizes an integer
// datapath to execute instructions and write out to memory. The
// module outputs a 16-bit address location and 16 bits of data out,
// along with 16 bits of data input. A program counter and instruction
// register is made as well, along with a 2-to-1 mux. Lastly, a sign
// extens... | 8.503391 |
module cpu_fetch #(
parameter BOOT_ADDRESS = 32'h00001000
) ( /*AUTOARG*/
// Outputs
imem_address_o,
imem_stb_o,
imem_cyc_o,
PC_o,
opcode,
valid,
operand,
imem_sel_o,
// Inputs
rst_i,
clk_i,
imem_data_i,
imem_ack_i,
branch_flag_i,
branch_target_i,
... | 7.875562 |
module cpu_fetch_stage(
input clk,
input reset,
output [31:2] memory_interface_fetch_address,
input [31:0] memory_interface_fetch_data,
input memory_interface_fetch_valid,
input `fetch_action fetch_action,
input [31:0] target_pc,
output reg [31:0] output_pc,
output [31:0] output_inst... | 6.832017 |
module cpu_flags #(
parameter N = `N_FLAGS,
parameter N_THREADS = 16,
parameter N_THREADS_MSB = `MSB(N_THREADS - 1)
) (
input CLK,
input [N_THREADS_MSB : 0] thread_num,
input load_en,
save_en,
output reg [N-1 : 0] flags, // Flags themselves
input [`CONDITION_LEN-1 : 0] op_condition... | 6.788534 |
module CPU_FPGA (
input rst,
input clk,
output wire [6:0] cathode,
output wire [7:0] anode
);
wire [31:0] tag;
Processor CPU (
clk,
~rst,
tag
);
Seven_Seg SVG (
clk,
tag,
cathode,
anode
);
endmodule
| 7.338196 |
module cpu_gpr_tb;
/* clk & reset */
reg clk = `LOW;
reg reset = `RESET_ENABLE;
/* read port 0-1 */
reg [`REG_ADDR_BUS] rd_addr_0;
wire [`WORD_DATA_BUS] rd_data_0;
reg [`REG_ADDR_BUS] rd_addr_1;
wire [`WORD_DATA_BUS] rd_data_1;
/* write port */
reg we_n = `DISABLE_;
reg [`REG_ADDR_BUS] w... | 6.532091 |
module cpu (
PC,
INSTRUCTION,
CLK,
RESET
);
input [31:0] INSTRUCTION;
input CLK, RESET;
output reg signed [31:0] PC;
wire [31:0] nextPC, jumpPC, NEWPC;
wire [2:0] READREG1, READREG2, WRITEREG, ALUOP;
wire [7:0] IMMEDIATE, aluOut, REGOUT1, REGOUT2, REGOUT2MINUS, JUMPIMMED;
wire [7:0] OUTmux... | 7.550153 |
module
module PCupdate(PCvalue, newPC, RESET);
input signed [31:0] PCvalue;
input RESET;
output reg signed [31:0] newPC;
always@ (PCvalue) begin
#1
newPC = PCvalue + 4;
end
// Reset pc to 0 when reset is high
always@ (RESET) begin
if(RESET) begin
new... | 6.620969 |
module PCAdder (
PC,
newPC,
isJump,
isBeq,
increment
);
input signed [31:0] PC;
input signed [7:0] increment;
input [7:0] OPCODE;
input isJump, isBeq, ZERO;
output reg signed [31:0] newPC;
always @(isJump or isBeq) begin
#1
if (isJump) newPC = PC + (increment * 4);
else if (... | 7.055893 |
module decode (
INSTRUCTION,
data1,
data2,
result,
immediate,
jumpImmed,
op_code
);
input [31:0] INSTRUCTION;
output reg [2:0] data1, data2, result;
output reg [7:0] immediate, op_code;
output reg signed [7:0] jumpImmed;
always @(INSTRUCTION) begin
#1;
// Decode the instru... | 7.887076 |
module to convert second operand
module twosComplement(DATA, OUTPUT);
input [7:0] DATA;
output reg [7:0] OUTPUT;
always@ (DATA) begin
#1
OUTPUT = ~DATA;
OUTPUT = OUTPUT + 1;
end
endmodule
| 7.504718 |
module MUX2_1 (
input0,
input1,
select,
outVal
);
input [7:0] input0, input1;
input select;
output reg [7:0] outVal;
always @(input0, input1, select) begin
case (select)
0: outVal = input0;
1: outVal = input1;
endcase
end
endmodule
| 7.064965 |
module MUX3_1 (
input0,
input1,
ISJMP,
ISBEQ,
OUTVAL,
ZERO
);
input [31:0] input0, input1;
input ISJMP, ISBEQ, ZERO;
output reg [31:0] OUTVAL;
always @(input0, input1, ISJMP, ISBEQ, ZERO) begin
if (ISJMP) OUTVAL = input1;
else if (ISBEQ) OUTVAL = input1;
else OUTVAL = input0... | 6.548938 |
module alu (
DATA1,
DATA2,
RESULT,
SELECT,
ZERO
);
// Define nputs and output
input [7:0] DATA1, DATA2;
input [2:0] SELECT;
output reg [7:0] RESULT;
output reg ZERO;
wire [7:0] Rfor, Radd, Rand, Ror;
// Instentiate
forwardmodule mod0 (
DATA2,
Rfor
);
addmodule mod1 ... | 6.675659 |
module addmodule (
DATA1,
DATA2,
RESULT
);
// Define nputs and output
input [7:0] DATA1;
input [7:0] DATA2;
output reg [7:0] RESULT;
reg [7:0] D2;
always @(DATA1, DATA2) begin
#2 RESULT = DATA1 + DATA2;
end
endmodule
| 6.559767 |
module andmodule (
DATA1,
DATA2,
RESULT
);
// Define nputs and output
input [7:0] DATA1;
input [7:0] DATA2;
output reg [7:0] RESULT;
always @(DATA1 or DATA2) begin
#1 RESULT = DATA1 & DATA2;
end
endmodule
| 7.151832 |
module ormodule (
DATA1,
DATA2,
RESULT
);
// Define nputs and output
input [7:0] DATA1;
input [7:0] DATA2;
output reg [7:0] RESULT;
always @(DATA1 or DATA2) begin
#1 RESULT = DATA1 | DATA2;
end
endmodule
| 6.610778 |
module CPU_HeartRateOut (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31... | 7.184523 |
module cpu_if(
input wire clk,
input wire rdy,
input wire rst,
// From Icache
input wire hitx,
// input wire hity,
input wire `word_t instx,
// input wire `word_t insty,
// To Icache
output wire en_rx_out,
output wire `addr_t pcx_out,
output wire en_ry_out,
outp... | 6.90145 |
module data_sync_mux #(
parameter DATA_WIDTH = 1
) (
input wire clk,
input wire sel,
input wire [DATA_WIDTH-1:0] in,
output wire [DATA_WIDTH-1:0] out
);
reg [DATA_WIDTH-1:0] data = {DATA_WIDTH{1'b0}};
always @(posedge clk) begin
data <= sel ? in : data;
end
assign out = data;
endmodu... | 8.666409 |
module pulse_sync #(
parameter SYNC_STAGE = 3
) (
input wire clk,
input wire in,
output wire out
);
reg [SYNC_STAGE-1:0] data = {SYNC_STAGE{1'b0}};
always @(posedge clk) begin
data <= {data[SYNC_STAGE-2:0], in};
end
assign out = data[SYNC_STAGE-1];
endmodule
| 7.750607 |
module cpu_io (
reset,
clk,
SW0,
SW1,
SW2,
SW3,
SW4,
SW5,
SW6,
SW7,
SW8,
SW9,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input reset, clk;
input SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
... | 6.82757 |
module CPU_IO_ConfigMem (
FrameData,
FrameStrobe,
ConfigBits
);
parameter MaxFramesPerCol = 20;
parameter FrameBitsPerRow = 32;
parameter NoConfigBits = 20;
input [FrameBitsPerRow-1:0] FrameData;
input [MaxFramesPerCol-1:0] FrameStrobe;
output [NoConfigBits-1:0] ConfigBits;
wire [ 8-1:0] frame... | 7.484413 |
module CPU_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire ... | 6.929951 |
module CPU_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
inpu... | 6.929951 |
module CPU_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] by... | 6.929951 |
module CPU_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo... | 6.929951 |
module cpu (
output reg readM, // read from memory
output [`WORD_SIZE-1:0] address, // current address for data
inout [`WORD_SIZE-1:0] data, // data being input or output
input inputReady, // indicates that data is ready from the input po... | 7.14871 |
module CPU_main (
input reset,
input clk_input,
input [7:0] switch,
input [3:0] button,
input uart,
output [7:0] data_led,
output [11:0] data_seg,
output data_uart,
output [2:0] VGA_r,
output [2:0] VGA_g,
output [1:0] VGA_b,
output VGA_hs,
output VGA_vs
);
wire [31:... | 7.344022 |
module CPU_MEM(
clk, rst, state, stall,
i_id, i_id_o,
wrIs, wr, wrData,
opCode, opType,
rd0, rd1, imm,
opCode_o, opType_o,
memIs, memType,
memData_o, memAdd,
memData_i,
wrIs_o, wr_o, wrData_o,
stall_o,
cacheMiss, cacheReady,
);
input wire clk, rst, state, stall;
input wire [ 31:0] i_id;
output... | 6.600441 |
module cpu_memory #(
// Default case for error handling
parameter MEM_DEPTH = -1
) (
input clk,
// PicoRV32 memory interface
input mem_valid,
output reg mem_ready,
input [31:0] mem_addr,
input [31:0] mem_wdata,
input [3:0] mem_wstrb,
output reg [31:0] mem_rdata
);
// Do not g... | 10.170812 |
module CPU_Mem_tb #(
parameter DIGIT = 32,
ADDRWIDTH = 16,
DEBUGSIZE = 8
) ();
wire clock;
reg reset;
reg run;
wire MemWrite;
reg [DEBUGSIZE - 1 : 0] ProbeAddress;
wire [ADDRWIDTH - 1 : 0] MemAddress;
wire [ ... | 6.710459 |
module: CPU_with_Memory_Test
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CPU_MEM_Tester;
// Inputs
reg Clock;
//reg Reset;
reg GamePadData;
reg serialValid;
reg [15:0] ser... | 7.174247 |
module cpu_muxMB (
DataB,
IMM,
MB,
MBOUT
);
input [7:0] DataB;
input [7:0] IMM;
input MB;
output [7:0] MBOUT;
assign MBOUT = (MB == 1'b0) ? DataB : IMM;
endmodule
| 7.125155 |
module cpu_muxMD (
DataD,
DataRAM,
MD,
D_in
);
input [7:0] DataD;
input [7:0] DataRAM;
input MD;
output [7:0] D_in;
assign D_in = (MD == 0) ? DataD : DataRAM;
endmodule
| 8.553487 |
module cpu_muxPC (
PC,
PC2,
H,
NextPC
);
input [7:0] PC, PC2;
input H;
output [7:0] NextPC;
assign NextPC = (H == 1'b0) ? PC2 : PC;
endmodule
| 7.508122 |
module CPU_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "CPU_onchip_memory2.hex";
output [31:0] readdata;
input [9:0] address;
input [3:0] byteenable;... | 6.812535 |
module CPU_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "CPU_onchip_memory2_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byteen... | 6.812535 |
module CPU_Option (
input clk,
input if_equal,
input [31:0] ins,
output PC_CLK,
output IM_R,
output [1:0] MUX_PC,
output [1:0] MUX_Rd,
output MUX_Rdc,
output MUX_Rdc2,
output MUX_Ext5,
output MUX_A,
output [1:0] MUX_B,
output [3:0] ALU,
output RF_W,
output RF_... | 7.009352 |
module cpu_peripheral_bridge_downstream_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
wrfull
);
output [51:0] q;
output rdempty;
output wrfull;
input aclr;
input [51:0] data;
input rdclk;
input rdreq;
input wrclk;
input ... | 7.113562 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.