code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cpu_peripheral_bridge_upstream_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
wrusedw
);
output [32:0] q;
output rdempty;
output [5:0] wrusedw;
input aclr;
input [32:0] data;
input rdclk;
input rdreq;
input wrclk;
... | 7.113562 |
module cpu_peripheral_sync (
input clk_1x,
input clk_2x,
// 1x inputs
input [3:0] cpu_wstrb,
input [31:0] cpu_address,
input [31:0] cpu_write_data,
input cpu_mem_valid,
// 2x inputs
input cpu_mem_ready,
input [31:0] cpu_read_data,
output reg [3:0] cpu_wstrb_2x,
output ... | 7.113562 |
module cpu_pipelined (
input reset,
clk
);
/*
* Processor registers. Rd and Rr refer to registers from this array.
*/
reg [7:0] registers[31:0];
integer i;
always @(posedge reset) begin
for (i = 0; i < 32; i = i + 1) begin
registers[i] = i;
end
end
reg [7:0] program_coun... | 7.427154 |
module/data_memory.v"
`include "../instruction_memory_module/instruction_memory.v"
`include "cpu_pipeline.v"
module cpu_pipeline_tb;
reg RESET, CLK;
wire INST_MEM_READ, DATA_MEM_BUSYWAIT, DATA_MEM_READ, DATA_MEM_WRITE, INST_MEM_BUSYWAIT;
wire [127:0] INST_MEM_READDATA, DATA_MEM_READDATA, DATA_MEM_WRITEDATA;
wire [27:... | 7.077241 |
module cpu_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire locked // locked.export
);
cpu_pll_0002 cpu_pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.o... | 6.873809 |
module data_hazard_unit (
hazard_nop_sel,
DM_en_EX,
DM_write_EX,
DM_write_MEM,
rf_write_EX,
branch_hazard,
jump_hazard,
rd_addr_EX,
rd_addr_MEM,
rs1_addr,
rs2_addr,
p,
p1,
p2,
p3
);
output hazard_nop_sel;
input DM_en_EX;
input DM_write_EX;
input DM_wri... | 7.861513 |
module mux_2to1_5 (
out,
sel,
src0,
src1
);
output [31:0] out;
input sel;
input [31:0] src0;
input [31:0] src1;
endmodule
| 6.726392 |
module tb_m68k_ram_uart;
reg clk;
reg rst_n;
/* m68k <=> arbiter connections */
wire [31:0] ao_addr;
wire [31:0] ao_data_out;
wire [31:0] ao_data_in;
wire [ 3:0] ao_sel;
wire ao_cyc;
wire ao_stb; //chip select
wire ao_we;
wire ao_ack;
wire ao_... | 6.994716 |
module regfile (
input clk, //posedge write-active
input rst, //active-high asynchronous
input we, //high:write low:read
input [31:0] raddr1,
input [31:0] raddr2,
output [31:0] rdata1,
output [31:0] rdata2,
input [31:0] waddr,
input [31:0] wdata,
//for test_egg program out
... | 7.809308 |
module cpu_register (
clk,
eni,
enoa,
enob,
in,
outa,
outb
);
input wire clk;
input wire eni;
input wire enoa;
input wire enob;
input wire [31:0] in;
output wire [31:0] outa;
output wire [31:0] outb;
wire [31:0] SYNTHESIZED_WIRE_0;
register b2v_inst (
.en (eni... | 6.974174 |
module cpu_registerfile ( /*AUTOARG*/
// Outputs
value0_o,
value1_o,
sp_o,
fp_o,
// Inputs
rst_i,
clk_i,
write_enable0_i,
write_enable1_i,
value0_i,
value1_i,
reg_write_index0_i,
reg_write_index1_i,
reg_read_index0_i,
reg_read_index1_i
);
// --- Clock ... | 6.795092 |
module cpu_registers (
input clk,
input rst,
input [3:0] i_vx_addr, // selects register o_vx_data, where i_vx_addr points to the address
input [3:0] i_vy_addr, // selects register o_vy_data, where i_vy_addr points to the address
output [7:0] o_vx_data,
output [7:0] o_vy_data,
output [7:0... | 7.901437 |
module CPU_RISCV_tb ();
reg CLK, RST, Go;
wire [7:0] SEG, AN;
wire halt, e_signal;
wire [31:0]PC_Data,IR_Data,in_PC,LED_num,R1Data,R2Data,ALUData,rd_in,Imm_value,Imm_shift_value;
wire [4:0] R1Addr, R2Addr, RD;
initial begin
CLK = 0;
RST = 0;
Go = 0;
end
always #1 CLK = ~CLK;
CPU_RISCV CP... | 7.686268 |
module cpu_rom (
clk,
addr,
dataOut
);
//FIFO_DEPTH = ADDR_WIDTH^2
parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 8192;
parameter ADDR_WIDTH = 13;
input clk;
output [FIFO_WIDTH-1:0] dataOut;
input [ADDR_WIDTH-1:0] addr;
wire clk;
reg [FIFO_WIDTH-1:0] dataOut;
wire [ADDR_WIDTH-1:0] ad... | 8.530246 |
module bus_wr_rd_test ();
reg clk, rd, wr, ce;
reg [7:0] addr, data_wr, data_rd;
reg [7:0] read_data;
// Clock Generator
initial begin : clock_Generator
clk = 0;
forever #(`TIMESLICE) clk = !clk;
end
initial begin
read_data = 0;
rd = 0;
wr = 0;
ce = 0;
addr = 0;
data_wr = ... | 6.548601 |
module cpu #(
parameter data_width = 4,
parameter addr_width = 4,
parameter op_width = 4,
parameter op_param = 4,
parameter pc_width = 8
) (
input wire clk,
rst,
input wire [(op_width+op_param)-1:0] instruction,
output reg [ data_width-1:0] ... | 7.996222 |
module CPU_SDRAM_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [42:0] rd_data;
input clk;
input rd;
... | 6.575671 |
module cpu_sim_1 ();
reg clk = 0;
reg rst = 1;
reg [23:0] sw = 24'b0;
wire [23:0] led;
reg [4:0] bt = 5'b0;
wire [7:0] seg_out;
wire [7:0] seg_en;
Top test (
rst,
clk,
sw,
led,
bt,
seg_out,
seg_en
);
initial begin
#6000 rst = 0;
sw = 24'b0000_0000_... | 6.89302 |
module cpu_sim_2 ();
reg clk = 0;
reg rst = 1;
reg [23:0] sw = 24'b0;
wire [23:0] led;
reg [4:0] bt = 5'b0;
wire [7:0] seg_out;
wire [7:0] seg_en;
Top test (
rst,
clk,
sw,
led,
bt,
seg_out,
seg_en
);
initial begin
#6000 rst = 0;
//sw = 24'b0000_010... | 7.23451 |
modules/mux_2x1_32bit/mux_2x1_32bit.v"
`include "../other_modules/mux_4x1_32bit/mux_4x1_32bit.v"
`include "../other_modules/register_32bit/register_32bit.v"
`include "../other_modules/adder_32bit/adder_32bit.v"
`include "../instruction_cache_module/instruction_cache.v"
`include "../reg_file_module/reg_file.v"
`include ... | 7.150489 |
module cpu_spm_dpram (
/* Port A */
input wire clka,
input wire [`SPM_ADDR_BUS] addra,
input wire [`WORD_DATA_BUS] dina,
input wire wea,
output reg [`WORD_DATA_BUS] douta,
/* Port B */
input wire clkb,
input wire [`SPM_ADDR_BUS] addrb,
input wire [`WORD_DATA_BUS] dinb,
i... | 6.657281 |
module cpu_state #(
parameter N_STAGES = `N_STAGES
) (
input CLK,
input invalidate,
instr_wait,
reload,
output reg thread_almost_switched = 0,
output reg [N_STAGES-1:0] stage_allow = 0
);
reg [N_STAGES-1:0] stage_reached = 0;
genvar i;
generate
for (i = 0; i < N_STAGES; i = i +... | 6.715138 |
module cpu_statemachine (
input [2:0] cs,
input extra,
output EXEC1,
EXEC2,
FETCH,
output [2:0] NS,
input pipeline_enabled
);
assign NS[2] = 0;
assign NS[1] = (~cs[2] & ~cs[1] & cs[0] & extra);
assign NS[0] = (~cs[0]&~cs[1]&~cs[2]) | (~cs[2]&~cs[1]&cs[0]&~extra&pipeline_enabled) | (~... | 8.490438 |
module cpu_statemachine_bus_splitting_tb (
output logic active,
output logic [31:0] register_v0,
/* Avalon memory mapped bus controller (master) */
output logic [31:0] address,
output logic write,
output logic read,
input logic waitrequest,
output logic [31:0] writedata,
output log... | 8.490438 |
module cpu_status (
input clk,
input rst_n,
// from control
input cpu_start,
input quit_cmd,
// to CPU
output stall,
output stall_1shot,
output reg stall_dly,
output reg rst_pipe,
output reg rst_pipe_id,
output reg rst_pipe_ex,
output reg rst_pipe_ma,
output reg ... | 8.124561 |
module data_hazard_unit (
hazard_nop_sel,
DM_en_EX,
DM_write_EX,
DM_write_MEM,
rf_write_EX,
branch_hazard,
jump_hazard,
rd_addr_EX,
rd_addr_MEM,
rs1_addr,
rs2_addr
);
input [4:0] rd_addr_EX;
input [4:0] rd_addr_MEM;
input [4:0] rs1_addr;
input [4:0] rs2_addr;
input ... | 7.861513 |
module CPU_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1391541526 : 286331153;
endmodu... | 6.736766 |
module cpu_sys_cpu_mem (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "cpu_mem.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byteenable;
input chip... | 7.047783 |
module cpu_tb_part ();
reg reset, clock, enable, start;
reg [15:0] i_datain;
reg [15:0] d_datain;
reg [3:0] select_y;
wire [7:0] i_addr;
wire [7:0] d_addr;
wire [15:0] d_dataout;
wire [15:0] y;
wire d_we;
cpu_part test (
.reset(reset),
.clock(clock),
.enable(enable),
.start(... | 6.654517 |
module CPU_TB ();
wire [31:0] data_o; // saida da memoria
wire mem_clk;
wire [1:0] mem_size;
wire [31:0] addr, data_i;
reg reset;
CPU CPU0 (
.reset(reset)
, .data_o(data_o)
, .mem_clk(mem_clk)
, .mem_size(mem_size)
, .addr(addr)
, .data_i(data_i)
);
/* Dentro do mó... | 6.616712 |
module.
*
****************************************************************************/
module test_pic10_cpu;
///////////////////////////////////////////////////////////////
// These are the 'pic10' module inout ports.
///////////////////////////////////////////////////////////////
wire [7:0] gpio5_pin_bus; // ... | 6.632288 |
module cpu_test_data (
clk,
reset,
addr,
data,
ena
);
input clk;
input reset;
input [21:0] addr;
input ena;
output [31:0] data;
reg [31:0] data;
always @(posedge clk)
if (reset) data <= 0;
else if (ena) data <= ~addr;
endmodule
| 6.933826 |
module cpu_test_disk (
clk,
reset,
addr,
data
);
input clk;
input reset;
input [7:0] addr;
output [31:0] data;
reg [31:0] data;
always @(posedge clk)
if (reset) data <= 0;
else data <= {~addr, addr, addr, ~addr};
endmodule
| 6.618339 |
module CPU_Test_Module;
// Inputs
reg sys_clk;
reg sys_rst;
// Interconnection wires
wire [31:0] MAddr; // Memory Address from CPU
wire [31:0] idp_out; // Data output from IDP in CPU
wire [31:0] Mem_out, Mem_in; // DM and IO Memory bus
// Wires for Data Memory
wire dm_cs, dm_rd, ... | 6.565406 |
module cpu_top_control (
input clk,
input reset0,
input [2:0] mode,
input handle_clk,
output [6:0] segment,
output [3:0] select
);
wire handle_clk0, reset, clk_1khz;
wire [7:0] output1, output2;
wire [31:0] curPC, nextPC, ReadData1, ReadData2, result, DataOut;
wire [4:0] rs, rt;
wire ... | 7.643707 |
module cpu_top_tb;
reg clk;
reg rstn;
cpu_top cpu (
.clk (clk),
.rstn(rstn)
);
always #5 clk = ~clk;
initial begin
rstn = 0;
clk = 1;
#10 rstn = 1;
#500 $stop;
end
initial begin
$monitor(
$time,
": r[rdi] = %h\t r[rsp] = %h\t r[10] = %h\t ... | 6.846022 |
module CPU_toy (
start,
clk,
rst,
bus_busy,
cache_busy,
address,
data,
read_operation,
store,
start_to_cache,
input_data
);
input start, clk, rst, bus_busy, cache_busy;
input store;
input [7:0] input_data;
output reg [7:0] address, data;
output reg read_operation;
... | 7.009876 |
module cpu_to_synth_cdc #(
parameter N_VOICES = 1
) (
input cpu_clk,
input [N_VOICES-1:0][23:0] cpu_carrier_fcws,
input [23:0] cpu_mod_fcw,
input [4:0] cpu_mod_shift,
input [N_VOICES-1:0] cpu_note_en,
input [4:0] cpu_synth_shift,
input cpu_req,
output cpu_ack,
input synth_clk,
... | 6.660692 |
module CPU_IDTrans (
clk,
rst,
stall,
i_id,
opCode,
i_id_o,
opCode_o
);
input wire clk, rst;
input wire [3 : 0] stall;
input wire [31 : 0] i_id, opCode;
output reg [31 : 0] i_id_o, opCode_o;
always @(posedge clk) begin
if (rst == `True || (stall[1] != `True && stall[0] == `T... | 7.293853 |
module cpu_vga_interface #(
parameter DATA_WIDTH = 16,
parameter ADDRESS_WIDTH = 16,
parameter INFER = 0
) (
input rst,
px_rst,
input clk,
px_clk,
input [ADDRESS_WIDTH-1:0] cpu_addr,
input [DATA_WIDTH-1:0] cpu_din,
input io_wr,
input screenbegin,
input v_sync,
input ... | 7.39024 |
module CPU_with_Memory_Test (
input Clock,
// input Reset,
input GamePadData,
input SerialRxD,
output SerialTxD,
output GPulse,
output GLatch,
output R,
output G,
output B,
output hSync,
output vSync,
output [7:0] debug
// output [15:0] fetchAddress
);
wire... | 7.042055 |
module cpu_write ( /*AUTOARG*/
// Inputs
rst_i,
clk_i,
pipeline_control_bits_i,
memory_address_i,
mem_result_i,
PC_i
);
// --- Clock and Reset ------------------------------------------
input rst_i, clk_i;
input [`PCB_WIDTH-1:0] pipeline_control_bits_i;
input [31:0] memory_address... | 6.690727 |
module cpx_databuf_ca ( /*AUTOARG*/
// Outputs
sctag_cpx_data_buf_pa,
// Inputs
sctag_cpx_data_pa
);
output [144:0] sctag_cpx_data_buf_pa;
input [144:0] sctag_cpx_data_pa;
assign sctag_cpx_data_buf_pa = sctag_cpx_data_pa;
endmodule
| 6.597526 |
module cpx_databuf_ca2 ( /*AUTOARG*/
// Outputs
sctag_cpx_data_buf_pa,
// Inputs
sctag_cpx_data_pa
);
output [144:0] sctag_cpx_data_buf_pa;
input [144:0] sctag_cpx_data_pa;
assign sctag_cpx_data_buf_pa = sctag_cpx_data_pa;
endmodule
| 6.597526 |
module cpx_multiply #(
parameter xi_bits = 12,
parameter xq_bits = 12,
parameter yi_bits = 12,
parameter yq_bits = 12,
parameter i_bits = 24,
parameter q_bits = 24
) (
input clk,
input m_axis_tready,
input ... | 7.522371 |
module cpx_spc_buf ( /*AUTOARG*/
// Outputs
cpx_spc_data_cx2_buf,
cpx_spc_data_rdy_cx2_buf,
// Inputs
cpx_spc_data_cx2,
cpx_spc_data_rdy_cx2
);
input [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
input cpx_spc_data_rdy_cx2;
output [`CPX_WIDTH-1:0] cpx_spc_data_cx2_buf;
output cpx_spc_data_rdy_c... | 6.570645 |
module cp_acc (
sum,
cout,
carry,
x1,
x2,
x3,
x4,
cin
);
input x1, x2, x3, x4, cin;
output sum, cout, carry;
wire w1;
fa FA_CP_1 (
w1,
cout,
x1,
x2,
x3
);
fa FA_CP_2 (
sum,
carry,
w1,
x4,
cin
);
endmodule
| 6.951778 |
module cp_app (
sum,
cout,
carry,
x1,
x2,
x3,
x4,
cin
);
input x1, x2, x3, x4, cin;
output sum, cout, carry;
wire w1, w2, w3, w4, w5;
nor (w1, x3, x4);
nor (w2, x1, x2);
nor (cout, w1, w1);
xnor (w3, x3, x4);
xnor (w3, x1, x2);
nor (w5, w3, w4);
buf (carry, cin);
... | 6.783249 |
module cp_latch (
output q,
input set,
input clear,
input clock,
input reset_n,
input sys_clk // Generated
);
wire ipt;
wire ip;
// Output buffers
wire q_obuf;
// Output buffers
assign q = q_obuf;
// DUPLO.NET (765) - ipt : nr2
assign ipt = ~(set | q_obuf);
// DU... | 6.871558 |
module isEqual (
input wire [2:0] din_a,
din_b,
output wire o
);
wire [2:0] t;
xnor2 x[2:0] (
din_a,
din_b,
t
);
and3 an1 (
t[2],
t[1],
t[0],
o
);
endmodule
| 7.240397 |
module ThreeBitReg (
input wire clk,
reset,
load,
input wire [2:0] inp,
output wire [2:0] outp
);
dfrl dfrl_0 (
clk,
reset,
load,
inp[0],
outp[0]
);
dfrl dfrl_1 (
clk,
reset,
load,
inp[1],
outp[1]
);
dfrl dfrl_2 (
clk,
... | 7.609831 |
module cq (
input wire clk,
reset,
wr,
rd,
input wire [15:0] din,
output wire empty,
full,
output wire [15:0] dout
);
// Local variables
wire [2:0] rd_addr, wr_addr;
wire [2:0] rd_inc, wr_inc;
wire [15:0] fakeDout;
wire wr_load, rd_load;
inc i2 (
wr_addr,
wr_inc
... | 8.302708 |
module CQTVBlinkerVerilogDemo (
input clk50mhz,
input button,
output LED1,
output LED2,
output LED3
);
reg [31:0] counter_r;
reg [ 2:0] led_r;
always @(posedge clk50mhz) begin
counter_r <= counter_r + 32'd1;
case ({
button, counter_r[25:24]
})
0: led_r <= 3'b001;
... | 7.453169 |
module cq_to_rq #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface s_axis_up_rc
parameter integer TDATA_WIDTH = 128,
parameter integer TKEEP_WIDTH = 4,
parameter integer RQ_TUSER_WIDTH = 85... | 8.696941 |
module cq_viola_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
w... | 6.791564 |
module cq_viola_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
... | 6.791564 |
module cq_viola_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:... | 6.791564 |
module cq_viola_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input... | 6.791564 |
module cq_viola_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [40:0] rd_data;
input clk;
input ... | 6.787097 |
module CR2GPIOTestBitstream (
gpio_in,
gpio_out,
led_0,
led_1
);
input wire gpio_in;
output wire gpio_out;
output wire led_0;
output wire led_1;
assign gpio_out = ~gpio_in;
assign led_0 = gpio_in;
assign led_1 = ~gpio_in;
endmodule
| 7.289594 |
module cra (
in0,
in1,
s,
e,
out
);
input [4:0] in0;
input [4:0] in1;
input [1:0] s;
input [1:0] e;
output [7:0] out;
wire c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11;
wire w0, w1, w2, w3, w4, w5;
half_adder h0 (
.in0 (in0[0]),
.in1 (s[0]),
.cout(c0),
... | 6.957381 |
module show you how to infer an SRAM block
// in your circuit using the standard Verilog code.
//
module cram
#(parameter DATA_WIDTH = 16, ADDR_WIDTH = 6, RAM_SIZE = 64)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// D... | 6.896868 |
module RAM0 (
a,
d,
we,
clk,
q
);
input [11:0] d;
input [6:0] a;
input we, clk;
output [11:0] q;
reg [11:0] w;
reg [11:0] mem0[31:0];
integer i;
initial begin
for (i = 0; i < 32; i = i + 1) begin
mem0[i] = i;
end
end
always @(posedge clk) begin
if (we) mem0[... | 6.550184 |
module crc12_tb;
parameter VCD_FILE = "crc12_tb.vcd";
`define TIMEOUT 400
`include "tb_base.v"
reg [63:0] data_in = 'h0;
reg [11:0] ref_crc12 = 'h0;
wire [11:0] crc12;
reg test_en = 1'b1;
reg init = 1'b0;
jesd204_crc12 DUT (
.clk(clk),
.reset(1'b0),
.init(init),
.data_in(da... | 7.019196 |
module crc16 (
// Inputs
input [15:0] crc_in_i
, input [ 7:0] din_i
// Outputs
, output [15:0] crc_out_o
);
assign crc_out_o[15] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^
crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_i... | 7.143427 |
module for data[15:0] , crc[15:0]=1+x^2+x^15+x^16;
//-----------------------------------------------------------------------------
module crc16_16b_parallel(
input [15:0] data_in,
input crc_en,
output [15:0] crc_out,
input rst,
input clk);
reg [15:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @... | 7.665116 |
module crc16_8b (
input clk,
input rstn,
input [ 7:0] din,
input din_en,
output [15:0] crc
);
wire [15:0] crc1;
reg [15:0] next_crc1;
reg [ 7:0] crc2;
assign crc = {crc2, crc1[7:0]};
assign crc1[15] = din[3] ^ din[7] ^ next_crc1[7] ^ next_crc1[3];
assign crc1... | 7.043087 |
module for data[7:0] , crc[15:0]=1+x^2+x^15+x^16;
//-----------------------------------------------------------------------------
module crc(
input [7:0] data_in,
input crc_en,
output [15:0] crc_out,
input rst,
input clk);
reg [15:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
lfs... | 7.303673 |
module for data[7:0] , crc[15:0]=1+x^5+x^12+x^16;
//-----------------------------------------------------------------------------
`default_nettype none
module crc16_CCITT #(parameter INIT_VALUE = 16'hFFFF) (
input wire clk,
input wire reset_n,
input... | 7.303673 |
module containing a synthesizable CRC function
// * polynomial: (0 5 12 16)
// * data width: 16
//
// Info: tools@easics.be
// http://www.easics.com
//////////////////////////////////////////////////////////... | 7.897638 |
module CRC16_D32;
// polynomial: (0 2 15 16)
// data width: 32
// convention: the first serial bit is D[31]
function [15:0] nextCRC16_D32;
input [31:0] Data;
input [15:0] crc;
reg [31:0] d;
reg [15:0] c;
reg [15:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[31] ^ d[30] ^... | 8.18354 |
module crc16_dat16 (
crc_in,
dat_in,
crc_out
);
input [15:0] crc_in;
input [15:0] dat_in;
output [15:0] crc_out;
wire [15:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc16_dat16_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.580967 |
module crc16_dat24 (
crc_in,
dat_in,
crc_out
);
input [15:0] crc_in;
input [23:0] dat_in;
output [15:0] crc_out;
wire [15:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc16_dat24_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.580036 |
module crc16_dat24_flat (
crc_in,
dat_in,
crc_out
);
input [15:0] crc_in;
input [23:0] dat_in;
output [15:0] crc_out;
wire [15:0] crc_out;
wire x7, x6, x5, x4, x3, x2, x1, x0, x15, x14, x13, x12, x11, x10, x9, x8;
assign crc_out = {x15, x14, x13, x12, x11, x10, x9, x8, x7, x6, x5, x4, x3, x2,... | 6.889253 |
module crc16_dat32 (
crc_in,
dat_in,
crc_out
);
input [15:0] crc_in;
input [31:0] dat_in;
output [15:0] crc_out;
wire [15:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc16_dat32_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.527409 |
module crc16_dat32_flat (
crc_in,
dat_in,
crc_out
);
input [15:0] crc_in;
input [31:0] dat_in;
output [15:0] crc_out;
wire [15:0] crc_out;
wire x15, x14, x13, x12, x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x1, x0;
assign crc_out = {x15, x14, x13, x12, x11, x10, x9, x8, x7, x6, x5, x4, x3, x2,... | 7.235826 |
module crc16_dat8 (
crc_in,
dat_in,
crc_out
);
input [15:0] crc_in;
input [7:0] dat_in;
output [15:0] crc_out;
wire [15:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc16_dat8_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_out... | 7.576021 |
module crc16_dat8_flat (
crc_in,
dat_in,
crc_out
);
input [15:0] crc_in;
input [7:0] dat_in;
output [15:0] crc_out;
wire [15:0] crc_out;
wire x7, x6, x5, x4, x3, x2, x1, x0, x15, x14, x13, x12, x11, x10, x9, x8;
assign crc_out = {x15, x14, x13, x12, x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x... | 6.966933 |
module crc16_dat8_factor (
crc_in,
dat_in,
crc_out
);
input [15:0] crc_in;
input [7:0] dat_in;
output [15:0] crc_out;
wire [15:0] crc_out;
wire x19, x18, x17, x16, x7, x6, x5, x4, x3, x2, x1, x0, x15, x14, x13, x12, x11, x10, x9, x8;
assign crc_out = {x15, x14, x13, x12, x11, x10, x9, x8, x7,... | 6.676623 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module crc_192bits (
input [175:0] data_in,
input clk,
output reg [191:0] data_out
);
reg [191:0] input_reg;
reg [15:0] crc_reg;
integer i;
integer j = 0;
//////////////
/////////////////////////////////
always @(posedge clk) begin
if (!j) begin
input_reg = {data_in, 16'b00000000... | 6.93771 |
module crc22a (
clock,
data,
reset,
crc
);
input clock;
input [15:0] data;
input reset;
output [21:0] crc;
// Latch crc function result
reg [21:0] crc = 0;
always @(posedge clock) begin
if (reset) crc <= 0;
else crc <= nextCRC22_D16(data, crc);
end
//----------------------... | 7.506958 |
module crc24_dat64 (
input [23:0] crc_in,
input [63:0] dat_in,
output [23:0] crc_out
);
parameter METHOD = 1;
generate
if (METHOD == 0)
crc24_dat64_flat cc (
.c(crc_in),
.d(dat_in),
.crc_out(crc_out)
);
else
crc24_dat64_factor cc (
.c... | 7.743586 |
module crc24_zer64x2_flat (
c,
crc_out
);
input [23:0] c;
output [23:0] crc_out;
wire [23:0] crc_out;
assign crc_out[0] = c[0] ^ c[3] ^ c[9] ^ c[14] ^ c[15] ^ c[19] ^ c[20] ^ c[22] ^ c[23];
assign crc_out[1] = c[1] ^ c[3] ^ c[4] ^ c[9] ^ c[10] ^ c[14] ^ c[16] ^ c[19] ^ c[21] ^ c[22];
assign crc_o... | 8.334084 |
module crc24_zer64x3_flat (
c,
crc_out
);
input [23:0] c;
output [23:0] crc_out;
wire [23:0] crc_out;
assign crc_out[0] = c[7] ^ c[9] ^ c[14] ^ c[15] ^ c[17] ^ c[19] ^ c[22] ^ c[23];
assign crc_out[1] =
c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[14] ^ c[16] ^
c[17] ^ c[18] ^ c[19] ^ c[20] ^ c[22];
a... | 8.002165 |
module crc24_zer64_flat (
c,
crc_out
);
input [23:0] c;
output [23:0] crc_out;
wire [23:0] crc_out;
assign crc_out[0] =
c[1] ^ c[6] ^ c[8] ^ c[9] ^ c[12] ^ c[13] ^
c[16] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23];
assign crc_out[1] =
c[0] ^ c[1] ^ c[2] ^ c[6] ^ c[7] ^ c[8] ^
c[10] ^ c... | 7.87145 |
module crc32c_dat32 (
input [31:0] crc_in,
input [31:0] dat_in,
output [31:0] crc_out
);
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32c_dat32_flat cc (
.c(crc_in),
.d(dat_in),
.crc_out(crc_out)
);
else
crc32c_dat32_factor cc (
... | 7.653159 |
module crc32c_dat64 (
input [31:0] crc_in,
input [63:0] dat_in,
output [31:0] crc_out
);
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32c_dat64_flat cc (
.c(crc_in),
.d(dat_in),
.crc_out(crc_out)
);
else
crc32c_dat64_factor cc (
... | 7.833253 |
module crc32c_dat64_only (
d,
crc_out
);
input [63:0] d;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32c_dat64_only_flat cc (
.d(d),
.crc_out(crc_out)
);
else
crc32c_dat64_only_factor cc (
.d(d... | 8.477192 |
module crc32c_zer64 (
c,
crc_out
);
input [31:0] c;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32c_zer64_flat cc (
.c(c),
.crc_out(crc_out)
);
else
crc32c_zer64_factor cc (
.c(c),
.c... | 8.158519 |
module crc32d16N ( /*AUTOARG*/
// Outputs
crc32N,
// Inputs
clk,
resetN,
load,
d,
en
);
input clk;
input resetN;
input load; //load the seed value
input [15:0] d; //16 bit of tlp data starting with seq. num
input en; //should be high the entire packet.
output [31:0] crc3... | 6.847495 |
module crc32_128_tb ();
////////////////////////////
// 1 to 16 byte variable unit
// under test
////////////////////////////
reg [3:0] dat_size;
reg [31:0] crc_in;
wire [31:0] crc_out;
reg [127:0] dat;
reg [127:0] tmp_dat;
crc32_dat128_any_byte crc (
.dat_size(dat_size),
.crc_in(crc_in),
.crc_out(crc_out),
.dat8... | 7.60883 |
module crc32_byte_roll #(
parameter TARGET_CHIP = 2,
parameter REDUCE_LATENCY = 1'b0
) (
input clk,
input [2:0] roll_bytes,
input [31:0] pc, // previous CRC
output [31:0] c
);
reg roll1_r = 1'b0;
reg roll0_r = 1'b0;
reg roll0_rr = 1'b0;
reg roll1_rr = 1'b0;
reg roll0_rrr = 1'b0;
re... | 6.592658 |
module name conflict with 10G MAC CRC library name. Change to crc32_calculator.v
module crc32_calculator (
CLK,
RESET_N,
DATA_INPUT_ENDIAN_SEL,
CRC_OUTPUT_ENDIAN_SEL,
AVST_READY,
AVST_VALID,
AVST_SOP,
AVST_DATA,
AVST_EOP,
AVST_EMPTY,
CRC_VALID,
CRC_CHECKSUM
);
parameter DATA_WIDTH = 32; //8, 16(... | 7.56484 |
module crc32_chk (
CLK,
RESET_N,
AVST_READY,
AVST_VALID,
AVST_SOP,
AVST_DATA,
AVST_EOP,
AVST_EMPTY,
CRC_VALID,
CRC_BAD
);
parameter DATA_WIDTH = 32; //8, 16(optional), 32,64
parameter EMPTY_WIDTH = 2; //x, 1 , 2 ,3
parameter CRC_WIDTH = 32; //CRC32
parameter RE... | 7.03049 |
module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 8
//
// Info: tools@easics.be
// http://www.easics.com
///////////////////////////////... | 7.897638 |
module crc32_dat104 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [103:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat104_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(c... | 7.384639 |
module crc32_dat112 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [111:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat112_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(c... | 6.828286 |
module crc32_dat120 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [119:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat120_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(c... | 7.325483 |
module crc32_dat128 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [127:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat128_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(c... | 7.128645 |
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