code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module crc32_dat16 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [15:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat16_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.432566 |
module crc32_dat24 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [23:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat24_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.231786 |
module crc32_dat32 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [31:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat32_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.160491 |
module crc32_dat32_any_byte (
dat_size,
crc_in,
crc_out,
dat8,
dat16,
dat24,
dat32
);
input [1:0] dat_size;
input [31:0] crc_in;
output [31:0] crc_out;
wire [31:0] crc_out;
input [7:0] dat8;
input [15:0] dat16;
input [23:0] dat24;
input [31:0] dat32;
parameter METHOD = ... | 7.715703 |
module crc32_dat40 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [39:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat40_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.079922 |
module crc32_dat48 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [47:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat48_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.308537 |
module crc32_dat56 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [55:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat56_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 6.800063 |
module crc32_dat64 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [63:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat64_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.522447 |
module crc32_dat64_any_byte (
dat_size,
crc_in,
crc_out,
dat8,
dat16,
dat24,
dat32,
dat40,
dat48,
dat56,
dat64
);
input [2:0] dat_size;
input [31:0] crc_in;
output [31:0] crc_out;
wire [31:0] crc_out;
input [7:0] dat8;
input [15:0] dat16;
input [23:0] dat24;
... | 8.448938 |
module crc32_dat72 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [71:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat72_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 6.996752 |
module crc32_dat8 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [7:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat8_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_out... | 7.180227 |
module crc32_dat8_flat (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [7:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
wire x7, x6, x5, x4, x3, x2, x1,
x0, x31, x30, x29, x28, x27, x26, x25,
x24, x23, x22, x21, x20, x19, x18, x17,
x16, x15, x14, x13, x12... | 7.520663 |
module crc32_dat80 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [79:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat80_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.126138 |
module crc32_dat88 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [87:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat88_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 6.994256 |
module crc32_dat96 (
crc_in,
dat_in,
crc_out
);
input [31:0] crc_in;
input [95:0] dat_in;
output [31:0] crc_out;
wire [31:0] crc_out;
parameter METHOD = 1;
generate
if (METHOD == 0)
crc32_dat96_flat cc (
.crc_in (crc_in),
.dat_in (dat_in),
.crc_out(crc_... | 7.014313 |
module crc32_data32 (
input wire rst,
input wire clk,
input wire init_i,
input wire valid_i,
input wire [ 1:0] mod_i,
input wire [31:0] data_i,
output reg [31:0] crc_o
);
function [31:0] bit_swap;
input [31:0] data;
integer i;
begin
for (i = 0; i <= 7; i ... | 7.052235 |
module is mainly to adjust the latency to compatible with Altera CRC Compiler
module crc32_gen (
CLK,
RESET_N,
AVST_READY,
AVST_VALID,
AVST_SOP,
AVST_DATA,
AVST_EOP,
AVST_EMPTY,
CRC_VALID,
CRC_CHECKSUM
);
parameter DATA_WIDTH = 32; //8, 16(optional), 32,64
parameter EMPTY_WIDTH = 2; //x, 1 , 2 ,... | 8.207033 |
module to do that.
module crc_32_32_pipelined_1 (
use_F_for_CRC,
data_in_32,
running_crc_1,
crc_correct_2,
clk
);
parameter NUMBER_OF_BITS_APPLIED = 32; // do NOT override
input use_F_for_CRC;
input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_32;
output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] running_cr... | 8.940615 |
module can be given a starting CRC, and can incrementally calculate
// a new CRC-32 by applying 1 new data byte at a time.
module crc_32_8_incremental_pipelined_1 (
use_old_CRC,
old_crc,
use_F_for_CRC,
data_in_8,
running_crc_1,
crc_correct_2,
clk
);
parameter NUMBER_OF_BITS_APPLIED = 8; // do NOT ov... | 7.81177 |
modules which have the real formulas in them:
// Given a 32-bit CRC-32 running value, update it using 8 new bits of data.
// The way to make this fast is to find common sub-expressions.
//
// The user needs to supply external flops to make this work.
module crc_32_8_private (
use_F_for_CRC,
present_crc,
data_in... | 8.707764 |
module crc_32_64_private (
use_F_for_CRC,
present_crc,
data_in_64,
next_crc
);
parameter NUMBER_OF_BITS_APPLIED = 64;
input use_F_for_CRC;
input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc;
input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_64;
output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_c... | 9.662685 |
module crc_32_1_bit_at_a_time (
use_F_for_CRC,
present_crc,
data_in_1,
next_crc
);
input use_F_for_CRC;
input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc;
input data_in_1;
output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc;
wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] resettable_crc;
assig... | 7.238182 |
module crc32_tx (
input wire rst,
input wire clk,
input wire crc_en,
input wire [3:0] data_in,
output reg [31:0] crc_out
);
wire [ 3:0] idx;
reg [31:0] crc_table;
always @(*) begin
case (idx)
4'b0000: begin
crc_table = 32'h4DBDF21C;
end
4'b0001: begin
c... | 6.834788 |
module inputs and outputs are synchronized to, frequency > ~30 MHz */
/* serialClk(synch): serialData input is captured @ posedge of seriaClk */
/* serialData(Synch): Input data subject for CRC calculation */
/* reset(Synch): At posedge of reset the CRC calculation is resta... | 6.690571 |
module crc5 (
input [ 4:0] crc_i,
input [10:0] data_i,
output [ 4:0] crco
);
wire [4:0] crc_o;
assign crco = ~crc_o;
assign crc_o[0] = data_i[10] ^ data_i[9] ^ data_i[6] ^ data_i[5] ^ data_i[3] ^ data_i[0] ^
crc_i[0] ^ crc_i[3] ^ crc_i[4];
assign crc_o[1] = data_i[... | 7.352574 |
module crc7 #(
parameter WIDTH = 40
) (
clk,
reset,
load,
data_in,
crc_ready,
crc
);
input clk, reset, load;
input [WIDTH-1:0] data_in;
output reg crc_ready;
output [6:0] crc;
reg [WIDTH+6:0] data;
reg [6:0] index;
wire [7:0] divisor;
// generator polynomial: G(x) = x^7 + x... | 6.848693 |
module crc7_32_dec (
clk,
reset_n,
enable,
i_code,
o_data,
o_valid,
o_haserr
);
//------ INPUT PORTS -----
input clk;
input reset_n;
input enable;
input [0:38] i_code;
//------OUTPUT PORTS -----
output [0:31] o_data;
output o_valid;
output o_haserr;
//---- INTERNAL V... | 7.168619 |
module crc7_32_enc (
clk,
reset_n,
enable,
i_data,
o_code,
o_valid
);
//--- INPUT PORTS ---
input clk;
input reset_n;
input enable;
input [0:31] i_data;
//----OUTPUT PORTS----
output [0:38] o_code;
output o_valid;
//---INTERNAL SIGNALS --
reg [0:31] datareg; // OPTIONAL ... | 6.882552 |
module crc7_d1 (
input clk,
input rst,
input data,
input dvld,
output [6:0] dout
);
reg [6:0] crc;
/* TODO: this is wrong */
always @(posedge clk) begin
if (rst) begin
crc <= 0;
end else begin
if (dvld) begin
crc[0] <= data ^ crc[6];
... | 6.804477 |
module for data[7:0] , crc[7:0]=1+x^1+x^2+x^3+x^6+x^7+x^8;
// poly taken from https://users.ece.cmu.edu/~koopman/crc/index.html
// should have HD=3 (detect 2b) for packets up to 247b (incl 8 CRC bits), HD=2 (detect 1b) else
// PWI - formatting and switched rst to asynch active low
//----------------------------------... | 7.303673 |
module crc8_64_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:63] DATA_OUT;
reg [0:71] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
reg active;
//------INSTANTIATE MODULE -----
crc8_64_dec u_crc8_64_dec (
.clk(clk_drv),
.reset_n(r... | 7.502976 |
module crc8_64_enc_tb;
//------ INPUT PORTS -----
reg clk_drv;
reg rst_n;
reg [0:63] DATA_IN;
wire [0:71] CODE_OUT;
wire VALID_OUT;
reg EN;
reg active;
// ---- instantiate the UUT ----
crc8_64_enc u_crc8_64_enc (
.clk(clk_drv),
.reset_n(rst_n),
.enable(EN),
.i_data(DATA_IN... | 6.591408 |
module CRC8_D1;
// polynomial: x^8 + x^5 + x^4 + 1
// data width: 1
// convention: the first serial bit is D[0]
function [7:0] nextCRC8_D1;
input Data;
input [7:0] crc;
reg [0:0] d;
reg [7:0] c;
reg [7:0] newcrc;
begin
d[0] = Data;
c = crc;
newcrc[0] = d[0] ^ c[7];
... | 7.365451 |
module CRC8_D8;
// polynomial: x^8 + x^5 + x^4 + 1
// data width: 8
// convention: the first serial bit is D[7]
function [7:0] nextCRC8_D8;
input [7:0] Data;
input [7:0] crc;
reg [7:0] d;
reg [7:0] c;
reg [7:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[6] ^ d[4]... | 7.692804 |
module for data[7:0] , crc[7:0]=1+x^4+x^5+x^8;
//-----------------------------------------------------------------------------
module crc8_lfsr(
input [7:0] data_in,
input crc_en,
output [7:0] crc_out,
input rst,
input clk);
reg [7:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
lfs... | 7.303673 |
module for data[7:0] , crc[7:0]=1+x^4+x^5+x^8;
//-----------------------------------------------------------------------------
module crc8_lfsr(
input [7:0] data_in,
input crc_en,
output [7:0] crc_out,
output [7:0] crc_oth,
input rst,
input clk);
reg [7:0] lfsr_q,lfsr_c;
reg [7:0] lfsr_p,lfsr_t;
a... | 7.303673 |
module crc9_128_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:127] DATA_OUT;
reg [0:136] CODE_IN;
wire VALID_OUT;
reg EN;
wire HASERR;
reg active;
//------INSTANTIATE MODULE -----
crc9_128_dec u_crc9_128_dec (
.clk(clk_drv),
.reset_n(rst_n),
.enable(EN),
... | 7.220992 |
module bit_reversal
#(
parameter DATA_SIZE = 32
)
(
//OUTPUTS
output [DATA_SIZE - 1 : 0] data_out,
//INPUTS
input [DATA_SIZE - 1 : 0] data_in,
input [1 : 0] rev_type
);
//Bit reversing types
localparam NO_REVERSE = 2'b00;
localparam BYTE = 2'b01;
localparam HALF_WORD = 2'b10;
localparam WORD = 2... | 6.714069 |
module implements the combinational logic for one iteration of CRC Calculation
//If conected to shift register and after n clock cycles, this module realize CRC calculation
//for n bits of data.
//If instantiated in serial form, this module realize the parallel CRC calculation
//for n bits of data.
module crc_comb
#(
... | 7.842559 |
module crc_parallel #(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter FRAME_SIZE = 8 // Number of bits in the data block
) (
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out,
//INPUTS
input [FRAME_SIZE - 1 : 0] data_in,
input [CRC_SIZE - 1 : 0] crc_init,
input [C... | 8.891047 |
module crc_unit (
//OUTPUTS
output [31:0] crc_poly_out,
output [31:0] crc_out,
output [31:0] crc_init_out,
output [7:0] crc_idr_out,
output buffer_full,
output read_wait,
output reset_pending,
//INPUTS
input [31:0] bus_wr,
input [1:0] crc_poly_size,
input [1:0] bus_size,
... | 7.872133 |
module host_interface (
//OUTPUTS
output [31:0] HRDATA,
output HREADYOUT,
output HRESP,
output [31:0] bus_wr,
output [1:0] crc_poly_size,
output [1:0] bus_size,
output [1:0] rev_in_type,
output rev_out_type,
output crc_init_en,
output crc_idr_en,
output crc_poly_en,
o... | 7.200446 |
module crcgen (
clk,
data,
datavalid,
empty,
endofpacket,
reset_n,
startofpacket,
checksum,
crcvalid
);
input clk;
input [63:0] data;
input datavalid;
input [2:0] empty;
input endofpacket;
input reset_n;
input startofpacket;
output [31:0] checksum;
output crcvalid... | 6.740536 |
module crcGenMaster #(
parameter bitLength = 40,
parameter crcLength = 7
) (
clk, // Clock
useModule, // sync. CRC Slave will start on posedge and keeps crc until negedge
instream, // input bit stream. length defined by parameter 'bitLength'. Should not change while useModule.
generato... | 7.801749 |
module crcgen_dat32 (
clk,
data,
datavalid,
empty,
endofpacket,
reset_n,
startofpacket,
checksum,
crcvalid
);
input clk;
input [31:0] data;
input datavalid;
input [1:0] empty;
input endofpacket;
input reset_n;
input startofpacket;
output [31:0] checksum;
output cr... | 6.526293 |
module crclut #(
// IWIDTH is width of LUT input.
parameter IWIDTH = 8,
// OWIDTH is width of LUT output. This is the width of the CRC check value,
// which is one less than the order of the CRC polynomial.
parameter OWIDTH = 32,
// POLY is the CRC polynomial, excluding the msb. This should be... | 7.728653 |
module crcSMPTE (
input [17:0] crcIn,
input [ 9:0] data,
output [17:0] crcOut
);
assign crcOut[0] = crcIn[10];
assign crcOut[1] = crcIn[11];
assign crcOut[2] = crcIn[12];
assign crcOut[3] = (crcIn[0] ^ crcIn[13] ^ data[0]);
assign crcOut[4] = (crcIn[0] ^ crcIn[1] ^ crcIn[14] ^ data[0] ^ dat... | 6.792499 |
module crc_128_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:127] DATA_OUT;
reg [0:133] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
crc_128_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(... | 6.905881 |
module crc_128_enc_tb;
//------ INPUT PORTS -----
reg clk_drv;
reg rst_n;
reg [0:127] DATA_IN;
wire [0:133] CODE_OUT;
wire VALID_OUT;
reg EN;
// ---- instantiate the UUT ----
crc_128_enc UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(EN),
.i_data(DATA_IN),
.o_code(CODE_... | 6.673809 |
module crc_16(bit, enable, clk, reset, crc);
input bit;
input enable;
input clk;
input reset;
output[15:0] crc;
reg[15:0] crc;
wire inv;
assign inv = bit ^ crc[15];
always @(posedge clk or posedge reset) begin
if (reset) begin
crc = 0;
end else begin
if (enable==1) beg... | 7.268827 |
module CRC_16_CCITT_Parallel (
input i_Clk,
input i_Rst_n,
input i_Init,
input i_DV,
input [7:0] i_Data,
output [15:0] o_CRC,
output [15:0] o_CRC_Reversed,
output [15:0] o_CRC_Xor,
output [15:0] o_CRC_Reversed_Xor
);
reg [15:0] r_CRC;
// CRC Control logic
always @(posedge i_C... | 7.024076 |
module crc_16_rtu (
input clk,
input start,
input [ 7:0] byte_in,
input reset,
output reg [15:0] crc_16,
output reg busy
);
localparam [15:0] polinom = 16'hA001;
localparam [3:0] IDLE = 4'b0000;
localparam [3:0] STAGE_0 = 4'b0001;
localpa... | 8.678847 |
module crc_16_rtu_rx_32_w (
input clk,
input start,
input [ 7:0] byte_in,
input reset,
output reg [15:0] crc_16,
output reg busy
);
localparam [15:0] polinom = 16'hA001;
localparam [3:0] IDLE = 4'b0000;
localparam [3:0] STAGE_0 = 4'b0001;
... | 8.550892 |
module crc_16_rtu_tx_32_w (
input clk,
input start,
input [ 7:0] byte_in,
input reset,
output reg [15:0] crc_16,
output reg busy
);
localparam [15:0] polinom = 16'hA001;
localparam [3:0] IDLE = 4'b0000;
localparam [3:0] STAGE_0 = 4'b0001;
... | 8.413354 |
module CRC_16_serial (
clk,
rst,
load,
d_finish,
crc_in,
crc_out
);
input clk; //輸入信號
input rst; //重設信號
input load; //開始編碼信號
input d_finish; //編碼結束信號
input crc_in; //待編碼字輸入
output crc_out; //編碼後碼字輸出
reg crc_out; //碼字輸出暫存器,1bit
reg [15:0] crc_reg; //線性移位暫存器,16bit
reg [... | 6.589863 |
module CRC_16_serial_test;
reg clk;
reg rst;
reg load;
reg d_finish;
reg crc_in;
wire crc_out; //線網型資料,1bit
parameter clk_period = 40; //clk 週期為 40ns
initial //初始化相關阜值
begin
#clk_period clk = 1;
#clk_period rst = 1;
#clk_period rst = 0;
#clk_period crc_in = 1; //輸入... | 6.589863 |
module crc_16_tb ();
//激励信号定义
reg tb_clk ;
reg tb_rst_n ;
reg crc_en ;
reg clear ;
reg [7:0] data_in ;
reg [3:0] byte_cnt;
//输出信号定义
wire [15:0] crc_out ;
//时钟周期参数定义
parameter CLOCK_CYCLE = 20;
parameter CHECK_BYTES = 48'hf00300010001;
crc_16 u_crc_16 (
... | 7.717858 |
module crc_2_level_pipeline (
clk,
reset,
data_in,
data_out
);
input clk, reset;
input [9:0] data_in;
output reg [8:0] data_out;
reg [9:0] data_reg;
reg d1, d2;
always @(posedge clk or posedge reset) begin
if (reset) begin
data_out <= 0;
$display("1 data_out = %b ", data_o... | 6.870721 |
module: crc_2_level
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//Verilog test bench code for generator polynomial 1+y+y8+y9 with 2 level pipelining
//Serial CRC circuit with 2 level pi... | 8.160055 |
module CRC_32 (
input clk,
input reset,
input enable,
input tx,
input [15:0] data,
output [15:0] crc
);
reg [15:0] data_r1;
reg [15:0] data_r2;
reg [15:0] data_r3;
reg odd;
wire [15:0] current_data;
reg [31:0] current_c... | 7.497111 |
module crc_32b (
input clk_usr,
input rst,
input [31:0] usr_rx,
input usr_rx_valid,
output reg err,
output reg [31:0] check
);
always @(posedge clk_usr or posedge rst) begin
if (rst) begin
err <= 1'b0;
check <= 32'h0000_0001;
end else begin
if (... | 6.501504 |
module CRC_4_level_pipeline (
clk,
reset,
data_in,
data_out
);
input clk, reset;
input [9:0] data_in;
output reg [8:0] data_out;
reg [9:0] data_reg;
reg d1, d21, d22, d31, d32, d33, d41, d42, d5;
always @(posedge clk or posedge reset) begin
if (reset) begin
data_out <= 0;
$... | 6.740023 |
module: CRC_4_level
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//Verilog testbench code for generator polynomial 1+y+y8+y9 with 4 level pipeline
//Serial CRC circuit
module CRC_test;... | 7.440262 |
module crc_64bit (
input t_clk,
input rst,
input check_start,
input check_en,
input [63:0] data,
output reg erro,
output reg [31:0] err_cnt,
output reg [63:0] regc
);
always @(posedge t_clk) begin
if (rst) regc <= 64'h... | 7.576187 |
module crc_64_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:63] DATA_OUT;
reg [0:69] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
crc_64_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(EN),... | 7.075033 |
module crc_64_enc (
clk,
reset_n,
enable,
i_data,
o_code,
o_valid
);
//--- INPUT PORTS ---
input clk;
input reset_n;
input enable;
input [0:63] i_data;
//----OUTPUT PORTS----
output [0:69] o_code;
output o_valid;
//---INTERNAL SIGNALS --
reg [0:63] datareg; // OPTIONAL i... | 6.750364 |
module CRC7_32BIT;
// polynomial: (0 3 7)
// data width: 32
// convention: the first serial bit is D[31]
function [6:0] nextCRC7_D32;
input [31:0] Data;
input [6:0] crc;
reg [31:0] d;
reg [ 6:0] c;
reg [ 6:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[31] ^ d[30]... | 7.727092 |
module CRC_CAL (
CLK4,
D,
CRC_ARM,
CRC_ENB,
CRC_Q
);
input CLK4;
input [15:0] D;
input CRC_ARM;
input CRC_ENB;
output [15:0] CRC_Q;
wire [15:0] R_D;
reg [15:0] R_Q;
// CRC combination logic block
CRC_CL CF (
.D(D), // one input is the data block
.C(R_Q), // othe... | 7.223731 |
module crc_ccitt16_test;
//`define inccrc 1
`ifdef inccrc
`define test_size 48
`else
`define test_size 32
`endif
reg clrcrc;
reg clk;
//reg txdin;
reg wb_rst_i;
reg crcndata;
reg bdcrc;
reg ser_i;
reg [`test_size-1:0] par_i;
reg shr_i;
reg load_i;
wire [`test_size-1:0] par_o;
crc_cci... | 6.831616 |
module crc_checksum_aligner (
CLK,
RESET_N,
CRC_CHECKSUM_LATCH_IN,
CRC_CHECKSUM_IN,
CRC_VALID_OUT,
CRC_CHECKSUM_OUT
);
parameter CRC_WIDTH = 32;
parameter LATENCY = 0;
input CLK;
input RESET_N;
input CRC_CHECKSUM_LATCH_IN;
input [CRC_WIDTH-1:0] CRC_CHECKSUM_IN;
output CRC_VAL... | 6.595426 |
module CRC_chk (
Reset,
Clk,
CRC_data,
CRC_init,
CRC_en,
//From CPU
CRC_chk_en,
CRC_err
);
input Reset;
input Clk;
input [7:0] CRC_data;
input CRC_init;
input CRC_en;
//From CPU
input CRC_chk_en;
output CRC_err;
//******************************************************... | 7.446468 |
module crc_cmp_tb ();
parameter datw = 8;
reg clk, rst, rst_syn;
reg crc_en;
reg [15:0] random_dat;
wire dat_i = random_dat[15];
wire [datw - 2:0] dat_o, dat_o_2;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst_syn = 0;
crc_en = 0;
end
initial begin
rst... | 7.630473 |
module crc_comb #(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter MASK = 8'hff // This mask define the level of configurability of the module
) (
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out, // CRC code after one round of calculation
//INPUTS
input data_in, // One bi... | 8.235015 |
module XOR_Shift_Block (
block_input,
poly,
data_input,
block_output
);
parameter crc_width = 32;
input [(crc_width-1):0] block_input;
input [(crc_width-1):0] poly;
input [7:0] data_input;
output [(crc_width-1):0] block_output;
wire [(crc_width-1):0] cascade[7:0];
XOR_Shift bit_0 (
... | 7.900138 |
module XOR_Shift (
stage_input,
poly,
new_bit,
stage_output
);
parameter crc_width = 32;
input [crc_width-1:0] stage_input;
input [crc_width-1:0] poly;
input new_bit;
output [crc_width-1:0] stage_output;
assign stage_output[0] = new_bit ^ stage_input[crc_width-1];
assign stage_output[cr... | 8.020923 |
module CRC_Custom_Instruction (
clk,
reset,
dataa,
n,
clk_en,
start,
done,
result
);
/*
See the Avalon CRC component for details on the meaning of each
parameter listed below.
*/
parameter crc_width = 32;
parameter polynomial_inital = 32'hFFFFFFFF;
parameter polynomial ... | 8.215224 |
module crc_parallel #(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter FRAME_SIZE = 8 // Number of bits in the data block
) (
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out,
//INPUTS
input [FRAME_SIZE - 1 : 0] data_in,
input [CRC_SIZE - 1 : 0] crc_init,
input [C... | 8.891047 |
module crc_comb #(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter MASK = 8'hff // This mask define the level of configurability of the module
) (
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out, // CRC code after one round of calculation
//INPUTS
input data_in, // One bi... | 8.235015 |
module bit_reversal
#(
parameter DATA_SIZE = 32
)
(
//OUTPUTS
output [DATA_SIZE - 1 : 0] data_out,
//INPUTS
input [DATA_SIZE - 1 : 0] data_in,
input [1 : 0] rev_type
);
//Bit reversing types
localparam NO_REVERSE = 2'b00;
localparam BYTE = 2'b01;
localparam HALF_WORD = 2'b10;
localparam WORD = 2... | 6.714069 |
module crc_ethernet (
aclr,
clk,
ena,
init,
dat_size,
crc_out,
dat
);
input [1:0] dat_size; // 0=1 byte .. 3=4 bytes.
input [31:0] dat;
input clk;
input ena; // deactivate me for power savings
input aclr; // async rst to 0
input init; // sync load 111...
output [31:0] crc_... | 6.640616 |
module crc_flat (
input [57:0] c,
input [ 0:0] d,
output [57:0] crc_out
);
assign crc_out[0] = c[57] ^ d[0];
assign crc_out[1] = c[0];
assign crc_out[2] = c[1];
assign crc_out[3] = c[2];
assign crc_out[4] = c[3];
assign crc_out[5] = c[4];
assign crc_out[6] = c[5];
assign crc... | 6.932487 |
module crc_guts (
input clk,
input gate,
input clear,
input b_in,
output b_out,
output zero
);
// default is CRC-16-CCITT
// poly high order bit implicitly one
// http://en.wikipedia.org/wiki/Cyclic_redundancy_check
parameter wid = 16;
parameter poly = 16'h1021;
parameter init = ... | 6.893438 |
module CRC_Module (
Clk,
Reset,
Data,
Enable,
Initialize,
Crc,
CrcError
);
input Clk;
input Reset;
input [3:0] Data;
input Enable; //should be valid from the destination address until the data before the CRC checksum
input Initialize; //need to initialize before data in
outp... | 6.677614 |
module crc_parallel #(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter FRAME_SIZE = 8 // Number of bits in the data block
) (
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out,
//INPUTS
input [FRAME_SIZE - 1 : 0] data_in,
input [CRC_SIZE - 1 : 0] crc_init,
input [C... | 8.891047 |
module crc_comb #(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter MASK = 8'hff // This mask define the level of configurability of the module
) (
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out, // CRC code after one round of calculation
//INPUTS
input data_in, // One bi... | 8.235015 |
module crc_parallel #(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter FRAME_SIZE = 8 // Number of bits in the data block
) (
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out,
//INPUTS
input [FRAME_SIZE - 1 : 0] data_in,
input [CRC_SIZE - 1 : 0] crc_init,
input [C... | 8.891047 |
module crc_register (
d,
q,
clk,
init,
sclr,
ena,
aclr
);
parameter WIDTH = 32;
parameter METHOD = 1;
parameter INIT_CONST = 32'hffffffff;
input [WIDTH-1:0] d;
input clk, init, sclr, ena, aclr;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
genvar i;
generate
if (METHOD ==... | 8.106027 |
module crc_rom (
input clk,
input [4:0] address,
input oe,
output reg valid,
output reg [7:0] q_a
);
/*****************************************************************************
Here is the CRC code used by Project 64 where we are going to use
the 6502 to process... | 7.53412 |
module for data[7:0] , crc[4:0]=1+x^2+x^5;
//------------------------------------------------------------------
module crc(
input [7:0] data_in,
input crc_en,
output [4:0] crc_out,
input rst,
input clk);
reg [4:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
lfsr_c[0] = lfsr_q[0]^l... | 7.303673 |
module CRC16_D8;
23 // polynomial: (0 2 15 16)
24 // data width: 8
25 // convention: the first serial bit is D[7]
26 function [15:0] nextCRC16_D8;
28 input [7:0] Data;
29 input [15:0] crc;
30 reg [7:0] d;
31 reg [15:0] c;
32 reg [15:0] newcrc;
33 begin
34 d = Data;
35 c = crc;
37 ... | 6.936285 |
module for data[7:0] , crc[4:0]=1+x^2+x^5;
4 module crc(
5 input [7:0] data_in,
6 input crc_en,
7 output [4:0] crc_out,
8 input rst,
9 input clk);
11 reg [4:0] lfsr_q,lfsr_c;
13 assign crc_out = lfsr_q;
15 always @(*) begin
16 lfsr_c[0] = lfsr_q[0]^lfsr_q[2]^lfsr_q[3]^data_in[0]^data_in[3]^d... | 7.303673 |
module crc_test_tb ();
reg clk, reset;
reg [7:0] d;
reg load_init;
reg calc;
reg data_valid;
wire [31:0] crc_reg;
wire [7:0] crc;
initial begin
clk = 0;
reset = 0;
load_init = 0;
calc = 0;
data_valid = 0;
d = 0;
end
always begin
#10 clk = 1;
#10 clk = 0;
end
alway... | 6.600549 |
module: CRC_unfold3_eq2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CRC_unfold3_eq2_test;
// Inputs
reg clk;
reg reset;
reg [5:0] data_in;
// Outputs
wire [4:0] data_out;... | 6.883113 |
module crc_unit (
//OUTPUTS
output [31:0] crc_poly_out,
output [31:0] crc_out,
output [31:0] crc_init_out,
output [7:0] crc_idr_out,
output buffer_full,
output read_wait,
output reset_pending,
//INPUTS
input [31:0] bus_wr,
input [1:0] crc_poly_size,
input [1:0] bus_size,
... | 7.872133 |
module crc_parallel #(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter FRAME_SIZE = 8 // Number of bits in the data block
) (
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out,
//INPUTS
input [FRAME_SIZE - 1 : 0] data_in,
input [CRC_SIZE - 1 : 0] crc_init,
input [C... | 8.891047 |
module crc_comb #(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter MASK = 8'hff // This mask define the level of configurability of the module
) (
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out, // CRC code after one round of calculation
//INPUTS
input data_in, // One bi... | 8.235015 |
module bit_reversal
#(
parameter DATA_SIZE = 32
)
(
//OUTPUTS
output [DATA_SIZE - 1 : 0] data_out,
//INPUTS
input [DATA_SIZE - 1 : 0] data_in,
input [1 : 0] rev_type
);
//Bit reversing types
localparam NO_REVERSE = 2'b00;
localparam BYTE = 2'b01;
localparam HALF_WORD = 2'b10;
localparam WORD = 2... | 6.714069 |
module crc_xnor #(
parameter INPUT_WIDTH = 64,
parameter OUTPUT_WIDTH = 8
) (
input clk,
input [INPUT_WIDTH:1] input_data,
input rst,
input hold,
output [OUTPUT_WIDTH:1] crc_out
);
wire [INPUT_WIDTH:1] current_lfsr;
reg [INPUT_WIDTH:1] current_lfsr_r;
// LFSR based on table given b... | 7.747031 |
module top_module (
input clk,
input j,
input k,
output Q
);
always @(posedge clk) Q <= (~j & ~k & Q) | (j & ~k) | (j & k & ~Q);
endmodule
| 7.203305 |
module PAGE6 ();
//: interface /sz:(40, 40) /bd:[ ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
reg w6; //: /sn:0 {0}(154,237)(309,237){1}
reg w2; //: /sn:0 {0}(219,137)(186,137)(186,137)(154,137){1}
wire w7; //: /sn:0 {0}(330,235)(340,235){1}
wire w0; //: /sn:0 {0}(204,142)(219,142){1}
wire w5; //: /sn:0 {0}(309,2... | 6.504761 |
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