code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module PAGE3 ();
//: interface /sz:(40, 40) /bd:[ ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
wire w0; //: /sn:0 {0}(204,137)(219,137){1}
wire w1; //: /sn:0 {0}(204,142)(219,142){1}
wire w2; //: /sn:0 {0}(240,140)(255,140){1}
//: enddecls
_GGAND2 #(6) g2 (
.I0(w0),
.I1(w1),
.Z (w2)
); //: @(230,... | 6.512788 |
module CreateHeader;
/*********** Variables ************/
integer conn_entries, num_credit_delay, num_of_vcs, max_cycles, num_of_routers, vcs_size;
integer fd, fh;
integer temp_res_0, temp_res_1, temp_res_2, temp_res_3;
/*********** Code ************/
initial begin
conn_entries = 0;
num_credi... | 6.72341 |
module CreateLargePulse #(
// means the pulse has to be solwed down
// to the frequency of clk/(2^16)
parameter PULSE_SIZE = 16
) (
output wire large_pulse,
input wire small_pulse,
input wire rst,
input wire clk
);
parameter WAITING = 1'b0;
parameter COUNTING = 1'b1;
reg state;
r... | 7.624281 |
module can handle i-1 when signal sw is 1
*/
module CreateNumber#(
parameter INIT_HEXES = 16'b1010_1011_1100_1101 // Init with "AbCd"
) (
input[3:0] btn,
input[3:0] sw,
output reg[15:0] num
);
wire[3:0] A, B, C, D;
initial num <= INIT_HEXES;
// A(the next num[3:0]) is always greater than current num[3:... | 6.522648 |
module CreateNumber_tb ();
reg [ 3:0] btn;
wire [15:0] num;
CreateNumber m0 (
.btn(btn),
.num(num)
);
initial begin
$dumpfile("CreateNumber.vcd");
$dumpvars(1, CreateNumber_tb);
#50;
// Simulate pressing one btn
#5 btn = 4'b1000;
#5 btn = 4'b0100;
#5 btn = 4'b0010;... | 7.198686 |
module CreateRandPosition (
clk,
randx,
randy
);
parameter LEFTLIMIT = 0;
parameter RIGHTLIMIT = 640;
parameter DOWNLIMIT = 0;
parameter UPLIMIT = 480; //˶߽
parameter A = 20; //
parameter B = 10; //
input wire clk;
output reg [9:0] randx; //ɵĺֵǾԶһλ
output reg [8:0] randy; //ɵֵ
reg ... | 7.300961 |
module createRoundKey (
input [127:0] RK,
input [ 3:0] r_c,
output [127:0] NextRK
);
wire [31:0] k1, k2, k3, k4, temp;
assign k1 = RK[127:96];
assign k2 = RK[95:64];
assign k3 = RK[63:32];
assign k4 = RK[31:0];
assign NextRK[127:96] = k1 ^ temp ^ r_const(r_c);
assign NextRK[95:64] = k1 ^... | 6.925724 |
module top (
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int... | 7.233807 |
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
| 6.553865 |
module: create_node_code
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module create_node_code_test;
// Inputs
reg CLK;
reg nRST;
reg [1:0] state;
reg [12:0] info_node_1;
reg [12:0... | 7.305397 |
module: create_node_code
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module create_node_test;
// Inputs
reg CLK;
reg nRST;
reg [1:0] state;
reg [12:0] leaf_A;
reg [12:0] leaf_B;
... | 7.305397 |
module create_paddle (
input [7:0] i_keycode,
input i_v_sync,
input i_clock_100MHz,
input [9:0] i_h_count,
input [9:0] i_v_count,
output reg o_draw_paddle
);
reg [9:0] next_y;
reg y_move_down = 1;
reg [9:0] paddle_right, paddle_left, paddle_top, paddle_bottom;
reg position_defined = ... | 8.738233 |
module creative (
// Inputs
RXD,
osc_in,
// Outputs
LED_GREEN,
LED_RED,
TXD
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input RXD;
input osc_in;
//----------------------... | 6.924955 |
module creator_dcm #(
parameter CLKFX_DIVIDE = 1,
parameter CLKFX_MULTIPLY = 4
) (
// Clock in ports
input clkin,
// Clock out ports
output clk_out_200,
output nclk_out_200,
output clk_out_25
);
IBUFG clkin_buf (
.O(b_clkin),
.I(clkin)
);
wire locked_int;
w... | 6.995463 |
module TopLevel_CREATORTESTNAME #(
parameter DATA_WIDTH = 65,
parameter FIFO_DEPTH = 6,
parameter N_OUTPUTS = CREATORNOUTPUTS,
parameter N_INPUTS = CREATORNINPUTS
) (
input wire clock,
input wire reset_n,
input wire [DATA_WIDTH-1:0] input_data[CREATORNINPUTS],
output wire [DATA_WIDTH... | 7.898657 |
module sw_mask_gen #(
parameter V = 4, // vc_num_per_port
parameter P = 5 // router port num
) (
assigned_ovc_num,
dest_port,
full,
credit_increased,
nearly_full,
ivc_getting_sw_grant,
assigned_ovc_is_full,
clk,
reset
);
localparam P_1 = P - 1, VP_1 = V * P_1;
input ... | 6.50492 |
module is a simple counter for credits
// It does not prevent over/underflow, instead it relies on the upstream environment
// to behave appropriately
module credit_counter(clk, rst, inc, dec, has_credits);
parameter CREDITS_MAX=8,
CNT_WIDTH=$clog2(CREDITS_MAX+1);
input clk, rst, inc, dec;
output... | 7.514223 |
module: create_node_code
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module create_node_code_test;
// Inputs
reg CLK;
reg nRST;
reg [1:0] state;
reg [12:0] info_node_1;
reg [12:0... | 7.305397 |
module criuspwmin (
clk,
pwmsignal,
ratio
);
input clk;
input pwmsignal;
output [10:0] ratio;
reg [31:0] counter;
reg [18:0] signalon; //# of times a sec pwm signal is at 1
reg [12:0] ratio;
reg [31:0] tempcounter;
reg [31:0] tempratio;
reg [10:0] preratio;
always @(posedge clk) begi... | 7.253756 |
module crngt_to_trng (
rst_n,
rng_clk,
rnd_src_en,
collector_crngt_data,
collector_valid,
trng_valid,
trng_crngt_bypass,
rst_trng_logic,
crngt_collector_rd,
crngt_dout,
crngt_valid,
crngt_err
);
`include "cc_params.inc"
input rst_n;
input rng_clk;
input rnd_src_en... | 7.948768 |
module CRN_COMMON (
REFCLK_SYNC_EN,
CFM_CLKOUT,
PLL0_REFCLK_SYNC_EN,
PLL1_REFCLK_SYNC_EN
)
/* synthesis black_box
*/
/* synthesis black_box black_box_pad ="" */
;
input REFCLK_SYNC_EN;
output CFM_CLKOUT;
output PLL0_REFCLK_SYNC_EN;
output PLL1_REFCLK_SYNC_EN;
parameter PC_CIMUX_GEN0_SEL = 'h0... | 6.768387 |
module CRN_COMMON (
REFCLK_SYNC_EN,
CFM_CLKOUT,
PLL0_REFCLK_SYNC_EN,
PLL1_REFCLK_SYNC_EN
);
/* synthesis syn_black_box
*/
/* synthesis black_box_pad_pin ="" */
input REFCLK_SYNC_EN;
output CFM_CLKOUT;
output PLL0_REFCLK_SYNC_EN;
output PLL1_REFCLK_SYNC_EN;
parameter PC_CIMUX_GEN0_SEL = 'h... | 6.768387 |
module for HPSDR MERCURY/QS1R Project
Copyright (C) 2007 Philip A. Covington, N8VB
The author can be reached at:
p.covington@gmail.com
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either... | 7.028669 |
module cronometro (
clk,
dis0,
dis1
);
input clk;
output [0:6] dis0, dis1;
reg segundos = 0;
reg [0:30] i = 0;
reg [3:0] number, num0, num1;
parameter segundo = 50000000;
always @(posedge clk) begin
if (i == segundo) begin
i <= 0;
segundos <= segundos + 1;
end else i <= i +... | 6.570769 |
module CrossDomainBuffer (
input wire clk,
input wire [31:0] in,
input wire save,
output reg [31:0] out = 0,
output wire saved
);
always @(posedge save) begin
out <= in;
end
reg [1:0] syncSaved;
always @(posedge clk) begin
syncSaved[0] <= save;
syncSaved[1] <= syncSaved[0];
... | 7.500806 |
module crossbar36
(input clk, input reset, input clear,
input cross,
input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i,
output [35:0] data1_o, output src1_rdy_o, input dst1_rdy... | 6.639052 |
module Axi4WriteOnlyErrorSlave (
input io_axi_aw_valid,
output io_axi_aw_ready,
input [ 63:0] io_axi_aw_payload_addr,
input [ 3:0] io_axi_aw_payload_id,
input [ 3:0] io_axi_aw_payload_region,
input [ 7:0] io_axi_aw_payload_len,
input [ 2:0] io_axi_aw_payload_size,
... | 7.745535 |
module Axi4ReadOnlyErrorSlave (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [ 63:0] io_axi_ar_payload_addr,
input [ 3:0] io_axi_ar_payload_id,
input [ 3:0] io_axi_ar_payload_region,
input [ 7:0] io_axi_ar_payload_len,
input [ 2:0] io_axi_ar_payload_size,
... | 7.858199 |
module vc_Crossbar2 #(
parameter p_nbits = 32
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
input logic sel0,
input logic sel1,
output logic [p_nbits-1:0] out0,
output logic [p_nbits-1:0] out1
);
vc_Mux2 #(p_nbits) out0_mux (
.in0(in0),
.in1(in1),
.... | 8.449409 |
module vc_Crossbar3 #(
parameter p_nbits = 32
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
input logic [p_nbits-1:0] in2,
input logic [1:0] sel0,
input logic [1:0] sel1,
input logic [1:0] sel2,
output logic [p_nbits-1:0] out0,
output logic [p_nbits-1:0] out1,
... | 8.520218 |
module vc_Crossbar4 #(
parameter p_nbits = 32
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
input logic [p_nbits-1:0] in2,
input logic [p_nbits-1:0] in3,
input logic [1:0] sel0,
input logic [1:0] sel1,
input logic [1:0] sel2,
input logic [1:0] sel3,
output l... | 8.172106 |
module crossbarShiftDown #(
parameter DATA_WIDTH = 32
) (
input [1-1:0] clk,
input [1-1:0] clk_en,
input [1-1:0] start,
input [1-1:0] reset,
input [DATA_WIDTH-1:0] in0,
input [DATA_WIDTH-1:0] in1,
input [DATA_WIDTH-1:0] in2,
input [DATA_WIDTH-1:0] in3,
input [DATA_WIDTH-1:0] in4,... | 7.312216 |
module crossbarShiftUp #(
parameter DATA_WIDTH = 32
) (
input [1-1:0] clk,
input [1-1:0] clk_en,
input [1-1:0] start,
input [1-1:0] reset,
input [DATA_WIDTH-1:0] in0,
input [DATA_WIDTH-1:0] in1,
input [DATA_WIDTH-1:0] in2,
input [DATA_WIDTH-1:0] in3,
input [DATA_WIDTH-1:0] in4,
... | 7.312216 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
as... | 7.603405 |
module CrossbarSwitchInCtl #(
parameter IO_WIDTH = 1
) (
clk_in,
xbar_selectors_a,
xbar_selectors_b,
xbar_selectors_c,
xbar_selectors_d,
outputs_a,
outputs_b,
outputs_c,
outputs_d,
inputs_a,
inputs_b,
inputs_c,
inputs_d
);
input clk_in;
input [1:0] xbar_selec... | 9.397522 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitchNew.scala 15:17 CrossBarSwitchNew.scala 16:18 CrossBarSwitchNew.scala 18... | 7.603405 |
module CrossbarSwitchOutCtl #(
parameter IO_WIDTH = 1
) (
clk_in,
xbar_selectors_a,
xbar_selectors_b,
xbar_selectors_c,
xbar_selectors_d,
inputs_a,
inputs_b,
inputs_c,
inputs_d,
outputs_a,
outputs_b,
outputs_c,
outputs_d
);
input clk_in;
input [1:0] xbar_sele... | 9.397522 |
module crossbar_4x4_addr (
input [`A_bus -1:0] LSU_addr_bus_3,
input [`A_bus -1:0] LSU_addr_bus_2,
input [`A_bus -1:0] LSU_addr_bus_1,
input [`A_bus -1:0] LSU_addr_bus_0,
output [`A_W -1:0] BG_addr_in_3,
output [`A_W -1:0] BG_addr_in_2,
output [`A_W -1:0] BG_addr_... | 6.967407 |
module crossbar_4x4_all (
input [`R_Q -1:0] LSU_R_req_3,
input [`R_Q -1:0] LSU_R_req_2,
input [`R_Q -1:0] LSU_R_req_1,
input [`R_Q -1:0] LSU_R_req_0,
input [`A_bus -1:0] LSU_addr_bus_3,
input [`A_bus -1:0] LSU_addr_bus_2,
input [`A_bus -1:0] LSU_addr_bus_1,
input [`... | 6.967407 |
module crossbar_4x4_read_data (
input [`R_Q -1:0] LSU_R_req_3,
input [`R_Q -1:0] LSU_R_req_2,
input [`R_Q -1:0] LSU_R_req_1,
input [`R_Q -1:0] LSU_R_req_0,
output to_CBG_3,
output to_CBG_2,
output to_CBG_1,
output to_CBG_0,
input [`C_L_bus-1:0] R_response_3,
input [... | 6.967407 |
module crossbar_4x4_write_data (
input [`W_Q -1:0] LSU_W_req_3,
input [`W_Q -1:0] LSU_W_req_2,
input [`W_Q -1:0] LSU_W_req_1,
input [`W_Q -1:0] LSU_W_req_0,
output [`W_d-1:0] W_BG_3,
output [`W_d-1:0] W_BG_2,
output [`W_d-1:0] W_BG_1,
output [`W_d-1:0] W_BG_0
);
wire [1:0... | 6.967407 |
module crossbar_mux (
onehot,
datain,
dataout
);
parameter ENDPOINTS = 2;
parameter SIZE = 1;
input [ENDPOINTS-1:0] onehot;
input [(SIZE*ENDPOINTS)-1:0] datain;
output reg [SIZE-1:0] dataout;
integer i;
always @(*) begin
dataout = (onehot >> 1) ? 0 : datain[0+:SIZE];
for (i = 1; i ... | 7.097822 |
module crossbar_comb #(
// The data width of input data
parameter data_width = 16,
// The data width utilized for accumulated results
parameter num_input = 8,
parameter num_output = 8,
// The latency of adder
parameter sel_width = $clog2(num_input)
) (
input wire [ num_input * data_wi... | 8.415968 |
module crossbar_top_tb ();
reg clk;
reg reset;
reg req0;
reg req1;
reg cmd0;
reg cmd1;
wire [31:0] addr0;
wire [31:0] addr1; // use the same address and wdata
wire [31:0] wdata0;
wire [31:0] wdata1;
wire [31:0] rdata_m0;
wire [31:0] rdata_m1;
wire ack_m0;
wire ack_m1;
reg sfor0;
reg ... | 6.632942 |
module crossclkparam (
i_a_clk,
i_b_clk,
i_params,
o_params
);
parameter PW = 32;
input wire i_a_clk, i_b_clk;
input wire [(PW-1):0] i_params;
output reg [(PW-1):0] o_params;
reg [1:0] a_send, b_send, a_ack;
reg [(PW-1):0] r_params;
reg b_ack;
initial a_send = 2'b00;
initial r_params... | 6.959541 |
module CrossClockDomain (
input clkA, // we actually don't need clkA in that example, but it is here for completeness as we'll need it in further examples
input SignalIn_clkA,
input clkB,
output SignalOut_clkB
);
// We use a two-stages shift-register to synchronize SignalIn_clkA to the clkB clock d... | 7.02199 |
module for a two-step cross-clock-domain synchronizer.
// It uses one intermediate register and one output register to bring
// values into the domain of the clock given as clk.
//
// This module supports values of arbitrary sizes but when using multi-bit
// values it's important to use a grey code, or equivalent, to a... | 6.822349 |
module CrossDomainBuffer (
input wire clk,
input wire [31:0] in,
input wire save,
output reg [31:0] out = 0,
output wire saved
);
always @(posedge save) begin
out <= in;
end
reg [1:0] syncSaved;
always @(posedge clk) begin
syncSaved[0] <= save;
syncSaved[1] <= syncSaved[0];
... | 7.500806 |
module crossdomain_signal (
input reset,
input clk_b,
input sig_domain_a,
output sig_domain_b
);
reg [1:0] sig_domain_b_reg;
always @(posedge reset or posedge clk_b) begin
if (reset) begin
sig_domain_b_reg <= 2'b0;
end else begin
sig_domain_b_reg[1:0] <= {sig_domain_b_reg[0],... | 6.93182 |
module CrossingBypassWire (
CLK,
WGET,
WVAL
);
parameter width = 1;
input CLK;
input [width - 1 : 0] WVAL;
output [width - 1 : 0] WGET;
assign WGET = WVAL;
endmodule
| 7.91915 |
module CrossingRegA(CLK, RST, Q_OUT, D_IN, EN);
parameter width = 1;
parameter init = { width {1'b0}} ;
input CLK;
input RST;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
always@(posedge CLK or `BSV_RESET_EDGE RST) begin
... | 7.371205 |
module CrossingRegN(CLK, RST, Q_OUT, D_IN, EN);
parameter width = 1;
parameter init = { width {1'b0} } ;
input CLK;
input RST;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
always@(posedge CLK)
begin
if (RST == ... | 7.24068 |
module CrossingRegUN(CLK, EN, D_IN, Q_OUT);
parameter width = 1;
input CLK;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
Q... | 6.730655 |
module Crossover #(
parameter IndividualWidth = 32,
parameter RotationIndexWidth = $clog2(IndividualWidth),
parameter CrossMaskIndexWidth = $clog2(IndividualWidth)
) (
input clk,
input rst,
input ce,
input [IndividualWidth-1:0] dad,
input [IndividualWidth-1:0] mom,
output [Individual... | 8.401536 |
module crossover_engine (
clk,
rst,
bias,
co_prob,
parent_gene0,
parent_gene1,
crossover_gene
);
input clk;
input rst;
input [31:0] parent_gene0;
input [31:0] parent_gene1;
input bias;
input [7:0] co_prob;
reg [7:0] seed_wire1 = 8'b00001110;
reg [7:0] seed_wire2 = 8'b000011... | 6.71003 |
module crossover_selector (
clk,
rst,
bias,
prob,
seed,
select
);
input clk;
input rst;
input [0:0] bias;
input [7:0] prob;
input [7:0] seed;
wire [7:0] random;
lfsr random_lfsr (
.out (random),
.clk (clk),
.rst (rst),
.seed(seed)
);
output reg selec... | 7.792694 |
module crossover_selector_tb ();
reg clk;
reg rst;
reg bias_wire;
reg [3:0] prob_wire;
reg [3:0] random_wire;
wire select_out;
//Block to hint generation of waveforms
initial begin
$vcdplusfile("crossover_selector.vcd");
$vcdplusmemon();
$vcdpluson();
end
//Initialize the design
i... | 7.792694 |
module crossover_tb ();
reg clk;
reg rst;
reg [31:0] parent_gene0_input;
reg [31:0] parent_gene1_input;
wire [31:0] crossover_gene_output;
//Block to hint generation of waveforms
initial begin
$vcdplusfile("crossover.vcd");
$vcdplusmemon();
$vcdpluson();
end
//Initialize the design
i... | 7.128731 |
module dff (
input clk,
D,
output reg Q
);
always @(posedge clk) begin
Q <= D;
end
endmodule
| 7.174483 |
module divider_integer #(
parameter WIDTH = 24,
parameter N = 12000000
) (
input clk,
output reg clkout
);
reg [WIDTH-1:0] cnt;
always @(posedge clk) begin
if (cnt >= (N - 1)) cnt <= 1'b0;
else cnt <= cnt + 1'b1;
clkout <= (cnt < N / 2) ? 1'b1 : 1'b0;
end
endmodule
| 6.687714 |
module dff (
input clk,
D,
output reg Q
);
always @(posedge clk) begin
Q <= D;
end
endmodule
| 7.174483 |
module divider_integer #(
parameter WIDTH = 24,
parameter N = 12000000
) (
input clk,
output reg clkout
);
reg [WIDTH-1:0] cnt;
always @(posedge clk) begin
if (cnt >= (N - 1)) cnt <= 1'b0;
else cnt <= cnt + 1'b1;
clkout <= (cnt < N / 2) ? 1'b1 : 1'b0;
end
endmodule
| 6.687714 |
module ADC_top (
clk_in,
rstn,
digital_out,
analog_cmp,
analog_out,
sample_rdy
);
parameter ADC_WIDTH = 8, // ADC Convertor Bit Precision
ACCUM_BITS = 10, // 2^ACCUM_BITS is decimation rate of accumulator
LPF_DEPTH_BITS = 3, // 2^LPF_DEPTH_BITS is decimation rate of averager
INPUT_TO... | 7.78093 |
module sigmadelta_adc (
clk,
rstn,
digital_out,
analog_cmp,
analog_out,
sample_rdy
);
parameter ADC_WIDTH = 8, // ADC Convertor Bit Precision
ACCUM_BITS = 10, // 2^ACCUM_BITS is decimation rate of accumulator
LPF_DEPTH_BITS = 3; // 2^LPF_DEPTH_BITS is decimation rate of averager
//i... | 6.661028 |
module box_ave (
clk,
rstn,
sample,
raw_data_in,
ave_data_out,
data_out_valid
);
parameter ADC_WIDTH = 8, // ADC Convertor Bit Precision
LPF_DEPTH_BITS = 4; // 2^LPF_DEPTH_BITS is decimation rate of averager
//input ports
input clk; // sample rate clock
input rstn; // async reset... | 8.728438 |
module cross_bar (
rst,
clk,
wr_en,
d,
full,
valid,
q,
stall,
almost_full
);
parameter WIDTH = 8;
parameter IN_PORTS = 8;
parameter OUT_PORTS = IN_PORTS;
parameter FIFO_DEPTH = 32;
parameter IN_PORTS_ADDR_WIDTH = log2(IN_PORTS - 1);
parameter OUT_PORTS_ADDR_WIDTH = log2(O... | 7.178155 |
module cross_bar_tb;
reg rst, clk;
reg [ 0:7] wr_en;
reg [63:0] d;
wire [ 0:7] full;
wire [ 0:7] valid;
wire [63:0] q;
reg [ 0:7] stall;
wire [ 0:7] almost_full;
cross_bar #(8, 8) dut (
rst,
clk,
wr_en,
d,
full,
valid,
q,
stall,
almost_full
);... | 6.612891 |
module cross_clk (
input wire clk_a, //时钟a
input wire clk_b, //时钟b
input wire sys_rst_n, //复位信号
input wire en_a, //a使能信号
output reg en_b //b使能信号
);
//********************************************************************//
//****************** Parameter and Internal Signal *****... | 7.23251 |
module cross_clk_sync #(
parameter LAT = 2,
parameter DSIZE = 1
) (
input clk,
input rst_n,
input [DSIZE-1:0] d,
output [DSIZE-1:0] q
);
reg [DSIZE-1:0] ltc[LAT-1:0];
always @(posedge clk /*,negedge rst_n*/) begin : GEN_LAT
integer II;
if (~rst_n) begi... | 7.355893 |
module cross_clock_data #(
parameter DATA_WIDTH = 8
) (
input rst,
input [DATA_WIDTH - 1:0] in_data,
input out_clk,
output reg [DATA_WIDTH - 1:0] out_data = 0
);
reg [DATA_WIDTH - 1:0] data_sync[2:0];
initial begin
data_sync[0] = 0;
data_sync... | 8.056807 |
module cross_clock_enable (
input rst,
input in_en,
input out_clk,
output reg out_en = 0
);
//Parameters
//Registers/Wires
reg [2:0] out_en_sync = 3'b0;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @(posedge out_clk) begin
if (rst) begin
out_en_sync <= 0;
... | 7.446803 |
module cross_clock_strobe (
input rst,
input in_clk,
input in_stb,
input out_clk,
output out_stb
);
//parameters
//registers/wires
reg toggle_stb;
reg [2:0] sync_out_clk;
//submodules
//asynchronous logic
assign out_stb = (sync_out_clk[2] ^ sync_out_clk[1]);
//synchronous lo... | 6.685204 |
module cross_counter #(
parameter WIDTH = 8,
parameter GRAY_BITS = WIDTH,
parameter OUT_WIDTH = WIDTH,
parameter OUT_LOWER_SKIP = 0,
parameter OUT_RESET_ASYNC = 0,
parameter OUT_PIPELINED = 0
) (
input inrst,
input inclk,
input incmdvalid,... | 7.505285 |
module cross_demux2 #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] din0,
din1,
input sel,
output reg [WIDTH-1:0] dout0,
output reg [WIDTH-1:0] dout1
);
always @(*) begin
if (sel == 1'b0) begin
dout0 = din0;
dout1 = din1;
end else if (sel == 1'b1) begin
dout0 = din1;
... | 6.982016 |
module Flag_CrossDomain (
input clkA,
input FlagIn_clkA,
input clkB,
input ready_to_get_more_data,
output FlagOut_clkB,
output user_w_mydevice_full
);
// this changes level when the FlagIn_clkA is seen in clkA
reg FlagToggle_clkA;
always @(posedge clkA) FlagToggle_clkA <= FlagToggle_c... | 6.720921 |
module Signal_CrossDomain (
input clkA, // we actually don't need clkA in that example, but it is here for completeness as we'll need it in further examples
input SignalIn_clkA,
input clkB,
output SignalOut_clkB
);
// We use a two-stages shift-register to synchronize SignalIn_clkA to the clkB clock... | 7.487392 |
module FlagAck_CrossDomain (
input clkA,
input FlagIn_clkA,
output Busy_clkA,
input clkB,
output FlagOut_clkB
);
reg FlagToggle_clkA;
always @(posedge clkA) FlagToggle_clkA <= FlagToggle_clkA ^ (FlagIn_clkA & ~Busy_clkA);
reg [2:0] SyncA_clkB;
always @(posedge clkB) SyncA_clkB <= {SyncA... | 7.249763 |
module cross_hair (
state,
hcnt,
vcnt,
color,
color_out
);
input state;
input hcnt, vcnt, color;
output color_out;
wire [1:0] state;
wire [9:0] hcnt, vcnt;
wire [2:0] color;
reg [2:0] color_out;
always @(*) begin
if (state == 1) begin //
color_out <= ((vcnt >= 240 && v... | 7.215753 |
module cross_icache_line_size_detector (
input [3:0] OFFSET,
output [4:0] SIZE1,
SIZE2
);
/*
size1[4] = (!offset[3]&!offset[2]&!offset[1]&!offset[0]);
size1[3] = (offset[3]&!offset[2]&!offset[1]&!offset[0]) | (!offset[3]
&offset[0]) | (!offset[3]&offset[2]) | (!offset[3]&offset[1]);
size1[2] = (of... | 6.618476 |
module cross_mlab #(
parameter TARGET_CHIP = 1, // 1 S4, 2 S5
parameter WIDTH = 10 // max speed at width is up to 20 (one lab)
) (
input aclr, // no domain
input din_clk,
input [WIDTH-1:0] din,
input din_valid,
input dout_clk,
output reg [WIDTH-1:0] dout,
output reg dout_valid
)... | 7.310868 |
module cross_switch2x2 #(
parameter WIDTH = 8
) (
input [WIDTH-1:0] a,
b,
input s1,
s2,
output [WIDTH-1:0] x,
y
);
assign x = (s1 == 0) ? b : a;
assign y = (s2 == 0) ? b : a;
endmodule
| 8.515674 |
module cross_v (
input clk,
input pulse,
input en,
input [6:0] qty_v,
input qty_amb,
input [1:0] state_v,
output cross_v,
output cross_amb
);
reg [3:0] cross_countdown;
reg cross_v_reg;
reg cross_amb_reg;
always @(posedge clk) begin
cross_v_reg <= 0;
cross_amb_reg <= ... | 7.326443 |
module mux (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input sel;
input [3:0] dc1, dc0;
input carc0, carc1;
output cout;
output [3:0] data;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.856429 |
module CrsRegFile (
input Clk,
input Rst,
//Wb阶段，对现场进行保存
input [`DataBus] CsrWriteDataClintIn,
input [11:0] CsrWriteAddrClintIn,
input CsrWriteEnableClintIn,
output [`DataBus] CsrMstatusReadDataToClint,
output [`DataBus] CsrMtvecReadDataToClint,
output [`DataBus] CsrMepcReadDataToCli... | 7.83522 |
module crtc (
// CPU Clock Domain
input wire clk_i
, input wire rst_i
, input wire enable_i
, input wire [11:0] ha_i
, input wire [11:0] hfw_i
, input wire [11:0] hsw_i
, input wire [11:0] hbw_i
, input wire [11:0] va_i
, input wire [11:0] vfw_i
, input wire [11:0] vsw_i... | 7.864962 |
module CRTClock2015fall_tb;
reg Reset, Clock;
wire PixelClock;
reg [9:0] SystemClockFreq;
reg [9:0] CRTClockFreq;
CRTClock uut (
SystemClockFreq,
CRTClockFreq,
PixelClock,
Reset,
Clock
);
initial begin
SystemClockFreq = 100;
CRTClockFreq = 25;
Reset = 0;
Cl... | 6.606075 |
module
// hsync <= ~(xposos > 664 && xposos <= 760); // active for 95 clocks
// vsync <= ~(yposos == 490 || yposos == 491); // active for lines 490 and 491
module CRTcontroller2015fall(Xresolution, Yresolution, SystemClockFreq, CRTClockFreq, hsync, vsync, xpos, ypos, reset, clock);
parameter ResolutionSize=10, S... | 7.686434 |
module CRTcontroller2015fall_tb;
//change pixel clock to 10
reg [9:0] Xresolution, Yresolution;
reg [9:0] SystemClock;
reg reset, clock;
wire hsync, vsync;
wire [9:0] xposition, yposition;
wire PixelClock = uut.PixelClock;
// Instantiate the Unit Under Test (UUT)
CRTcontroller2015fall uut (
Xr... | 7.331444 |
module CRTC_IOB (
reset_in,
clk_in,
hsync_in,
vsync_in,
rgb_in,
hsync_out,
vsync_out,
rgb_out
);
input reset_in, clk_in;
input hsync_in, vsync_in;
input [15:4] rgb_in;
output hsync_out, vsync_out;
output [15:4] rgb_out;
reg hsync_out, vsync_out;
reg [15:4] rgb_out;
... | 6.726124 |
module crtc_tb;
parameter WIDTH = 10;
parameter MSB = WIDTH - 1;
reg clock = 1;
always #5 clock <= ~clock;
reg reset_n = 1;
wire vsync, hsync;
wire vblank, hblank;
wire de;
wire [MSB:0] row, col;
initial begin : Sim
$write("%% ");
$dumpfile("tb.vcd");
$dumpvars; // (1, CNTRL0, dd... | 7.392253 |
module crtl_generater (
pps,
rst,
crtl_pps1
);
input rst;
input pps;
output reg crtl_pps1;
reg crtl_pps_reg;
always @(posedge pps) begin
if (!rst) begin
crtl_pps_reg <= 0;
end else begin
crtl_pps_reg <= ~crtl_pps_reg;
end
crtl_pps1 = crtl_pps_reg;
end
endmodule... | 6.717976 |
module: Crtl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module crtl_test;
// Inputs
reg [5:0] OPCode;
reg [5:0] FunctCode;
// Outputs
wire [1:0] MemtoReg;
wire MemWrite;
wire ... | 6.52739 |
module crttest (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB VGA
);
/*******************************************************
* ... | 6.547093 |
module crt_address_decoder (
addr,
cs,
q
);
localparam WIDTH = 4;
localparam OUTPUT_WIDTH = {1'b1, {WIDTH{1'b0}}};
input [WIDTH-1:0] addr;
input cs;
output [OUTPUT_WIDTH-1:0] q;
reg [OUTPUT_WIDTH-1:0] m;
assign q = m & {OUTPUT_WIDTH{cs}};
always @(addr) begin
case (addr)
defaul... | 8.278685 |
module crt_register (
clk,
reset,
resetvalue,
cs,
we,
value,
data
);
parameter WIDTH = 16;
input wire clk;
input wire reset;
input wire [WIDTH-1:0] resetvalue;
input wire cs;
input wire we;
output reg [WIDTH-1:0] value;
inout wire [WIDTH-1:0] data;
wire cs_wr = cs & we;
... | 7.627099 |
module crt_ramdac (
clk,
pixaddr,
ven,
qpixel,
breq,
back
);
parameter ADDR_SIZE = 32;
localparam PIXEL_SIZE = 32;
input clk;
input [ADDR_SIZE-1:0] pixaddr;
input ven;
output [PIXEL_SIZE-1:0] qpixel;
output breq;
input back;
always @(posedge clk) begin
end
endmodule
| 7.2647 |
module crubits (
// select
input [0:3] cru_base,
// TI clock input
input ti_cru_clk,
// TI mem enable (when high, not a memory operation
input ti_memen,
// FPGA synchronous clock
input clk,
// cru_address
input [0:14] addr,
// input
input ti_cru_out,
// input to TMS99... | 7.151741 |
module cruce_eo (
input [6:0] N_eo,
input [1:0] contador,
input [5:0] luces,
output auto_cruza
);
wire verde_eo = luces[5];
wire amarillo_eo = luces[4];
wire rojo_eo = luces[3];
assign auto_cruza = contador == 2'd0 & N_eo > 6'd0 & verde_eo == 1;
endmodule
| 7.552639 |
module cruce_sn (
input [6:0] N_sn,
A,
input [1:0] contador,
input [5:0] luces,
output auto_cruza,
output amb_cruza
);
wire verde_sn = luces[2];
wire amarillo_sn = luces[1];
wire rojo_sn = luces[0];
assign auto_cruza = contador == 2'd0 & N_sn > 6'd0 & verde_sn & ~A;
assign amb_cruza... | 6.849859 |
module cryomodule_badger (
input clk1x,
input clk2x,
input gmii_tx_clk,
input gmii_rx_clk,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
output [7:0] gmii_txd,
output gmii_tx_en,
output gmii_tx_er,
// Ethernet configuration port
input eth_cfg_clk,
input [9... | 6.653625 |
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