code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cryomodule_badger_tb;
// based mostly on aggregate_tb.v
parameter [31:0] ip = 32'd3232237316; // 192.168.7.4
parameter [47:0] mac = 48'h112233445566;
// Buffer memory to hold a packet read from a file
parameter max_data_len = 1024;
reg [7:0] pack_mem[0:max_data_len-1];
reg clk;
integer cc;
... | 6.653625 |
module selectRomOutput (
input [2:0] romColourOutput1,
input [2:0] romColourOutput2,
input [1:0] selectRom,
output reg [2:0] romColourOutput
);
always @(*) begin
case (selectRom)
2'd0: romColourOutput = 3'b000;
2'd1: romColourOutput = romColourOutput1;
2'd2: romColourOutput = ro... | 8.467311 |
module selectCounter (
input selectCounters,
input [5:0] xcounter,
input [5:0] ycounter,
input [7:0] startX,
input [6:0] startY,
input [5:0] xcounterL,
input [5:0] ycounterL,
input [7:0] startXL,
input [6:0] startYL,
output reg [5:0] xcounterF,
output reg [5:0] ycounterF,
... | 6.919419 |
module drawNumberOutput (
input clk,
input draw,
input v0flag,
v1flag,
v0erase,
v1erase,
input [7:0] startXWire,
input [6:0] startYWire,
input [12:0] startAddress,
output reg [5:0] xcounter,
output reg [5:0] ycounter,
output reg [7:0] startX,
output reg [6:0] startY,
... | 6.716252 |
module drawLetterOutput (
input clk,
input drawLetter,
input v0flag,
v1flag,
v0erase,
v1erase,
input [7:0] startXWire,
input [6:0] startYWire,
input [12:0] startAddress,
output reg [5:0] xcounterL,
output reg [5:0] ycounterL,
output reg [7:0] startXL,
output reg [6:0]... | 6.652364 |
module RateDivider (
input enable,
input Clock,
input [25:0] D,
output reg [25:0] Q,
input reset
);
always @(posedge Clock, negedge reset) begin
if (reset == 0) Q <= 26'd0;
else if (enable == 1'b0 || (Q == 26'd0)) Q <= D;
else Q <= Q - 26'd1;
end
endmodule
| 8.599311 |
module DisplayCounter (
input Enable,
Clock,
output reg [3:0] Q,
input reset
);
always @(posedge Clock) begin
if (reset == 0) Q <= 4'd0;
else if (Q == 4'd15) Q <= 4'd0;
else if (Enable == 1'b1) Q <= Q + 4'b0001;
end
endmodule
| 8.070283 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001... | 7.584821 |
module m1crypto (
input sysclk,
input resetn,
input [47:0] key,
input load_key,
input ser_in,
input start,
input fb,
output reg trx_ks,
output wire trx_fout
);
wire ks;
reg [47:0] lfsr;
wire linear_feedback = lfsr[0] ^ lfsr[5] ^ lfsr[9] ^ lfsr[10] ^ lfsr[12] ^
... | 6.881145 |
module mult_gen_0 (
input CLK,
input [63:0] A,
input [63:0] B,
output reg [127:0] P
);
always @(posedge CLK) begin
P <= A * B;
end
endmodule
| 6.555383 |
module go_CDC_go (
input clk_i,
input rstn_i,
input go_i,
input clk_o,
input rst_o,
output go_o
);
//##################### clk_i domain ################################33
reg flip_i;
always @(posedge clk_i or negedge rstn_i)
if (!rstn_i) flip_i <= 0;
else if (go_i) flip_i <... | 8.376076 |
module crypto_wallet2_nios (
clk_clk,
epcs_flash_controller_external_dclk,
epcs_flash_controller_external_sce,
epcs_flash_controller_external_sdo,
epcs_flash_controller_external_data0,
po_led_external_connection_export,
reset_reset_n,
sdram_wire_addr,
sdram_wire_ba,
sdram_wire_ca... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [26:0]... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] sw... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free ... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(emp... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.556583 |
module crypto_wallet2_nios_cpu_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
o... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_nios2_performance_monitors;
endmodule
| 6.556583 |
module crypto_wallet2_nios_cpu_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
t... | 6.556583 |
module crypto_wallet2_nios_cpu_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
inpu... | 6.556583 |
module crypto_wallet2_nios_fast (
clk_clk,
epcs_flash_controller_external_dclk,
epcs_flash_controller_external_sce,
epcs_flash_controller_external_sdo,
epcs_flash_controller_external_data0,
pi_random_external_connection_export,
po_led_external_connection_export,
po_random_seed_external_c... | 6.556583 |
module crypto_wallet2_nios_fast_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
inp... | 6.556583 |
module crypto_wallet2_nios_fast_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
inp... | 6.556583 |
module crypto_wallet2_nios_fast_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst... | 6.556583 |
module crypto_wallet2_nios_fast_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
in... | 6.556583 |
module crypto_wallet2_nios_fast_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "crypto_wallet2_nios_fast_onchip_memory2.hex";
output [31:0] read... | 6.556583 |
module crypto_wallet2_nios_fast_pi_random_value (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [7:0] in_port;
input reset_n;
wire clk_en;
wire [ 7:0] data_in;
wire [ 7:0] read_mux_o... | 6.556583 |
module crypto_wallet2_nios_fast_po_led (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write... | 6.556583 |
module crypto_wallet2_nios_fast_po_random_seed (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
in... | 6.556583 |
module crypto_wallet2_nios_fast_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [42:0] rd_data;
inp... | 6.556583 |
module crypto_wallet2_nios_fast_sysid (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1549997543 : 0;
e... | 6.556583 |
module crypto_wallet2_nios_fast_uart_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
);
output source_rxd;
input [12:0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;... | 6.556583 |
module crypto_wallet2_nios_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fi... | 6.556583 |
module crypto_wallet2_nios_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fi... | 6.556583 |
module crypto_wallet2_nios_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
... | 6.556583 |
module crypto_wallet2_nios_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input c... | 6.556583 |
module crypto_wallet2_nios_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "crypto_wallet2_nios_onchip_memory2.hex";
output [31:0] readdata;
in... | 6.556583 |
module crypto_wallet2_nios_pi_random (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [31:0] in_port;
input reset_n;
wire clk_en;
wire [31:0] data_in;
wire [31:0] read_mux_out;
reg ... | 6.556583 |
module crypto_wallet2_nios_pi_random_value (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [7:0] in_port;
input reset_n;
wire clk_en;
wire [ 7:0] data_in;
wire [ 7:0] read_mux_out;
... | 6.556583 |
module crypto_wallet2_nios_po_led (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 6.556583 |
module crypto_wallet2_nios_po_random_seed (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input w... | 6.556583 |
module crypto_wallet2_nios_po_random_seed_high (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
in... | 6.556583 |
module crypto_wallet2_nios_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [42:0] rd_data;
input cl... | 6.556583 |
module crypto_wallet2_nios_sysid (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1549548728 : 0;
endmod... | 6.556583 |
module crypto_wallet2_nios_uart_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
);
output source_rxd;
input [8:0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;
r... | 6.556583 |
module CryptRingOscillator (
reset,
clkout
);
input wire reset;
(* S = "yes" *) output wire clkout;
//Inverter stage
(* S = "yes" *) wire dout0;
(* S = "yes" *) (* RLOC = "X0Y0" *) LUT2 #(
.INIT(2'b0001)
) nor0 (
.O (dout0),
.I0(clkout),
.I1(reset)
);
//Buffer stages
... | 6.569643 |
module CryptRingOscillatorColumn (
clk,
reset,
clkout
);
input wire clk;
input wire reset;
output reg clkout = 0;
//The oscillators
//Stagger different ring lengths in hopes of having less coupling
(* S = "yes" *) wire [9:0] clkout_raw;
(* RLOC = "X0Y0" *) CryptRingOscillator ring0 (
... | 6.569643 |
module crypt_cycle_salt (
input [31:0] L,
input [31:0] R,
input [67:0] K,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
wire [31:0] Ltmp[14:0];
wire [31:0] Rtmp[14:0];
wire [67:0] Ktmp[14:0];
crypt_shift_salt_1 crypt_shift_salt_instance1 (
L,
... | 7.12137 |
module crypt_shift_salt_1 (
input [31:0] L,
input [31:0] R,
input [67:0] K,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
wire [55:0] Ktmp;
wire [47:0] Ktmp_in;
shifts_s1 shifts_s1_instance1 (
K[55:0],
Ktmp
);
Delay3_salt delay3_instance_s... | 6.793408 |
module crypt_shift_salt_2 (
input [31:0] L,
input [31:0] R,
input [67:0] K,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
wire [55:0] Ktmp;
wire [47:0] Ktmp_in;
shifts_s2 shifts_s2_instance2 (
K[55:0],
Ktmp
);
Delay3_salt delay3_instance_s... | 6.793408 |
module cr_adler (
adler_out,
clk,
rst_n,
data_in,
bytes_valid,
sof
);
input clk;
input rst_n;
input [63:0] data_in;
input [7:0] bytes_valid;
input sof;
output logic [31:0] adler_out;
int i;
logic [ 7:0] data_arr [8];
logic [15:0] b_out;
logic [15:0] a_int_... | 6.891373 |
module cr_axi4s2_slv (
axi4s_ib_out,
axi4s_slv_out,
axi4s_slv_empty,
axi4s_slv_aempty,
axi4s_slv_bimc_odat,
axi4s_slv_bimc_osync,
axi4s_slv_ro_uncorrectable_ecc_error,
clk,
rst_n,
axi4s_ib_in,
axi4s_slv_rd,
axi4s_slv_bimc_idat,
axi4s_slv_bimc_isync,
bimc_rst_n
)... | 7.901777 |
module cr_axi4s_slv (
axi4s_ib_out,
axi4s_slv_out,
axi4s_slv_empty,
axi4s_slv_aempty,
clk,
rst_n,
axi4s_ib_in,
axi4s_slv_rd
);
`include "cr_structs.sv"
parameter N_ENTRIES = 16;
parameter N_AFULL_VAL = 1;
parameter N_AEMPTY_VAL = 1;
localparam N_DATA_BITS = $bits(ax... | 7.602612 |
module cr_axi4s_slv2 (
axi4s_ib_out,
axi4s_slv_out,
axi4s_slv_empty,
axi4s_slv_aempty,
overflow,
clk,
rst_n,
axi4s_ib_in,
axi4s_slv_rd
);
`include "cr_structs.sv"
parameter N_ENTRIES = 16;
parameter N_AFULL_VAL = 1;
parameter N_AEMPTY_VAL = 1;
localparam N_DATA_... | 7.296335 |
module cr_cdc_fifo_wrap1 (
full,
afull,
rdata,
empty,
aempty,
wclk,
wrst_n,
rclk,
rrst_n,
wdata,
wen,
ren
);
parameter N_DATA_BITS = 64;
parameter N_ENTRIES = 8;
parameter N_AFULL_VAL = 1;
parameter N_AEMPTY_VAL = 1;
parameter TYPE = 0;
`include "c... | 7.667743 |
module cr_cddip_sa (
rbus_ring_o,
clk,
rst_n,
scan_en,
scan_mode,
scan_rst_n,
ovstb,
lvm,
mlvm,
rbus_ring_i,
cfg_start_addr,
cfg_end_addr,
isf_stat_events,
osf_stat_events,
xp10_decomp_lz77d_stat_events,
xp10_decomp_hufd_stat_events,
crcc0_stat_event... | 6.645142 |
module cr_cddip_support_core (
pipe_stat,
cddip_int,
cddip_idle,
sup_osf_halt,
clk,
rst_n,
osf_sup_cqe_exit,
isf_sup_cqe_exit,
isf_sup_cqe_rx,
isf_sup_rqe_rx,
pre_cddip_int
);
`include "cr_structs.sv"
import cr_cddip_supportPKG::*;
import cr_cddip_support_regsPKG::*... | 6.902853 |
module cr_clic_arb_kernel (
// input
prio_in_vec,
// output
sel_out_onehot
);
parameter PRIO_WIDTH = 6;
parameter INT_NUM = 32;
parameter PRIO_EXP_NUM = 1 <<< PRIO_WIDTH;
input [PRIO_WIDTH*INT_NUM-1:0] prio_in_vec;
output [INT_NUM-1:0] sel_out_onehot;
wire [ INT_NUM-1:0] sel_out_oneh... | 7.287492 |
module cr_clic_ff1_onehot (
data_in,
ff1_out_onehot
);
parameter WIDTH = 32;
input [WIDTH-1:0] data_in;
output [WIDTH-1:0] ff1_out_onehot;
wire [WIDTH:0] ff1_tmp;
assign ff1_tmp[WIDTH] = 1'b0;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : FF1_ONEHOT
assign ff1_tmp[i] ... | 7.582297 |
module cr_clic_sel (
// input
data_in,
sel_in_onehot,
// output
data_out
);
parameter DATA_WIDTH = 32;
parameter SEL_NUM = 256;
input [DATA_WIDTH*SEL_NUM-1:0] data_in;
input [SEL_NUM-1:0] sel_in_onehot;
output [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] data_in_2d [ SEL_NUM... | 8.161387 |
module cr_clint_busif (
busif_regs_msip_sel,
busif_regs_mtimecmp_hi_sel,
busif_regs_mtimecmp_lo_sel,
busif_regs_wdata,
busif_regs_write_vld,
clint_tcipif_cmplt,
clint_tcipif_rdata,
msip_value,
mtime_hi_value,
mtime_lo_value,
mtimecmp_hi_value,
mtimecmp_lo_value,
tcipi... | 7.035968 |
module cr_clkrst_top (
cpurst_b,
forever_cpuclk,
forever_cpuclk_nogated,
forever_jtgclk,
hadrst_b,
pad_cpu_rst_b,
pad_had_jtg_tclk,
pad_had_jtg_trst_b,
pad_had_rst_b,
pad_yy_test_mode,
pll_core_cpuclk,
trst_b
);
// &Ports; @23
input pad_cpu_rst_b;
input pad_had_jtg... | 6.784996 |
module cr_crc #(
parameter POLYNOMIAL = 32'h82F63B78,
parameter N_CRC_WIDTH = 32,
parameter N_DATA_WIDTH = 64
) (
crc,
clk,
rst_n,
data_in,
data_valid,
data_vbytes,
enable,
init_value,
init
);
`include "ccx_std.vh"
localparam N_VBYTES_WIDTH = N_DATA_WIDTH / 8;
... | 7.551736 |
module cr_crc16t (
crc,
clk,
rst_n,
data_in,
data_valid,
data_vbytes,
enable,
init_value,
init
);
`include "ccx_std.vh"
localparam N_CRC_WIDTH = 16;
localparam N_DATA_WIDTH = 64;
localparam N_VBYTES_WIDTH = N_DATA_WIDTH / 8;
localparam POLYNOMIAL = 16'hEDD1;
input clk... | 6.89258 |
module cr_crcgc #(
parameter STUB_MODE = 0
) (
crcgc_ib_out,
rbus_ring_o,
crcgc_ob_out,
crcgc_stat_events,
crcgc_int,
clk,
rst_n,
scan_en,
scan_mode,
scan_rst_n,
ovstb,
lvm,
mlvm,
ext_ib_out,
crcgc_ib_in,
rbus_ring_i,
cfg_start_addr,
cfg_end_... | 6.507869 |
module cr_crcgc_crc
#(
parameter POLYNOMIAL = 32'h82F63B78,
parameter N_CRC_WIDTH = 32,
parameter N_DATA_WIDTH = 64
)
(
crc,
clk, rst_n, data_in, data_valid, data_vbytes, enable, init_value,
init
);
`include "ccx_std.vh"
localparam N_VBYTES_WIDTH = N_DATA_WIDTH/8;
... | 7.721121 |
module cr_div (
rst,
clk,
addr,
start,
a,
b,
q,
r,
done
);
parameter IDLE = 3'd1;
parameter RECIP = 3'd2;
parameter RECIP1 = 3'd3;
parameter DONE = 3'd4;
input rst;
input clk;
input [31:0] addr;
input start;
input [31:0] a;
input [31:0] b;
output [31:0] q;
out... | 7.45054 |
module cr_dual_rank_synchronizer (
clk,
rst_n,
din,
dout
);
parameter WIDTH = 1;
parameter RESET_VAL = 0;
input clk;
input rst_n;
input din;
output dout;
assign dout = rst_n;
endmodule
| 6.90577 |
module cr_engine (
input clk,
input rst_n,
// Inputs
input [ `FLOW_ID_W-1:0] enq_fid_in,
input [`FLOW_SEQ_NUM_W-1:0] enq_seq_in,
input [ `TX_CNT_W-1:0] enq_seq_tx_id_in,
input [`DD_CONTEXT_W-1:0] dd_cntxt_in,
input [ `FLOW_ID_W-1:0] ... | 6.516137 |
module cr_fifo_wrap1 (
full,
afull,
rdata,
empty,
aempty,
clk,
rst_n,
wdata,
wen,
ren
);
parameter N_DATA_BITS = 64;
parameter N_ENTRIES = 8;
parameter N_AFULL_VAL = 1;
parameter N_AEMPTY_VAL = 1;
`include "cr_structs.sv"
input clk;
input rst_n;
... | 7.625515 |
module cr_fifo_wrap3 (
full,
afull,
rdata,
empty,
aempty,
overflow,
clk,
rst_n,
wdata,
wen,
ren
);
parameter N_DATA_BITS = 64;
parameter N_ENTRIES = 8;
parameter N_AFULL_VAL = 1;
parameter N_AEMPTY_VAL = 1;
`include "cr_structs.sv"
input clk;
inpu... | 7.69134 |
module cr_file_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f (
clk,
\d_in.read ,
\w_in.write_cr_enable ,
\w_in.write_cr_mask ,
\w_in.write_cr_data ,
\w_in.write_xerc_enable ,
\w_in.write_xerc_data ,
sim_dump,
\d_out.read_cr_data ,
\d_out.read_xerc_data ,
log_out
);
wire [ 3:0]... | 6.5823 |
module cr_had_sync_level (
clk1,
clk2,
rst1_b,
rst2_b,
sync_in,
sync_out
);
// &Ports; @25
input clk1;
input clk2;
input rst1_b;
input rst2_b;
input sync_in;
output sync_out;
// &Regs; @26
reg sync_ff1_clk1;
reg sync_ff2_clk1;
reg sync_ff_clk2;
// &Wires; @27
wire... | 7.134087 |
module cr_ifu_randclk (
randclk_ibuf_entry_data_mod_en_w16,
randclk_ibuf_pop_mod_en_w3,
randclk_ibuf_push_mod_en_w3
);
// &Ports; @25
output [3:0] randclk_ibuf_entry_data_mod_en_w16;
output randclk_ibuf_pop_mod_en_w3;
output randclk_ibuf_push_mod_en_w3;
// &Regs; @26
// &Wires; @27
wire [3:... | 6.978987 |
module cr_iu_special (
cp0_iu_cache_inv_done,
ctrl_special_ex_data_sel,
ctrl_special_ex_sel,
ctrl_special_expt_vec,
ctrl_special_expt_vld,
decd_special_fencei,
decd_special_icall,
decd_special_icpa,
special_ctrl_stall,
special_ctrl_stall_noinput,
special_pcgen_chgflw_vld,
... | 6.573442 |
module cr_kme_fifo (
fifo_in_stall,
fifo_out,
fifo_out_valid,
fifo_overflow,
fifo_underflow,
clk,
rst_n,
fifo_in,
fifo_in_valid,
fifo_out_ack,
fifo_in_stall_override
);
parameter DATA_SIZE = 10;
parameter FIFO_DEPTH = 2;
parameter OVERRIDE_EN = 0;
parameter STALL_A... | 8.266262 |
module cr_kme_key_tlv_rsm (
usr_ob_full,
usr_ob_afull,
axi4s_ob_out,
stat_stall_on_valid_key,
key_tlv_rsm_end_pulse,
key_tlv_rsm_idle,
clk,
rst_n,
usr_ob_wr,
usr_ob_tlv,
axi4s_ob_in
);
`include "cr_kme_body_param.v"
input clk;
input rst_n;
input usr_ob_wr;... | 7.09526 |
module cr_kme_kop_kdf_keyfilter (
keyfilter_cmdfifo_ack,
keyfilter_upsizer_stall,
hash_key_in,
hash_key_in_valid,
clk,
rst_n,
cmdfifo_keyfilter_valid,
cmdfifo_keyfilter_cmd,
upsizer_keyfilter_data,
upsizer_keyfilter_valid,
upsizer_keyfilter_eof,
hash_key_in_stall
);
... | 7.197113 |
module cr_kme_kop_kdf_stream_pipe (
pipe_valid,
pipe_data,
pipe_byte_count,
clk,
rst_n,
cmd_valid,
cmd_data_size,
cmd_data,
pipe_ack,
pipe_ack_num_bytes
);
`include "cr_kme_body_param.v"
parameter IN_DATA_SIZE_IN_BYTES = 4;
localparam IN_DATA_SIZE_IN_BITS = IN_DATA_S... | 7.197113 |
module cr_kme_ram_fifo (
fifo_in_stall,
fifo_out,
fifo_out_valid,
fifo_bimc_osync,
fifo_bimc_odat,
fifo_mbe,
clk,
rst_n,
fifo_in,
fifo_in_valid,
fifo_out_ack,
bimc_rst_n,
fifo_bimc_isync,
fifo_bimc_idat
);
parameter DATA_SIZE = 10;
parameter FIFO_DEPTH = 2;... | 7.077227 |
module bm_phase_compare (
input_data,
hb,
compare_en,
bm_phase
);
input [7:0] input_data;
input [7:0] hb;
input compare_en;
output wire bm_phase;
`ifdef FAST_RTL_NO_GATES
assign bm_phase = (input_data == hb) && compare_en;
`else
wire [7:0] n;
wire [7:0] x;
assign n = ~(input_da... | 7.719344 |
module cr_lz77_comp_pmu (
lob_events,
clk,
rst_n,
pac_exg_data,
pac_exg_val,
exg_pmu_bypass_stb,
exg_pmu_eof_stb,
exg_pmu_enable_stats
);
`include "cr_lz77_comp_includes.vh"
input clk;
input rst_n;
input packer_symbol_bus_t pac_exg_data;
input pac_exg_val;
input exg_pmu... | 7.104791 |
module cr_lz77_comp_snode #(
parameter T_WIDTH = 4,
parameter T_MASK = 0,
parameter OI_WIDTH = 1
) (
therm_out,
offset_out,
therm_in_0,
therm_in_1,
offset_in_0,
offset_in_1
);
localparam OI_ADJ_W = (OI_WIDTH == 0) ? 1 : OI_WIDTH;
input [T_WIDTH-1:0] therm_in_0;
input [T_... | 7.104791 |
module cr_lz77_comp_stree #(
parameter GROUP_NUM = 1,
parameter OFFSETS = 2,
parameter T_WIDTH = 4,
parameter T_MASK = 0,
parameter OI_WIDTH = 1
) (
therm_out,
offset_out,
therm_in,
offset_in
);
localparam LEVELS = $clog2(OFFSETS);
localparam OI_ADJ_W = (OI_WIDTH == 0)... | 7.104791 |
module
// Project Name: SRT Correlator
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cr_muxes(
input we_coeff,
... | 7.088073 |
module cr_prefix_fe (
feature_ctr,
fe_ctr_1,
fe_ctr_2,
fe_ctr_3,
fe_ctr_4,
clk,
rst_n,
fe_config,
ibc_data_tlv_tdata,
ibc_data_vbytes,
ibc_blk_sel,
ibc_ctr_reload
);
`include "cr_structs.sv"
import cr_prefixPKG::*;
import cr_prefix_regsPKG::*;
input clk;
... | 6.597775 |
module cr_prefix_fe_char (
fe_char_match,
clk,
rst_n,
fe_config,
fe_prior_in,
fe_char_in,
fe_char_valid
);
`include "cr_structs.sv"
import cr_prefixPKG::*;
import cr_prefix_regsPKG::*;
input clk;
input rst_n;
input feature_t fe_config;
input fe_prior_in;
input... | 7.375486 |
module cr_prefix_fe_cmp (
prior_out,
clk,
rst_n,
prior_in,
prior_in_no_delay,
char_in,
char_valid,
use_prior,
no_delay,
match_val,
cmp_type
);
`include "cr_structs.sv"
import cr_prefixPKG::*;
import cr_prefix_regsPKG::*;
input clk;
input rst_n;
input p... | 7.375486 |
module cr_prefix_fe_cmpa (
cmp_r,
char_valid_r,
clk,
rst_n,
char_in,
char_valid,
match_val,
cmp_type
);
`include "cr_structs.sv"
import cr_prefixPKG::*;
import cr_prefix_regsPKG::*;
input clk;
input rst_n;
input [7:0] char_in;
input char_valid;
input [7:0... | 7.375486 |
module cr_prefix_fe_ctr (
fe_ctr_1k,
fe_ctr_2k,
fe_ctr_3k,
fe_ctr_4k,
fe_prior_out,
clk,
rst_n,
fe_config,
fe_prior_in,
fe_ctlr_eodb,
fe_sel_1k,
fe_char_in,
fe_char_vbytes
);
`include "cr_structs.sv"
import cr_prefixPKG::*;
import cr_prefix_regsPKG::*;
... | 7.375486 |
module cr_prefix_fe_grp (
fe_ctr_1k,
fe_ctr_2k,
fe_ctr_3k,
fe_ctr_4k,
clk,
rst_n,
fe_config,
fe_ctlr_eodb,
fe_sel_1k,
fe_char_in,
fe_char_vbytes
);
`include "cr_structs.sv"
import cr_prefixPKG::*;
import cr_prefix_regsPKG::*;
input clk;
input rst_n;
in... | 7.375486 |
module cr_rst_sync (
input clk,
input async_rst_n,
input bypass_reset,
input test_rst_n,
output rst_n
);
wire sync_rst_n;
wire dual_rank_rst_n;
assign dual_rank_rst_n = (bypass_reset && test_rst_n) || async_rst_n;
cr_dual_rank_synchronizer #(
.WIDTH(1),
.RESET_VAL(0)
) r... | 7.105063 |
module cr_rst_top (
cpurst_b,
hadrst_b,
pad_cpu_rst_b,
pad_had_jtg_trst_b,
pad_had_rst_b,
pad_yy_test_mode,
trst_b
);
// &Ports; @23
input pad_cpu_rst_b;
input pad_had_jtg_trst_b;
input pad_had_rst_b;
input pad_yy_test_mode;
output cpurst_b;
output hadrst_b;
output trst_b;
... | 7.365069 |
module cr_sa_counter (
sa_count,
sa_snapshot,
clk,
rst_n,
sa_event_sel,
sa_events,
sa_clear,
sa_snap
);
`include "cr_structs.sv"
input clk;
input rst_n;
input [9:0] sa_event_sel;
input [63:0] sa_events[15:0];
input sa_clear;
input sa_snap;
output logic ... | 6.716346 |
module cr_tcipif_dummy_bus (
bmu_tcipif_ibus_acc_deny,
bmu_tcipif_ibus_addr,
bmu_tcipif_ibus_req,
bmu_tcipif_ibus_write,
cpurst_b,
forever_cpuclk,
pad_yy_gate_clk_en_b,
tcipif_bmu_ibus_acc_err,
tcipif_bmu_ibus_data,
tcipif_bmu_ibus_data_vld,
tcipif_bmu_ibus_grnt,
tcipif_b... | 7.807747 |
module cr_xp10_decomp_be_tlvp (
xp10_decomp_ob_out,
pt_ob_rd,
lz_data_full,
lz_data_afull,
clk,
rst_n,
xp10_decomp_ob_in,
pt_ob_empty,
pt_ob_aempty,
pt_ob_tlv,
lz_data_wr,
lz_data_tlv
);
import crPKG::*;
import cr_xp10_decompPKG::*;
import cr_xp10_decomp_regsPKG:... | 6.66545 |
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