code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cr_xp10_decomp_fe_crc (
crc_out,
clk,
rst_n,
sof,
crc_in,
data_in,
data_sz
);
import crPKG::*;
import cr_xp10_decompPKG::*;
import cr_xp10_decomp_regsPKG::*;
input clk;
input rst_n;
input sof;
input [31:0] crc_in;
input [63:0] data_in;
input [6:0] data_sz;
out... | 6.66545 |
module cr_xp10_decomp_fe_tlvp (
xp10_decomp_ib_out,
fhp_tlvp_pt_tlv,
fhp_tlvp_pt_empty,
fhp_tlvp_usr_empty,
fhp_tlvp_usr_tlv,
fe_tlvp_error,
clk,
rst_n,
xp10_decomp_ib_in,
fhp_tlvp_pt_rd,
fhp_tlvp_usr_rd,
sw_TLVP_ACTION_CFG0,
sw_TLVP_ACTION_CFG1,
xp10_decomp_mod... | 6.66545 |
module cr_xp10_decomp_htf_array_inc (
array,
clk,
rst_n,
preload_en,
preload_data,
inc_onehot
);
parameter RANGE_BASE = 1;
parameter DEPTH = 27;
parameter WIDTH = 10;
parameter NUM_INC_PORTS = 2;
input clk;
input rst_n;
input logic [`BIT_VEC_BASE(DEPTH, RANGE_BASE)] prel... | 6.66545 |
module cr_xp10_decomp_htf_bct_sat_writer (
bct_sat_wen,
bct_sat_addr,
bct_sat_last,
bct_valid,
bct_data,
sat_data,
bct_sat_error,
clk,
rst_n,
hist_complete,
hist_depth,
histogram
);
parameter MAX_DEPTH = 27;
parameter WIDTH = 10;
input clk;
input rst_n;
i... | 6.66545 |
module cr_xp10_decomp_htf_blt (
blt, blt_depth,
clk, rst_n, blt_wdata, blt_wen, blt_start
);
parameter DEPTH = 576;
parameter WIDTH = 5;
parameter NUM_WR_PORTS = 2;
parameter CLEAR_ON_FIRST_WRITE = 0;
input clk;
input rst_n;
input [`BIT_VEC(NUM_WR_PO... | 6.66545 |
module cr_xp10_decomp_htf_histogram (
histogram,
clk, rst_n, hist_waddr, hist_inc, hist_start
);
parameter DEPTH = 27;
parameter WIDTH = 10;
parameter NUM_INC_PORTS = 2;
input clk;
input rst_n;
input [`BIT_VEC(NUM_INC_PORTS)][`LOG_VEC(DEPTH+1)] hist_... | 6.66545 |
module cr_xp10_decomp_unpacker
(
src_ready, dst_items_avail, dst_data, dst_last,
clk, rst_n, src_items_valid, src_data, src_last, dst_items_consume,
clear
);
parameter IN_ITEMS = 64;
parameter OUT_ITEMS = 16;
parameter MAX_CONSUME_ITEMS = 16;
parameter BITS_PER_ITEM = 1;
... | 6.66545 |
module CS151_ALU(
input [31:0] operandA,
input [31:0] operandB,
input [3:0] ALUopsel, // not sure what the size of the array should be
output [31:0] ALUresult,
output overflow,
output equal,
output [1:0] carry// can use a AND gate to see if there is a carry out of 1 or 0 when adding and can use no... | 7.414765 |
module parking_system (
input clk,
reset_n,
input sensor_entrance,
sensor_exit,
input [1:0] password,
output wire GREEN_LED,
RED_LED,
output reg [2:0] state,
output reg [3:0] number,
output reg [9:0] fare
);
parameter IDLE = 3'b000, WAIT_PASSWORD=3'b001, WRONG_PASS=3'b010, RIGH... | 7.282482 |
module cs42448 #(
parameter clk_freq = 12288
) (
input sys_clk,
input sys_nrst,
// ===================================
output CS42xx8_DAC_SDOUT0,
output CS42xx8_DAC_SDOUT1,
output CS42xx8_DAC_SDOUT2,
output CS42xx8_DAC_SDOUT3,
output CS42xx8_DAC_SCLK,
output CS42xx8_DAC_LRCK,
... | 7.427315 |
module cs42448_adc (
// 12MHz
input sys_clk,
input sys_nrst,
input init_done,
output [15 : 0] adc_dout_l0,
output [15 : 0] adc_dout_r0,
output [15 : 0] adc_dout_l1,
output [15 : 0] adc_dout_r1,
output [15 : 0] adc_dout_l2,
output [15 : 0] adc_dout_r2,
// Physical Layer - ... | 6.886874 |
module cs42448_dac (
input sys_clk,
input sys_nrst,
input init_done,
input [15 : 0] dac_din_l0,
input [15 : 0] dac_din_r0,
input [15 : 0] dac_din_l1,
input [15 : 0] dac_din_r1,
input [15 : 0] dac_din_l2,
input [15 : 0] dac_din_r2,
input [15 : 0] dac_din_l3,
input [15 : 0] ... | 6.601871 |
module nabs the serial data from the adcs and
// breaks it into 8-bit chunks for the ft245r. alignment
// is by constant size counted from a reset assertion.
module cs5361 (
adcval, // out: data to ft245r handler
adcstrobe,// out: strobe to ft245r handler
lrck, // in: left-right from adc
sclk, // in: shift cl... | 7.269896 |
module \$paramod\RCA\n=4 (
A,
B,
Ci,
Co,
S
);
input [3:0] A;
input [3:0] B;
input Ci;
output Co;
output [3:0] S;
wire [4:0] c;
FA \addbit[0].bit (
.a (A[0]),
.b (B[0]),
.ci(Ci),
.co(c[1]),
.s (S[0])
);
FA \addbit[1].bit (
.a (A[1]),
.b (B[1... | 7.791478 |
module CSA (
A,
B,
Ci,
Co,
S
);
input [15:0] A;
input [15:0] B;
wire [4:0] C;
input Ci;
output Co;
wire [1:0] Ctmp;
output [15:0] S;
wire [11:0] \Stmp[0] ;
wire [11:0] \Stmp[1] ;
\$paramod\RCA\n=4 \addbit.$genblock$n-bit%20CSA\CSA.v:25$33[4].bitA (
.A (A[7:4]),
.B (B[... | 7.379379 |
module CSA16 (
a,
b,
cin,
s,
cout
);
input [15:0] a, b;
input cin;
output [15:0] s;
output cout;
wire c;
wire [7:0] s0, s1;
CSA8 a1 (
a[7:0],
b[7:0],
cin,
s[7:0],
cs
);
CSA8 a2 (
a[15:8],
b[15:8],
0,
s0[7:0],
c0
);
... | 6.734468 |
module CSA16ins (
a,
b,
cin,
sum,
cout
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire [2:0] c;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c[0])
);
// first 4-bit by ripple_carry_adder
ca... | 7.549809 |
module carry_select_adder_4bit_slice (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] s0, s1;
wire c0, c1;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(1'b0),
.sum(s0[3:0]),
.cout(c0)
);
ripp... | 7.112285 |
module mux2X1 (
in0,
in1,
sel,
out
);
parameter width = 16;
input [width-1:0] in0, in1;
input sel;
output [width-1:0] out;
assign out = (sel) ? in1 : in0;
endmodule
| 7.13045 |
module ripple_carry_4_bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire c1, c2, c3;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1])... | 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor xor_1 (sum, a, b);
and and_1 (cout, a, b);
endmodule
| 6.966406 |
module: CSA16ins
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CSA16ins_tb;
// Inputs
reg [15:0] a;
reg [15:0] b;
reg cin;
// Outputs
wire [15:0] sum;
wire cout;
// Inst... | 7.701534 |
module CSelA32 (
output [31:0] sum,
output cout,
input [31:0] a,
b
);
wire [31:0] sum0, sum1;
wire [7:1] c;
wire [7:0] cout0, cout1;
RCA4 rca0_0 (
sum0[3:0],
cout0[0],
a[3:0],
b[3:0],
0
);
RCA4 rca0_1 (
sum1[3:0],
cout1[0],
a[3:0],
b[3:... | 6.935068 |
module CSA3_2_Array #(
parameter WIDTH = 24
) (
input wire [WIDTH - 1 : 0] In_1,
input wire [WIDTH - 1 : 0] In_2,
input wire [WIDTH - 1 : 0] In_3,
output wire [WIDTH - 1 : 0] S,
output wire [WIDTH - 1 : 0] C
);
//Conventional
// assign S = In_1 ^ In_2 ^ In_3;
// assign C = (In_1 & In_2... | 8.091286 |
module CSA4ins (
A,
B,
Cin,
S,
Cout
);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Cout;
wire [3:0] sum0, sum1, carry0, carry1;
FA fa00 (
A[0],
B[0],
1'b0,
sum0[0],
carry0[0]
);
FA fa01 (
A[1],
B[1],
carry0[0],
sum0[1],
... | 7.202408 |
module csa4_2 (
A,
B,
C,
D,
sum,
carry,
cout
);
input [47:0] A, B, C, D;
output [47:0] sum, carry;
output cout;
wire [47:0] sum_temp;
wire [47:0] carry_temp;
genvar i, j;
generate
for (i = 0; i < 48; i = i + 1) begin : loop1
FA fa1 (
A[i],
B[i],
... | 6.82294 |
module CSA8 (
a,
b,
cin,
s,
cout
);
input [7:0] a, b;
input cin;
output [7:0] s;
output cout;
wire c;
wire [3:0] s0, s1;
RCA a1 (
a[3:0],
b[3:0],
cin,
s[3:0],
cs
);
RCA a2 (
a[7:4],
b[7:4],
0,
s0[3:0],
c0
);
RCA a3 ... | 7.341238 |
module CSA8ins (
A,
B,
Cin,
S,
Cout
);
input [7:0] A, B;
input Cin;
output [7:0] S;
output Cout;
wire [3:0] sumL, sumU0, sumU1, sumU, al, ah, bl, bh;
wire cL, cU0, cU1;
assign al = A[3:0];
assign ah = A[7:4];
assign bl = B[3:0];
assign bh = B[7:4];
CSA4ins cas1 (
al,
... | 7.029511 |
module: CSA8ins
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CSA8ins_tb;
// Inputs
reg [7:0] A;
reg [7:0] B;
reg Cin;
// Outputs
wire [7:0] S;
wire Cout;
// Instantiate... | 6.820116 |
module to add 3 N bit numbers
module csa3_N_bit
#(parameter N = 16)
(
input [N-1:0] a,
input [N-1:0] b,
input [N-1:0] cin,
output [N:0] cout,
output [N:0] s
);
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin: my_block
assign s[i] = a[i]^b[i]... | 7.234688 |
module csa (
input a,
input b,
input cin,
output sum,
output cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.918042 |
module carry_look_ahead_20bit (
a,
b,
cin,
sum,
cout
);
input [19:0] a, b;
input cin;
output [19:0] sum;
output cout;
wire c1, c2, c3, c4;
carry_look_ahead_4bit cla1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c1)
);
carry_look_ahead_4bit... | 6.511278 |
module carry_look_ahead_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
assign p = a ^ b; //propagate
assign g = a & b; //generate
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1]... | 6.511278 |
module add4 (
a,
b,
cin,
cout,
S,
Gm,
Pm
);
input [3:0] a; // 设置4位二进制输入x,y
input [3:0] b;
input cin; //设置二进制输入进位c0
output cout, Gm, Pm; //设置二进制输出进位c4
output [3:0] S; //设置二进制输出4位数F
wire [3:0] c, p, g;
add1 m_add1_1 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.... | 7.334232 |
module add16 (
a,
b,
cin,
S,
Pm,
Gm
);
input [15:0] a, b;
input cin;
output Pm, Gm;
output [15:0] S;
wire c4, c8, c12;
wire [4:1] p, g;
add4 m_add4_1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.cout(),
.S(S[3:0]),
.Gm(g[1]),
.Pm(p[1])
);
ad... | 6.87555 |
module csadd32 (
a,
b,
cin,
sum,
cout
);
input [32:1] a;
input [32:1] b;
input cin;
output [33:1] sum;
output cout;
wire px1, gx1, px2, gx2; //设置中间操作变量
wire c16;
add16 m_add16_1 (
a[16:1],
b[16:1],
cin,
sum[16:1],
px1,
gx1
);
add16 m_add16_2... | 6.814584 |
module for implementing bank memories
// --------------------------------------------------------------------
// This module implements a dual-ported RAM.
// with clocked write and read operations.
module ram(clock, addrA, wEnA, wDatA, rEnA, rDatA,
addrB, wEnB, wDatB, rEnB, rDatB);
parameter wordsize = 8; // Number o... | 8.007955 |
module cenrreg
// Clocked register with enable signal and synchronous reset
// Default width is 8, but can be overriden
module cenrreg(out, in, enable, reset, resetval, clock);
parameter width = 8;
output [width-1:0] out;
reg [width-1:0] out;
input [width-1:0] in;
input enable;
input reset;
input [width-1:0] resetval;... | 7.794596 |
module preg(out, in, stall, bubble, bubbleval, clock);
parameter width = 8;
output [width-1:0] out;
input [width-1:0] in;
input stall, bubble;
input [width-1:0] bubbleval;
input clock;
cenrreg #(width) r(out, in, ˜stall, bubble, bubbleval, clock);
endmodule
| 7.240363 |
module split (
ibyte,
icode,
ifun
);
input [7:0] ibyte;
output [3:0] icode;
output [3:0] ifun;
assign icode = ibyte[7:4];
assign ifun = ibyte[3:0];
endmodule
| 6.814667 |
module align (
ibytes,
need_regids,
rA,
rB,
valC
);
input [71:0] ibytes;
input need_regids;
output [3:0] rA;
output [3:0] rB;
output [63:0] valC;
assign rA = ibytes[7:4];
assign rB = ibytes[3:0];
assign valC = need_regids ? ibytes[71:8] : ibytes[63:0];
endmodule
| 7.456157 |
module pc_increment (
pc,
need_regids,
need_valC,
valP
);
input [63:0] pc;
input need_regids;
input need_valC;
output [63:0] valP;
assign valP = pc + 1 + 8 * need_valC + need_regids;
endmodule
| 6.514013 |
module alu(aluA, aluB, alufun, valE, new_cc);
input [63:0] aluA, aluB; // Data inputs
input [ 3:0] alufun; // ALU function
output [63:0] valE; // Data Output
output [ 2:0] new_cc; // New values for ZF, SF, OF
parameter ALUADD = 4’h0;
parameter ALUSUB = 4’h1;
parameter ALUAND = 4’h2;
parameter ALUXOR = 4’h3;
assign va... | 8.650555 |
module cond(ifun, cc, Cnd);
input [3:0] ifun;
input [2:0] cc;
output Cnd;
wire zf = cc[2];
wire sf = cc[1];
wire of = cc[0];
// Jump & move conditions.
parameter C_YES = 4’h0;
parameter C_LE = 4’h1;
parameter C_L = 4’h2;
parameter C_E = 4’h3;
parameter C_NE = 4’h4;
parameter C_GE = 4’h5;
parameter C_G = 4’h6;
assign... | 8.45792 |
module full_add (
input x,
y,
cin,
output s,
cout
);
assign s = x ^ y ^ cin;
assign cout = (x & y) | (x & cin) | (y & cin);
endmodule
| 7.176667 |
module csa_16 (
input [15:0] x,
y,
z,
output [15:0] s,
c
);
genvar i;
for (i = 0; i < 16; i = i + 1) begin
full_add full_add_i (
.x (x[i]),
.y (y[i]),
.cin (z[i]),
.s (s[i]),
.cout(c[i])
);
end
endmodule
| 7.237188 |
module csa_16bit (
s,
c,
x,
y,
z
);
output [15:0] s, c;
input [15:0] x, y, z;
full_adder_norm fan0 (
.sum(s[0]),
.cout(c[0]),
.a(x[0]),
.b(y[0]),
.cin(z[0])
);
full_adder_norm fan1 (
.sum(s[1]),
.cout(c[1]),
.a(x[1]),
.b(y[1]),
.c... | 6.601712 |
module tb_csa_16bit ();
reg [15:0] x, y, z;
wire [15:0] s, c;
csa_16bit uut (
.s(s),
.c(c),
.x(x),
.y(y),
.z(z)
);
initial begin
#00 x = 16'd10;
y = 16'd10;
z = 16'd12345; //10-2
#20 x = 16'd30;
y = 16'd20;
z = 16'd20123;
#20 x = 16'd150;
y = 16'... | 6.540425 |
module tb_csa_16bit ();
reg [15:0] x, y, z;
wire [15:0] s, c;
csa_16bit uut (
.s(s),
.c(c),
.x(x),
.y(y),
.z(z)
);
initial begin
#00 x = 16'd10;
y = 16'd10;
z = 16'd12345; //10-2
#20 x = 16'd30;
y = 16'd20;
z = 16'd20123;
#20 x = 16'd150;
y = 16'... | 6.540425 |
module CSA_3 (
input a,
input b,
input c,
output s,
output co
);
wire s1;
xor M1 (s1, a, b);
xor M2 (s, s1, c);
assign co = (a & b) | (b & c) | (c & a);
endmodule
| 8.051843 |
module csa_32 (
a,
b,
in,
sum,
overflow
);
//this module will help us to build a 32 bits csa adder
input [31:0] a, b;
input in;
output [31:0] sum;
output overflow;
//firstly: calculate the lower 16 bits using RCA
wire low_16_carry_out;
//wire low_16_overflow;
rca_16 low_16 (
... | 7.076247 |
module csa_32x3 (
input wire [31:0] in1,
input wire [31:0] in2,
input wire [31:0] in3,
output wire [31:0] sum,
output wire [31:0] carry
);
assign sum = in1 ^ in2 ^ in3;
assign carry = in1 & in2 | in1 & in3 | in2 & in3;
endmodule
| 7.238868 |
module csa_32x4 (
input wire [31:0] in1,
input wire [31:0] in2,
input wire [31:0] in3,
input wire [31:0] in4,
output wire [31:0] sum,
output wire [31:0] carry
);
wire [31:0] sum1;
wire [31:0] carry1;
csa_32x3 csa_32x3_1 (
.in1 (in1),
.in2 (in2),
.in3 (in3),
... | 7.079131 |
module CSA_4 (
a,
b,
cin,
cout,
sum
);
input [3:0] a, b;
input cin;
output cout;
output [3:0] sum;
wire [1:0] out1, out2;
wire w1, w2, w3;
RCA_2 RCA_2_1 (
a[1:0],
b[1:0],
cin,
w1,
sum[1:0]
);
RCA_2 RCA_2_2 (
a[3:2],
b[3:2],
1'b0,
... | 7.37909 |
module CSA_48 (
x,
y,
z,
s,
c
);
input [47:0] x, y, z;
output [47:0] s, c;
assign s = x ^ y ^ z;
assign c = {x[46:0] & y[46:0] | z[46:0] & y[46:0] | z[46:0] & x[46:0], 1'b0};
endmodule
| 7.579174 |
module fa_df (
input a,
b,
cin,
output sum,
cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 6.889194 |
module CSA_64 (
x,
y,
z,
s,
c
);
input [63:0] x, y, z;
output [63:0] s, c;
assign s = x ^ y ^ z;
assign c = {x[62:0] & y[62:0] | z[62:0] & y[62:0] | z[62:0] & x[62:0], 1'b0};
endmodule
| 7.229975 |
module half_adder (
a,
b,
sum_ha,
cout_ha
);
input a, b;
output sum_ha, cout_ha;
assign sum_ha = a ^ b;
assign cout_ha = a & b;
endmodule
| 6.966406 |
module mux_8 (
s0,
s1,
c0,
c1,
sel,
sum_8,
cout_8
);
input [7:0] s0, s1;
input c0, c1, sel;
output [7:0] sum_8;
output cout_8;
assign sum_8 = sel ? s1 : s0;
assign cout_8 = sel ? c1 : c0;
endmodule
| 7.066521 |
module mux_16_tier1 (
b_s_0,
b_s_1,
a_s_0,
a_s_1,
b_c_0,
b_c_1,
a_c_0,
a_c_1,
o_s_0,
o_s_1,
o_c_0,
o_c_1
);
input [7:0] b_s_0, b_s_1, a_s_0, a_s_1;
input a_c_0, a_c_1, b_c_0, b_c_1;
output [15:0] o_s_0, o_s_1;
output o_c_0, o_c_1;
assign o_s_0 = a_c_0 ? {b_s_1,... | 6.745859 |
module mux_16_tier2 (
o_s_0,
o_s_1,
o_c_0,
o_c_1,
cin,
e_s,
e_c
);
input [15:0] o_s_0, o_s_1;
input o_c_0, o_c_1, cin;
output [15:0] e_s;
output e_c;
assign e_s = cin ? o_s_1 : o_s_0;
assign e_c = cin ? o_c_1 : o_c_0;
endmodule
| 6.934693 |
module mux_32_tier2 (
b_s_0,
b_s_1,
a_s_0,
a_s_1,
b_c_0,
b_c_1,
a_c_0,
a_c_1,
o_s_0,
o_s_1,
o_c_0,
o_c_1
);
input [15:0] b_s_0, b_s_1, a_s_0, a_s_1;
input a_c_0, a_c_1, b_c_0, b_c_1;
output [31:0] o_s_0, o_s_1;
output o_c_0, o_c_1;
assign o_s_0 = a_c_0 ? {b_s_1... | 7.008272 |
module mux_32_tier3 (
o_s_0,
o_s_1,
o_c_0,
o_c_1,
cin,
e_s,
e_c
);
input [31:0] o_s_0, o_s_1;
input o_c_0, o_c_1, cin;
output [31:0] e_s;
output e_c;
assign e_s = cin ? o_s_1 : o_s_0;
assign e_c = cin ? o_c_1 : o_c_0;
endmodule
| 7.138036 |
module CSA_8 (
a,
b,
cin,
cout,
sum
);
input [7:0] a, b;
input cin;
output cout;
output [7:0] sum;
wire [3:0] out1, out2;
wire w1, w2, w3;
CSA_4 CSA_4_1 (
a[3:0],
b[3:0],
cin,
w1,
sum[3:0]
);
CSA_4 CSA_4_2 (
a[7:4],
b[7:4],
1'b0,
... | 6.653795 |
module mux2X1 (
in0,
in1,
sel,
out
);
input wire in0, in1, sel;
output wire out;
wire net0, net1, selnot;
not (selnot, sel);
and (net0, in0, selnot);
and (net1, in1, sel);
or (out, net0, net1);
endmodule
| 7.13045 |
module mux2X2 (
in0,
in1,
sel,
out
);
input wire [1:0] in0, in1;
input wire sel;
output wire [1:0] out;
wire net00, net10, selnot0, net01, net11, selnot1;
mux2X1 entity_5 (
in0[0],
in1[0],
sel,
out[0]
);
mux2X1 entity_6 (
in0[1],
in1[1],
sel,
... | 7.362079 |
module mux2X4 (
in0,
in1,
sel,
out
);
input wire [3:0] in0, in1;
input wire sel;
output wire [3:0] out;
mux2X2 entity_7 (
in0[1:0],
in1[1:0],
sel,
out[1:0]
);
mux2X2 entity_8 (
in0[3:2],
in1[3:2],
sel,
out[3:2]
);
endmodule
| 6.670839 |
module mux2X16 (
in0,
in1,
sel,
out
);
input wire [15:0] in0, in1;
input wire sel;
output wire [15:0] out;
mux2X8 entity_11 (
in0[7:0],
in1[7:0],
sel,
out[7:0]
);
mux2X8 entity_12 (
in0[15:8],
in1[15:8],
sel,
out[15:8]
);
endmodule
| 7.647156 |
module mux2X32 (
in0,
in1,
sel,
out
);
input wire [31:0] in0, in1;
input wire sel;
output wire [31:0] out;
mux2X16 entity_13 (
in0[15:0],
in1[15:0],
sel,
out[15:0]
);
mux2X16 entity_14 (
in0[31:16],
in1[31:16],
sel,
out[31:16]
);
endmodule
| 8.122258 |
module CSA_8BITS (
a,
b,
c_in,
sum,
c_out
);
input wire [7:0] a, b;
input wire c_in;
output wire [7:0] sum;
output wire c_out;
wire [3:0] s0, s1;
wire c0, c1, c2;
CSA_4BITS entity_23 (
a[3:0],
b[3:0],
c_in,
sum[3:0],
c0
);
CSA_4BITS entity_24 (
... | 6.606604 |
module mux2X64 (
in0,
in1,
sel,
out
);
input wire [63:0] in0, in1;
input wire sel;
output wire [63:0] out;
mux2X32 entity_38 (
in0[31:0],
in1[31:0],
sel,
out[31:0]
);
mux2X32 entity_39 (
in0[63:32],
in1[63:32],
sel,
out[63:32]
);
endmodule
| 7.219521 |
module csa_adder_3i_32b (
input [31:0] A,
input [31:0] B,
input [31:0] C,
output [31:0] R
);
wire [31:0] S;
wire [31:0] Ca;
wire [33:0] R_tmp;
//3-2 CSA
assign S = A ^ B ^ C;
assign Ca = (A & B) | (A & C) | (B & C);
//加法器
assign R_tmp = {Ca, {1'b0}} + S;
//输出端口,取低位，不考虑进位
assig... | 7.533174 |
module csa_adder_8bit (
input [7:0] A,
input [7:0] B,
input wire [4:0] cin,
output wire cout,
output [7:0] sum
);
//output wire cin_last
wire [3:0] c0;
wire [3:0] c1;
wire [3:0] s0;
wire [3:0] s1;
wire [3:0] cout_low;
//wire cin;
//assign cin = 0;
//lower 4-bit RCA adder
full_a... | 6.768228 |
module CSA_carry (
input enable,
input clk,
input [79:0] frac_even,
input [79:0] frac_odd,
output [1:0] adr_even,
output [1:0] adr_odd,
output [2:0] blk,
output [127:0] frac_out,
output clr_odd,
output sign,
output finish
);
reg [15:0] carry;
reg sign_1;
reg [63:0] f... | 7.081491 |
module CSA_Cell (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule... | 7.1219 |
module csa_dadda (
A,
B,
Cin,
Y,
Cout
);
input A, B, Cin;
output Y, Cout;
assign Y = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);
endmodule
| 7.659322 |
module csa_eight #(
parameter SIZE = 8,
APPROX_BITS = 0
) (
input signed [SIZE-1:0] a,
b,
c,
d,
e,
f,
g,
h,
input signed [SIZE-1:0] constant,
input approx_en,
output logic signed [SIZE+4:0] sum
);
logic signed [SIZE-1:0] c1, s1, c2, s2, c3, s3;
logic signed [SIZ... | 7.191196 |
module dut;
parameter SIZE = 8, APPROXI_BITS = 0;
logic signed [SIZE-1:0] a, b, c, d, e, f, g, h, constant, b_inv, f_inv;
logic signed approx_en;
logic signed [SIZE-1:0] a_i, b_i, c_i, d_i, e_i, f_i, g_i, h_i;
logic signed [SIZE+4:0] sum;
assign a_i = (a > 0) ? a : ~a;
assign b_i = (b > 0) ? b : ~b;
... | 7.185605 |
module Carry_skip_group_PG #(
parameter WIDTH = 16,
VALENCY = 2,
GROUP = 4
) (
input [WIDTH:0] G,
input [WIDTH:0] P,
output [WIDTH:0] Gi
);
wire [WIDTH:1] t;
wire [WIDTH:0] muxout;
assign Gi[0] = G[0];
assign muxout[0] = G[0];
genvar i, j;
generate
for (i = 2; i <= WIDTH - 2;... | 7.268229 |
module rca #(
parameter n = 32
) (
input [n-1:0] a,
b,
input ci,
output [n-1:0] s,
output co
);
wire [n:0] c;
assign c[0] = ci;
assign co = c[n];
generate
genvar i;
for (i = 0; i < n; i = i + 1)
`FA_CELL FA (
.COUT(c[i+1]),
.CIN(c[i]),
.A(a[i... | 7.699599 |
module csa8_4 (
input [7:0] a,
b,
input ci,
output [7:0] s,
output co
);
wire co0, co10, co11;
wire [3:0] s10, s11;
rca #(4) A0 (
.a (a[3:0]),
.b (b[3:0]),
.ci(ci),
.co(co0),
.s (s[3:0])
);
rca #(4) A10 (
.a (a[7:4]),
.b (b[7:4]),
.ci(... | 7.815626 |
module csa16_8 (
input [15:0] a,
b,
input ci,
output [15:0] s,
output co
);
wire co0, co10, co11;
wire [7:0] s10, s11;
rca #(8) A0 (
.a (a[7:0]),
.b (b[7:0]),
.ci(ci),
.co(co0),
.s (s[7:0])
);
rca #(8) A10 (
.a (a[15:8]),
.b (b[15:8]),
... | 7.20651 |
module csa32_8x4 (
input [31:0] a,
b,
input ci,
output [31:0] s,
output co
);
wire co0, co1, co2, co3;
wire [3:1] c0, c1;
wire [7:0] s0[3:1], s1[3:1];
wire lo, hi;
`TIE_CELL TIE (
.LO(lo),
.HI(hi)
);
csa8_4 A0 (
.a (a[7:0]),
.b (b[7:0]),
.ci(ci),
... | 6.93454 |
module csa32_16 (
input [31:0] a,
b,
input ci,
output [31:0] s,
output co
);
wire co0, co10, co11;
wire [15:0] s10, s11;
rca #(16) A0 (
.a (a[15:0]),
.b (b[15:0]),
.ci(ci),
.co(co0),
.s (s[15:0])
);
rca #(16) A10 (
.a (a[31:16]),
.b (b[31:16... | 6.973822 |
module sky130_csa (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
(* forc... | 7.364571 |
module sky130_csa_sub (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
(* ... | 7.578394 |
module csa_n (
a,
b,
ci,
s,
co
);
parameter n = 16; // Default
parameter k = 8;
parameter blockType = 0; // 0 if RCA, 1 if CLA
input [n-1:0] a, b;
input ci;
output [n-1:0] s;
output co;
wire c[n/k-1:0];
assign co = c[n/k-1];
wire [ n-1:k] s_0;
wire [ n-1:k] s_1;
wire [n/k... | 7.981653 |
module CSA_top (
a,
b,
c,
d,
cin1,
cin2,
Ws,
Wc
);
parameter Stage = 6;
localparam WL = Stage;
input [WL-1:0] a, d;
input [WL-1:1] b, c;
input cin1, cin2;
output [WL-1:0] Ws, Wc;
wire [WL-1:0] temp_Ws;
wire [WL:1] temp_Wc;
//wire [WL-1:1] temp_Wc;
wire [Stage-1:0] ... | 6.927876 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module csea16 (
Sum,
Cout,
A,
B,
Cin
);
input [15:0] A, B;
input Cin;
output [15:0] Sum;
output Cout;
wire [3:0] Sum0_0, Sum0_1, Sum1_0, Sum1_1, Sum2_0, Sum2_1;
rca4 rca1 (
Sum[3:0],
c4,
A[3:0],
B[3:0],
Cin
);
rca4 rca2 (
Sum0_0,
g4,
... | 7.043589 |
module degree0_cell (
in,
out,
clock,
load,
compute
);
input [4:0] in;
output [4:0] out;
input clock, compute, load;
wire [4:0] outmux, outreg;
register5_wl register (
outmux,
outreg,
clock,
load
);
mux2_to_1 multiplex (
in,
outreg,
outmux,
... | 6.616922 |
module degree1_cell (
in,
out,
clock,
load,
compute
);
input [4:0] in;
output [4:0] out;
input clock, load, compute;
wire [4:0] outmux;
wire [0:4] outmult, outreg;
register5_wl register (
outmux,
outreg,
clock,
load
);
mux2_to_1 multiplexer (
in,
... | 6.518041 |
module degree2_cell (
in,
out,
clock,
load,
compute
);
input [4:0] in;
output [4:0] out;
input clock, load, compute;
wire [4:0] outmux;
wire [0:4] outmult, outreg;
register5_wl register (
outmux,
outreg,
clock,
load
);
mux2_to_1 multiplexer (
in,
... | 7.009564 |
module degree3_cell (
in,
out,
clock,
load,
compute
);
input [4:0] in;
output [4:0] out;
input clock, load, compute;
wire [4:0] outmux;
wire [0:4] outmult, outreg;
register5_wl register (
outmux,
outreg,
clock,
load
);
mux2_to_1 multiplexer (
in,
... | 6.625559 |
module degree4_cell (
in,
out,
clock,
load,
compute
);
input [4:0] in;
output [4:0] out;
input clock, load, compute;
wire [4:0] outmux;
wire [0:4] outmult, outreg;
register5_wl register (
outmux,
outreg,
clock,
load
);
mux2_to_1 multiplexer (
in,
... | 6.597769 |
module degree6_cell (
in,
out,
clock,
load,
compute
);
input [4:0] in;
output [4:0] out;
input clock, load, compute;
wire [4:0] outmux;
wire [0:4] outmult, outreg;
register5_wl register (
outmux,
outreg,
clock,
load
);
mux2_to_1 multiplexer (
in,
... | 6.504917 |
module fulladder (
input a,
b,
cin,
output sum,
carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (cin & b) | (a & cin);
endmodule
| 7.454465 |
module multiplexer2 (
input i0,
i1,
sel,
output bitout
);
assign bitout = sel == 0 ? i0 : i1;
endmodule
| 7.52838 |
module carry_select_adder (
input [31:0] A,
B,
input cin,
output [31:0] S,
output cout,
output overflow
);
wire [31:0] temp0, temp1, carry0, carry1;
//for carry 0
fulladder fa00 (
A[0],
B[0],
1'b0,
temp0[0],
carry0[0]
);
fulladder fa01 (
A[0],
... | 7.112285 |
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