code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module csirx_tb #(
parameter integer N_DATA_LANES = 2
) ();
reg clk;
reg resetn;
// PPI input simulating Xilinx D-PHY core
reg cl_stopstate;
reg dl0_rxactivehs; // Whether high-speed receive is in progress
reg dl1_rxactivehs;
reg dl0_rxsynchs; // Pulse at the beginning of high-speed transmission
... | 7.02438 |
module csi_dphy_ipgen_lscc_clock_divider #(
parameter integer TGT_FREQ_IN = 100
) (
// -----------------------------------------------------------------------------
// Module Parameters
// -----------------------------------------------------------------------------
// target frequency in 24 - 200 M... | 7.547972 |
module CSI_parameter (
A1,
A2,
A3,
K,
P1,
P2,
P3,
B,
C,
D
);
//ģӿ
input A1, A2, A3, K, P1, P2, P3;
output B, C, D;
wire signed [19:0] A1, A2, A3, K, P1, P2, P3;
wire signed [19:0] B, C, D;
//ڲ
wire [19:0] H;
/*
//CSIֵ
C=K;
B=(A3-A2)/(P3-P2)-(P3-P2)*(2*K)/3;
D=(-... | 8.270565 |
module csi_rx_hdr_ecc (
data,
ecc
);
input [23:0] data;
output [7:0] ecc;
assign ecc[7] = 1'b0;
assign ecc[6] = 1'b0;
assign ecc[5] = data[10] ^ data[11] ^ data[12] ^ data[13] ^ data[14] ^ data[15] ^ data[16] ^ data[17] ^ data[18] ^ data[19] ^ data[21] ^ data[22] ^ data[23];
assign ecc[4] = data[4... | 6.929915 |
module csi_rx_header_ecc (
input [23:0] DIN,
output [ 7:0] ECC
);
assign ECC[7] = 0;
assign ECC[6] = 0;
assign ECC[5] = DIN[10] ^ DIN[11] ^ DIN[12] ^ DIN[13] ^ DIN[14] ^ DIN[15] ^ DIN[16] ^ DIN[17] ^ DIN[18] ^ DIN[19] ^ DIN[21] ^ DIN[22] ^ DIN[23];
assign ECC[4] = DIN[4] ^ DIN[5] ^ DIN[6] ^ DIN[7] ... | 6.678739 |
module csi_rx_ice40 #(
parameter LANES = 2, // lane count
parameter PAIRSWAP = 2'b10, // lane pair swap (inverts data for given lane)
parameter [1:0] VC = 2'b00, // MIPI CSI-2 "virtual channel"
parameter [5:0] FS_DT = 6'h00, // Frame start data type
parameter [5:0] FE_DT = 6'h01, // Frame end... | 7.525418 |
module cska16 (
Sum,
Cout,
A,
B,
Cin
);
input [15:0] A, B;
input Cin;
output [15:0] Sum;
output Cout;
wire [3:0] p1, p2;
rca4 cpa1 (
Sum[3:0],
c4,
A[3:0],
B[3:0],
Cin
);
rca4p cpa2 (
Sum[7:4],
w1,
p1,
A[7:4],
B[7:4],
... | 7.251892 |
module CSKA32Bit (
input [31:0] A,
input [31:0] B,
input Cin,
output [31:0] S,
output Cout
);
wire [8:0] carry_prop;
assign carry_prop[0] = Cin;
wire [3:0] ABUS0 = A[3:0];
wire [3:0] ABUS1 = A[7:4];
wire [3:0] ABUS2 = A[11:8];
wire [3:0] ABUS3 = A[15:12];
wire [3:0] ABUS4 = A[19:16];... | 6.625452 |
module: CSKA32Bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CSKA32Bit_tb;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg Cin;
// Outputs
wire [31:0] S;
wire Cout;
// Inst... | 7.260176 |
module CSKA4Bit (
input [3:0] A,
input [3:0] B,
input Cin,
output Cout,
output [3:0] S
);
wire [4:0] carry_prop;
wire [3:0] P;
assign carry_prop[0] = Cin;
FullAdder_P FullAdder_P0 (
A[0],
B[0],
carry_prop[0],
S[0],
P[0],
carry_prop[1]
);
FullAdder_P ... | 6.511413 |
module: CSKA4Bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CSKA4Bit_tb;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;
// Outputs
wire Cout;
wire [3:0] S;
// Instantia... | 6.739993 |
module CSkipA_16b_tb ();
wire [16:0] out0;
reg [15:0] in0;
reg [15:0] in1;
integer i, file, mem, temp;
CSkipA_16b U0 (
in0,
in1,
out0
);
initial begin
$display("-- Begining Simulation --");
$dumpfile("./CSkipA_16b.vcd");
$dumpvars(0, CSkipA_16b_tb);
file = $fopen("... | 6.52745 |
module csla (
x,
y,
s,
cout
);
output [31:0] s;
input [31:0] x, y;
output cout;
wire [4:0] sel;
wire [3:0] sum0;
wire [4:0] temp0, temp0_1;
wire [4:0] sum1;
wire [5:0] temp1, temp1_1;
wire [5:0] sum2;
wire [6:0] temp2, temp2_1;
wire [6:0] sum3;
wire [7:0] temp3, temp3_1;
wire... | 7.027024 |
module CSLA32Bit (
input [31:0] A,
input [31:0] B,
input Cin,
output [31:0] S,
output Cout
);
wire [8:0] carry_prop;
assign carry_prop[0] = Cin;
wire [3:0] ABUS0 = A[3:0];
wire [3:0] ABUS1 = A[7:4];
wire [3:0] ABUS2 = A[11:8];
wire [3:0] ABUS3 = A[15:12];
wire [3:0] ABUS4 = A[19:16];... | 6.578691 |
module: CSLA32Bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CSLA32Bit_tb;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg Cin;
// Outputs
wire [31:0] S;
wire Cout;
// Inst... | 7.028743 |
module bitNRCAdder #(
parameter N = 4
) (
input wire [N-1:0] add1, //adder1
input wire [N-1:0] add2, //adder2
input wire cin, //carry input
output wire [N-1:0] result, //sum
output wire cout //carry output
);
wire [N-1:0] p, g; //internal variables
wire [N:0] c_m... | 7.708111 |
module bitNmux #(
parameter N = 5
) (
input wire [N:0] in1,
in0, // 2-way inputs
input wire sel, // select
output reg [N:0] ou1 //outputs
);
always @(*) begin
case (sel)
1'b0: ou1 = in0;
1'b1: ou1 = in1;
endcase
end
endmodule
| 7.258402 |
module bit1adder (
input wire g, // generate
input wire p, // propagate
input wire cin, // carry in
output wire sum, // sum
output wire count // carry out
);
assign sum = p ^ cin;
assign count = g | (cin & p);
endmodule
| 7.611102 |
module csm51a_proj1 (
input x0,
input x1,
input x2,
output z
);
// Outputs from NOT and AND gates
wire x0_not, x1_not, x2_not, prod1, prod2;
// NOT inputs
not n1 (x0_not, x0);
not n2 (x1_not, x1);
not n3 (x2_not, x2);
// Calculate Products
// prod1 = x2'x1'x0
and a1 (prod1, x2... | 6.966528 |
module CSMC (
x,
y,
b,
bo,
d
);
// u = 0
input x, y, b;
output bo, d;
wire xNot, yNot, bNot;
assign xNot = ~x;
assign yNot = ~y;
assign bNot = ~b;
assign bo = (xNot & (y | b)) | (y & b);
assign d = x ^ (y ^ b);
endmodule
| 7.24668 |
module csm_tb (
output [31:0] product,
output reg [31:0] ref,
output done
);
reg clk;
reg reset;
reg [15:0] mer;
reg [15:0] mand;
reg go;
initial
clk <= 0;
always @ (clk)
clk <= #10 ~clk;
initial begin
reset <= 1;
go <= 0;
@(negedge clk);
mer <= 16'b1111111111111111;
mand <= 16'b0000000001010101;
@(negedge... | 7.229946 |
module csrAddrex (
input wire clk,
bubbleM,
flushM,
input wire [11:0] csrAex,
output reg [11:0] csrAmem
);
initial csrAmem = 0;
always @(posedge clk)
if (!bubbleM) begin
if (flushM) csrAmem <= 0;
else csrAmem <= csrAex;
end
endmodule
| 7.310963 |
module csrAddrid (
input wire clk,
bubbleE,
flushE,
input wire [11:0] csrAid,
output reg [11:0] csrAex
);
initial csrAex = 0;
always @(posedge clk)
if (!bubbleE) begin
if (flushE) csrAex <= 0;
else csrAex <= csrAid;
end
endmodule
| 7.16843 |
module for csr
//
//////////////////////////////////////////////////////////////////////////////////
// 功能说明
// 算数运算和?辑运算功能部件
// 输入
// op1 第一个操作数, rs1的??:写入CSR的??/说明CSR哪些位被置位
// op2 第二个操作数, csr?
// op3 第三个操?, 5位的rs1位置对应的??
// csrALU_func 运算类型
//... | 9.063363 |
module is running on -- referred to within as tclk ("target
* clock").
*
* No guarantees are required about the phase relationship of the two
* clocks. It is required that the cclk domain's clock has little enough
* skew internally that the data flip-flops will all transition within one
* cycle of tclk; if stra... | 7.699795 |
module is running on -- referred to within as tclk ("target
* clock").
*
* No guarantees are required about the phase relationship of the two
* clocks. It is required that the cclk domain's clock has little enough
* skew internally that the data flip-flops will all transition within one
* cycle of tclk; if stra... | 7.699795 |
module csrbrg (
input sys_clk,
input sys_rst,
/* WB */
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
/* CSR */
output reg [13:0] csr_a,
output reg csr_we,
output reg ... | 8.110753 |
module csrDex (
input wire clk,
bubbleM,
flushM,
input wire [31:0] csrALU_out,
output reg [31:0] csrRegmem2
);
initial csrRegmem2 = 0;
always @(posedge clk)
if (!bubbleM) begin
if (flushM) csrRegmem2 <= 0;
else csrRegmem2 <= csrALU_out;
end
endmodule
| 7.221123 |
module csrDid (
input wire clk,
bubbleE,
flushE,
input wire [31:0] csrRegid,
output reg [31:0] csrRegex
);
initial csrRegex = 0;
always @(posedge clk)
if (!bubbleE) begin
if (flushE) csrRegex <= 0;
else csrRegex <= csrRegid;
end
endmodule
| 6.565388 |
module csrex (
input wire clk,
bubbleM,
flushM,
input wire [31:0] csrRegex,
output reg [31:0] csrRegmem1
);
initial csrRegmem1 = 0;
always @(posedge clk)
if (!bubbleM) begin
if (flushM) csrRegmem1 <= 0;
else csrRegmem1 <= csrRegex;
end
endmodule
| 7.341787 |
module csrFwdUnit (
csrAddr_EX,
csrAddr_WB,
fwdCSR
);
input [11:0] csrAddr_EX;
input [11:0] csrAddr_WB;
output reg fwdCSR;
always @(*) begin
if ((csrAddr_EX == csrAddr_WB) && (csrAddr_EX != 12'hb00) && (csrAddr_EX != 12'hb01) && (csrAddr_EX != 12'hb02))
fwdCSR = 1'b1;
else fwdCSR = 1'... | 7.265294 |
module CSRRegisterFile (
input wire clk,
input wire rst,
input wire write_en,
input wire [11:0] addr,
wb_addr,
input wire [31:0] wb_data,
output wire [31:0] csrreg
);
reg [31:0] csr_reg_file[4095:0];
integer i;
// init register file
initial begin
for (i = 0; i < 4096; i = i + 1... | 7.055336 |
module CSRRegs (
input clk,
rst,
input [11:0] raddr,
waddr,
input [31:0] wdata,
input csr_w,
input [1:0] csr_wsc_mode,
output [31:0] rdata,
output [31:0] mstatus,
input is_trap,
input is_mret,
input [31:0] mepc,
input [31:0] mcause,
input [31:0] mtval,
output... | 7.15173 |
module csru (
input [ 5:0] csr_inst_info,
input [ `ZCRV_XLEN-1:0] dest_csr_data, //目标csr的数值
input [ `ZCRV_XLEN-1:0] rs1_csr,
input [`ZCRV_IMM_SIZE-1:0] uimm_csr,
input need_csr,
//input imm_en,
input [`ZCRV_CSRADDR_SIZE-1:0] op_csr_addr,
i... | 6.867347 |
module csr_except (
input wire clk,
input wire [`ADDR_SIZE : 0] PC,
input wire [`INSTR_SIZE : 0] instr,
input wire exception_valid,
input wire [`EX_WIDTH : 0] exception,
input wire [`REG_DATA_SIZE : 0] wr_data,
output wire [`REG_ADDR_SIZE : 0] rd_addr,
output reg [`REG_DATA_SIZE : 0] rd... | 7.628567 |
module csr_issue #(
parameter DW = `CSR_ISSUE_INFO_DW,
parameter EXE_DW = `CSR_EXEPARAM_DW
) (
//from fifo
output csr_fifo_pop,
input csr_fifo_empty,
input [DW-1:0] csr_issue_info,
output csr_exeparam_valid_qout,
output [EXE_DW-1 : 0] csr_exeparam_qout,
//from regFile
input [3... | 7.034869 |
module csr_logic (
// These ports are not in any interface
input data_gnt_i,
input data_req_i,
input data_we_i,
output mem_load,
output mem_store
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
assign mem_load = data_req_i & data_gnt_i & (~data_we_i);
... | 6.55432 |
module csr_mux (
// These ports are not in any interface
input [31:0] alu_operand_a_ex,
input [11:0] alu_operand_b_ex,
input csr_access_ex,
input [ 1:0] csr_op_ex,
input [11:0] dbg_csr_addr,
input dbg_csr_req,
input [31:0] dbg_csr_wdata,
input dbg_csr_we,... | 7.524464 |
module csr_reg (
input wire clk,
input wire rst,
input wire [6:0] csr_write_en,
output reg [`RegBus] mtvec_data_o,
output reg [`RegBus] mscratch_data_o,
output reg [`RegBus] mepc_data_o,
output reg [`RegBus] mcause_data_o,
output reg [`RegBus] mstatus_data_o,
output reg [`RegBus] s... | 6.949251 |
module CSR_Regfile (
input wire clk,
input wire rst,
input wire CSR_write_en,
input wire [11:0] CSR_write_addr,
input wire [11:0] CSR_read_addr,
input wire [31:0] CSR_data_write,
output wire [31:0] CSR_data_read
);
// TODO: Complete this module
/* FIXME: Write your code here... */
pa... | 6.562442 |
module csr_satp (
input wire clk,
input wire rst,
input wire srw_satp_sel,
input wire [63:0] data_csr,
input wire csr_write,
output wire [63:0] satp
);
reg [ 3:0] mode;
reg [43:0] ppn;
always @(posedge clk) begin
if (rst) begin
mode <= 4'b0;
ppn <= 44'b0;
end else... | 7.464276 |
module csr_sram (
input sys_clk,
// CSR slave interface
input [17:1] csr_adr_i,
input [ 1:0] csr_sel_i,
input csr_we_i,
input [15:0] csr_dat_i,
output reg [15:0] csr_dat_o,
// Pad signals
output [19:0] sram_addr_,
inout [15:0] sram_data_,
... | 6.796951 |
module cstageg #(
parameter shift = 1,
parameter zwidth = 16,
parameter width = 16,
parameter def_op = 0
) (
input clk,
input [1:0] opin,
input [width-1:0] xin,
input [width-1:0] yin,
input [zwidth-1:0] zin,
input [zwidth-1:0] ain,
output reg [1:0] opout,
output reg [wi... | 8.472991 |
module CST_MS_LPDZ (
out_a
);
output [1:0] out_a;
wire [1:0] wire_a = 1'b0;
assign out_a = wire_a;
endmodule
| 7.015889 |
module csum (
input wire clk,
input wire rst,
input wire fifo_empty,
output reg reads_en,
input wire [ 7:0] kernel_size,
input wire [15:0] data,
input wire data_ready,
output reg data_valid,
output reg [15:0] csum_result,
output ... | 8.866116 |
module CS_Adder (
A,
B,
Out,
Cout,
overflow
);
parameter width = 32;
input [width-1:0] A;
input [width-1:0] B;
output [width-1:0] Out;
output [0:0] Cout;
output [0:0] overflow;
wire [width-1:1] carry;
wire c1;
fulladderDelay ADD1[width-1:0] (
.A(A),
.B(B),
.... | 7.772035 |
module cs_gen (
input wire [29:0] bus_addr,
output wire cs
);
parameter address = 32'h00000000;
parameter size = 32'h00001000;
localparam cs_mask_bits = 32 - $clog2(size);
localparam cs_mask = {{cs_mask_bits{1'b1}}, {32 - cs_mask_bits - 2{1'b0}}};
assign cs = (bus_addr & cs_mask) == address[31:2];
... | 7.376158 |
module CS #(
parameter WIDTH_DATA_1 = 384,
parameter WIDTH_RESULT_1 = 8,
parameter WIDTH_DATA_2 = 128,
parameter WIDTH_RESULT_2 = 8
) (
data,
in_valid,
clk,
rst_n,
result,
out_valid
);
input [(WIDTH_DATA_1 + WIDTH_DATA_2 - 1):0] data;
input in_valid, clk, rst_n;
outpu... | 8.656841 |
module CS #(
parameter WIDTH_DATA_1 = 384,
parameter WIDTH_RESULT_1 = 8,
parameter WIDTH_DATA_2 = 128,
parameter WIDTH_RESULT_2 = 8
) (
data,
in_valid,
clk,
rst_n,
result,
out_valid
);
//================================================================
// INPUT AND OUTPUT... | 8.656841 |
module cs_lbp (
windowIn,
lbpPattern
); // 3x3 Center Symetric LBP Patterns
parameter inputWidth = 8;
parameter threshold = 5;
input [inputWidth*9-1:0] windowIn;
wire [inputWidth-1:0] win[0:8];
wire [7:0] comparisonString[0:8];
output [3:0] lbpPattern;
generate
// Make comparisons and c... | 6.903228 |
module: counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ctb;
// Inputs
reg clk;
reg reset;
// Outputs
wire [31:0] out;
// Instantiate the Unit Under Test (UUT)
coun... | 7.040838 |
module : dct_top_2d.v
//data : 2018.01.25
//file name : ctl0.v
//delay : 0 clk
//describe :
//modification :
//v1.0 :
module ctl0(
i_inverse ,
i_valid ,
o_valid0 ,//to mux2
o_valid1 //to mux0
);
// **************************************... | 6.830511 |
module : dct_top_2d.v
//data : 2018.01.29
//file name : ctl1.v
//delay : 0 clk
//describe :
//modification :
//v1.0 :
module ctl1(
i_inverse ,
i_valid ,
o_valid0 ,//mux0
o_valid1 //pe
);
// ********************************************
//... | 6.830511 |
module : dct_top_2d.v
//data : 2018.01.25
//file name : ctl2.v
//delay : 0 clk
//describe :
//modification :
//v1.0 :
module ctl2(
i_valid ,
i_inverse,
//----------------------------------//
o_valid0,//to dct
o_valid1//to i_dct
);
// **********... | 6.830511 |
module : dct_top_2d.v
//data : 2018.02.07
//file name : ctl3.v
//delay : 0 clk
//describe :
//modification :
//v1.0 :
module ctl3(
i_valid ,
i_inverse,
//----------------------------------//
o_valid0 ,//to mux1
o_valid1 //to mux3
);
// **********... | 6.830511 |
module ctlButtons #(
parameter speed = 1
) (
input wire clk,
input wire ply1_up,
input wire ply1_down,
input wire ply2_up,
input wire ply2_down,
output wire [9:0] pos_ply1,
output wire [9:0] pos_ply2
);
// Parameters for vertical players.
parameter ... | 7.919781 |
module ctl_enemy_test;
reg pclk;
reg rst;
wire [10:0] xpos;
wire [10:0] ypos;
wire on;
ctl_enemy ctl_en (
.pclk(pclk),
.rst (rst),
.xpos_out(xpos),
.ypos_out(ypos),
.on(on)
);
initial // reset implementation
begin
rst = 0;
#200;
rst = 1;
#... | 6.847882 |
module generate x, y and on for missile for one enemy
`timescale 1 ns / 1 ps
module ctl_missile_en (
input wire pclk,
input wire rst,
input wire [10:0] xpos_in,
input wire [10:0] ypos_in,
input wire missle_button,
input wire enemy_lives,
output reg [10:0] ypos_out,
output reg [10:0] x... | 7.190229 |
module ctl_rom (
input [5:0] op, // address
input reset,
we,
oe,
input irq,
z, // for later logic in ctl unit
output [17:0] p
); // p is data_out
reg [17:0] temp_data;
reg [17:0] rom[63:0];
initial begin
$readmemb("ctl_rom_data.txt", rom);
end
always @(*) begin
if (re... | 7.127532 |
module is genereating xpos_out by calculating inputs form keyboard
`timescale 1 ns / 1 ps
module position_rect_ctl
#( parameter
RESET_X_POS = 0
)(
input wire pclk,
input wire rst,
input wire dead_s,
input wire left,
input wire right,
output reg [10:0] xpos_out
);
localpar... | 7.026473 |
module ctr #(
parameter width = 10
) (
output [width-1:0] ctrOut,
input clk,
input rst,
input en,
input dir, // 0 -> Decrement , 1 -> Increment
input jmp,
input [width-1:0] jmpLoc
);
reg [width-1:0] ctrOutAux;
always @(posedge clk) begin
if (rst) ctrOutAux <= {(width) {1'b1... | 7.154539 |
module ctrace #(
parameter dw = 8, // width of data word captured
parameter tw = 24, // width of counter word keeping track of time
parameter aw = 10 // width of address, sets depth of memory
) (
input clk,
input [dw-1:0] data,
// Control in clk domain
input start, // single-cycle
... | 7.581248 |
module ctrace_tb;
reg clk;
integer cc;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("ctrace.vcd");
$dumpvars(5, ctrace_tb);
end
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 2000; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#... | 6.795476 |
module ctree ( /*AUTOARG*/
// Outputs
co,
// Inputs
ci
);
parameter DW = 2; // the total number of leaves of the C-element tree
input [DW-1:0] ci; // all input leaves
output co; // the combined output
wire [2*DW-2:0] dat;
genvar i;
assign dat[DW-1:0] = ci;
generate
for (i = 0;... | 7.938186 |
module ctrg_rmv (
// input
CLK,
RSTN,
PSW,
// output
PSW_SIG
);
//------ input --------------------------------------------
input CLK, RSTN;
input [2:0] PSW;
//------ output -------------------------------------------
output [2:0] PSW_SIG;
//------ reg ------------------------------... | 7.023706 |
module ctrl (
input wire rst,
input wire stallreq_from_id,
input wire stallreq_from_ex,
input wire stallreq_from_if,
input wire stallreq_from_mem,
input wire [`WordBus] cp0_epc_i,
input wire [`WordBus] excepttype_i,
output reg [`WordBus] new_pc,
output reg flush,
output wire ... | 6.946795 |
module CTRL1 (
input clk,
input rst_n,
input valid_i,
input signed [16:0] data_in_r,
input signed [16:0] data_in_i,
output reg valid_o,
output reg [ 1:0] state,
output reg signed [16:0] data_out_r,
output reg signed [16:... | 7.839282 |
module ctrl4 (
jal4,
RegDin4,
RegWrite4,
DMWrite,
mode,
ctrl4
);
input [21:0] ctrl4;
output jal4, RegDin4, RegWrite4, DMWrite;
output [3:0] mode;
assign jal4 = ctrl4[1];
assign RegDin4 = ctrl4[7];
assign RegWrite4 = ctrl4[8];
assign DMWrite = ctrl4[9];
assign mode = ctrl4[16:13];... | 7.144407 |
module ctrl5 (
jal5,
RegDin5,
RegWrite5,
syscall5,
equal5,
ctrl5
);
input [21:0] ctrl5;
output jal5, RegDin5, RegWrite5, syscall5, equal5;
assign jal5 = ctrl5[1];
assign RegDin5 = ctrl5[7];
assign RegWrite5 = ctrl5[8];
assign syscall5 = ctrl5[12];
assign equal5 = ctrl5[21];
endmodu... | 7.291687 |
module CTRL8 (
input clk,
input rst_n,
input valid_i,
input signed [13:0] data_in_r,
input signed [13:0] data_in_i,
output reg valid_o,
output reg [ 1:0] state,
output reg signed [13:0] data_out_r,
output reg signed [13:... | 7.59655 |
module controls access to the adc modules.
* It is implemented to simultaneously interface with 4 adcs for the pots (with common
* sclk/conv) and with 4 adcs for the motor current feedback (with common sclk/conv).
*
* For a different number of channels (e.g., 8 instead of 4), it is easier to
* directly instantiate... | 8.016412 |
module ctrlD (
input DCK,
input rst,
input DEN,
output reg CENB
);
parameter IDLE = 2'b00, IN = 2'b01, WRITE = 2'b10;
reg [1:0] cstate, nstate;
always @(posedge DCK, posedge rst) begin
if (rst) cstate <= IDLE;
else cstate <= nstate;
end
always @* begin
case (cstate)
IDLE... | 7.318008 |
module DoutCfgCheck (
input wire sysclk, // global clock
input wire dir12_read, // direction control for channels 1-2 (QLA Rev 1.4+)
input wire dir34_read, // direction control for channels 3-4 (QLA Rev 1.4+)
output reg dir12_reg, // direction control for channels 1-2 (QLA R... | 7.062027 |
module DoutPWM (
input wire sysclk, // sysclk
output wire [31:0] reg_rdata, // outgoing register data (control register)
input wire ctrl_enable, // write enable signal for control register
input wire [31:0] reg_wdata, // incoming register data (for control register)
inp... | 7.255951 |
module Ctrl_EX (
input wire clk,
bubbleE,
flushE,
input wire jalr_ID,
input wire [3:0] ALU_func_ID,
input wire [2:0] br_type_ID,
input wire load_npc_ID,
input wire wb_select_ID,
input wire [2:0] load_type_ID,
input wire reg_write_en_ID,
input wire [3:0] cache_write_en_ID,
... | 6.975901 |
module ctrl_flow #(
parameter XLEN = 32,
parameter [XLEN - 1:0] RESET = 0
) (
input clock,
input reset,
input pause,
input [XLEN - 1:0] nxt_pc,
output reg [XLEN - 1:0] pc
);
initial begin
pc = 0;
end
always @(posedge clock) begin
if (reset) pc <= RESET;
else if (!pause) pc... | 6.898224 |
module fetch #(
parameter XLEN = 32
) (
input clock,
input [XLEN - 1:0] pc,
output ready,
output [XLEN - 1:0] instruction
);
gnr_ram imem (
.clock(clock),
.write_en(1'b0),
.w_addr({XLEN{1'b0}}),
.r_addr(pc),
.ready(ready),
.data_o(instruction)
);
endmodule
| 7.00256 |
module addr_gen #(
parameter XLEN = 32
) (
input alu_z,
input s_jump,
input s_jalr,
input s_branch,
input s_branch_zero,
input [XLEN - 1:0] pc,
input [XLEN - 1:0] ex_pc,
input [XLEN - 1:0] imm,
input [XLEN - 1:0] alu_o,
output branch_take,
output [XLEN - 1:0] nxt_pc
);
... | 7.930522 |
module ctrlG (
input GCK,
input rst,
input Vsync,
input Vsync_pulse,
input first,
input read_start,
input first_read_done,
input frameout_done,
output reg CENA,
output reg out_en
);
parameter IDLE = 2'b00, R_O = 2'b01;
reg [1:0] cstate, nstate;
always @(posedge GCK, pos... | 8.51896 |
module CtrlHazard (
input [1:0] ID_NPCOp,
output IFIDFlush
);
wire goAway = ID_NPCOp != `NPC_PLUS4;
assign IFIDFlush = goAway; //flush the instruction at IF
endmodule
| 6.619423 |
module is to take care of control hazard, for now the
* scheme is to predict that branch will always to be untaken, so CPU will
* always execute branch instruction's following instructions, if the
* prediction is wrong, then the unit will flush IF/ID, ID/EX and EX/MEM's
* control signals and instruction field to zero... | 7.528277 |
module Ctrl_MEM (
input wire clk,
bubbleM,
flushM,
input wire wb_select_EX,
input wire [2:0] load_type_EX,
input wire reg_write_en_EX,
input wire [3:0] cache_write_en_EX,
output reg wb_select_MEM,
output reg [2:0] load_type_MEM,
output reg reg_write_en_MEM,
output reg [3:0] c... | 7.880536 |
module ctrlport_clk_crossing_derived (
// Clocks
input wire i_clk,
input wire o_clk,
// Request (domain: i_clk)
input wire i_ctrlport_rst,
input wire i_ctrlport_req_wr,
input wire i_ctrlport_req_rd,
input wire [19:0] i_ctrlport_req_addr,
input wire [31:0] i_ctrl... | 6.990918 |
module ctrlport_gate (
input wire ctrlport_clk,
input wire ctrlport_rst,
// Control interface
input wire enable,
// Slave interface
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [ 9:0] s_ctrlport_req_... | 7.396819 |
module combines the control-port responses from multiple slave blocks
// into a single response for the master. This is done by using ack bit to
// mask all bits of the responses then ORing all the results together onto a
// single response bus. This is valid because only one block is allowed to
// respond ... | 7.076524 |
module ctrlport_to_regport #(
parameter REG_AWIDTH = 20,
parameter REG_DWIDTH = 32
) (
input clk,
input rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
output reg ... | 8.802712 |
modules does
// not use any registers and therefore does not need ctrlport_clk and
// ctrlport_rst.
//
`default_nettype none
module ctrlport_window #(
parameter BASE_ADDRESS = 0,
parameter WINDOW_SIZE = 32
) (
// Slave Interface
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd... | 6.93097 |
module CTRLps2 #(
parameter clk_freq = 50000000
) (
input sys_rst,
input sys_clk,
input we_reg, //datainput
input [4:0] rx_bitcount, //recordar activar e igualar el chip select desde el wishbone
output reg ps2_clk_out,
output reg ps2_data_out1,
output reg tx_busy,
output state_re... | 7.277924 |
module ctrlsoc_spram (
input clk,
input enable,
input [15:0] addr,
input [ 3:0] wstrb,
input [31:0] wdata,
output [31:0] rdata
);
SB_SPRAM256KA spram_hi (
.ADDRESS(addr[15:2]),
.DATAIN(wdata[31:16]),
.MASKWREN({{2{wstrb[3]}}, {2{wstrb[2]}}}),
.WREN(|w... | 6.875799 |
module ctrlsoc_rxtx (
input clk,
input resetn,
input rx,
output tx,
input mem_wvalid,
input [31:0] mem_wdata,
input mem_rvalid,
output reg [31:0] mem_rdata,
output reg mem_ready
);
localparam [7:0] clkdiv_cnt_steps = 104;
reg [7:0] clkdiv_... | 7.125715 |
module testbench;
//Input
output reg[31:0] instrWord; // since the Instruction being seen from the input is the full 32 bit instruction you will send a 32 bit instruction to the input
//Output
input wire RegDest;
input wire RegWrite;
input wire ALUSrc;
input wire ALUOp1;
input wire ALUOp0;
input ... | 7.015571 |
module ctrltop ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Input Ports-----------------------------
input clk;
input rst_n;
input top_ctrltop_start;
input top_ctrltop_cfg_w;
input top_ctrltop_cfg_r;
input [MSB_REGS_ADDRESS:0] top_ctrltop_cfg_addr;
input [MSB:0] top_ctrltop_cfg_data_in;
... | 7.481276 |
module ctrlu_top (
input clk,
input Br,
input Z,
input [7:0] IR,
input [4:0] naddr,
output [34:0] out
);
/*
The module for the top part of the control unit
*/
wire [4:0] MAPLogic_connect;
wire [4:0] logicReg_connect;
wire [4:0] naregROM_connect;
//wire [4:0] out;
MAP MAP1 (
... | 8.18128 |
module control_ad724 (
input wire clk,
input wire poweron_rst_n,
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire [7:0] din,
output wire [7:0] dout,
output wire oe,
output wire ad724_xtal,
output wire ad724_mode,
output wire ad724_enable... | 6.724224 |
module ctrl_botones (
input wire clkr,
input wire levelr,
output wire tickr
);
reg FF1;
reg FF2;
reg FF3;
reg FF4;
always @(posedge clkr) begin
FF1 <= levelr; //el siguiente valor de FF1 sera elevelr
FF2 <= FF1; //el siguiente valor de FF2 sera FF1
FF3 <= FF2; //el siguiente va... | 7.154743 |
module ctrl_botones_down (
input wire clkd,
input wire leveld,
output wire tickd
);
reg FF1;
reg FF2;
reg FF3;
reg FF4;
always @(posedge clkd) begin
FF1 <= leveld; //el siguiente valor de FF1 sera inp
FF2 <= FF1; //el siguiente valor de FF2 sera FF1
FF3 <= FF2; //el siguiente v... | 7.285295 |
module ctrl_bus #(
parameter MAW = 13, // master address width
parameter SAW = 12, // slave address width
parameter QDW = 32, // data width
parameter QSW = QDW / 8 // select width
) (
// system
input wire clk,
input wire rst,
// master 0 (dcpu)
i... | 7.444905 |
module ctrl_cpu (
input wire up_clk,
input wire up_cs,
input wire up_wr,
input wire up_rd,
input wire [32-1:0] up_addr,
input wire [ 31:0] up_data_wr,
output wire [ 31:0] up_data_rd,
output wire up_busy,
output wire ctrl... | 6.820204 |
module CTRL_DISP (
input wire [2:0] IN_Frec,
input wire [4:0] IN_Co,
input wire CLK,
input wire IN_Sel,
input wire IN_Reset,
output wire [3:0] OUT_An,
output wire [7:0] OUT_Cat
);
wire [3:0] Uni;
wire [3:0] Dec;
wire [3:0] Cen;
wire [3:0] Mil;
Cod_Display Cod_Disp (
.Frecu... | 7.791442 |
module ctrl_gen (
input [6:0] op,
input [2:0] func3,
input func7_5,
output reg [2:0] ExtOp,
output reg RegWr,
output reg ALUAsrc,
output reg [1:0] ALUBsrc,
output reg [3:0] ALUctr,
output reg [2:0] Branch,
output reg MemtoReg,
output reg MemWr,
output [2:0] MemOp
);
a... | 7.084586 |
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