code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Ctrl_I2C_Op (
input clk,
input rst_n,
input wr_en,
input rd_en,
input i2c_done,
output reg i2c_start,
output reg [31:0] eeprom_config_data
);
wire [7:0] wr_device_addr = 8'hA0; //8'hA0дַ8'hA1ַ
wire [7:0] rd_devic... | 7.041967 |
module ctrl_mc_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8
, parameter DEPTH = 4
, parameter ADDR_W = 2
)
//-----------------------------------------------------------------
... | 6.971319 |
module ctrl_mc_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-------------------------------------... | 7.838507 |
module ctrl_mdio (
input wire rst,
input wire up_clk,
input wire up_wr,
input wire up_rd,
input wire [31:0] up_addr,
input wire [31:0] up_data_wr,
output reg [31:0] up_data_rd,
input wire mdio_clk,
inout wire mdio_io
);
// tri-state driver
wire mdio... | 6.887175 |
module Ctrl_mux (
input flush,
input PCtoRegSrc_in,
input branchCtrl_in,
input aluop_in,
input alusrc_in,
input regWrite_in,
input rdsrc_in,
input memRead_in,
input memWrite_in,
input memToReg_in,
output PCtoRegSrc_out,
output branchCtrl_out,
output aluop_ou... | 7.794764 |
module ctrl_opb_attach #(
parameter C_BASEADDR = 0,
parameter C_HIGHADDR = 0,
parameter C_OPB_AWIDTH = 32,
parameter C_OPB_DWIDTH = 32
) (
input OPB_Clk,
input OPB_Rst,
output [0:31] Sl_DBus,
output Sl_errAck,
output Sl_retry,
output Sl_toutSup,
output Sl_xferAck,
inp... | 8.046243 |
module CTRL_RAM (
input sys_clk,
input sys_rst,
// Signals RAM
input dataram,
output reg [7:0] dataLCD,
output reg rd,
//Signals SYNC
input H_DONE,
input V_DONE,
input CLKIN
);
/* FSM */
reg [1:0] state;
reg [1:0] next_state;
reg [1:0] countp;
parameter WAIT_RD = 3'... | 7.62759 |
module ctrl_rst (
// system
input wire clk,
// PLL lock input
input wire pll_lock,
// external reset input
input wire rst_ext,
// register reset input
input wire rst_reg,
// reset signal output
output reg rst
);
////////////////////////////////////////
// internal sig... | 7.90758 |
module: ctrl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ctrl_test;
// Inputs
reg clk;
reg rst;
reg [31:0] ir_data;
reg zero;
// Outputs
wire write_pc;
wire iord;
wire... | 6.640279 |
module ctrl_transmemory (
clk,
rst,
i_valid,
i_transize,
wen,
enable,
counter
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 6.660744 |
module CTRL_TX #(
parameter WIDTH = 8,
ADDR = 4
) (
input wire CLK,
input wire RST,
input wire UART_RF_SEND,
input wire [ WIDTH-1:0] UART_SEND_RF_DATA,
input wire UART_ALU_SEND,
input wire [WIDTH*2-1:0] UART_SEND_ALU_DATA,
... | 8.732038 |
module: counterrr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ctrrrr;
// Inputs
reg clk;
reg out;
reg reset;
// Instantiate the Unit Under Test (UUT)
counterrr uut (
.c... | 7.378668 |
module ctr_tb ();
wire [9:0] ctrOut;
reg clk, rst, en, dir, jmp;
reg [9:0] jmpLoc;
ctr UUT (
.clk(clk),
.en(en),
.dir(dir),
.jmp(jmp),
.jmpLoc(jmpLoc),
.rst(rst),
.ctrOut(ctrOut)
);
initial begin
clk = 0;
en = 1;
dir = 1;
jmp = 0;
jmpLoc = 10'b... | 6.855832 |
module ctr_update (
clk,
rst,
re,
we,
hit,
miss,
evict_data,
write_addr,
access_addr,
evict_addr
, update_EVA,
hitCtr_R_1D,
evictionCtr_R_1D,
hitCtr_NR_1D,
evictionCtr_NR_1D,
age_1D,
classificationBit
);
parameter k = 3; /////////////age counter w... | 8.282612 |
module ctu_clsp_synch_dldg ( /*AUTOARG*/
// Outputs
start_clk_dg,
ctu_ddr0_dram_cken_dg,
ctu_ddr1_dram_cken_dg,
ctu_ddr2_dram_cken_dg,
ctu_ddr3_dram_cken_dg,
ctu_dram02_dram_cken_dg,
ctu_dram13_dram_cken_dg,
a_grst_dg,
a_dbginit_dg,
de_grst_dsync_edge_dg,
de_dbginit_dsyn... | 6.769114 |
module ctu_level_mon (
hi,
lo,
mon_en,
mon_num,
off_on
);
input hi; // hi signal
input lo; // lo signal
input mon_en; // monitor enable
input [31:0] mon_num; // monitor num for failure tracking
input off_on; // turn off if 1
always @(hi or lo) begin
if (!$test$plusargs("ct... | 6.728599 |
module: counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ctx;
// Inputs
reg clk;
reg reset;
// Outputs
wire [31:0] out;
// Instantiate the Unit Under Test (UUT)
coun... | 7.040838 |
module ct_15t_gen #
(
parameter CLK_FREQ = 'd50000000,// 50MHz
parameter BAUD_RATE = 'd9600 //
)
(
input clk ,// system clock
input rst_n ,// system reset, active low
input rx_done ,// pos-pulse for 1 tick indicates 1 byte transfer done
in... | 7.566583 |
module ct_35t_gen #
(
parameter CLK_FREQ = 'd50000000,// 50MHz
parameter BAUD_RATE = 'd9600 //
)
(
input clk ,// system clock
input rst_n ,// system reset, active low
input rx_done ,// pos-pulse for 1 tick indicates 1 byte transfer done
input... | 7.656072 |
module ct_ciu_snb_dp_sel_16 (
entry0_age_vect,
entry10_age_vect,
entry11_age_vect,
entry12_age_vect,
entry13_age_vect,
entry14_age_vect,
entry15_age_vect,
entry1_age_vect,
entry2_age_vect,
entry3_age_vect,
entry4_age_vect,
entry5_age_vect,
entry6_age_vect,
entry7_... | 6.691074 |
module ct_ciu_snb_dp_sel_8 (
entry16_age_vect,
entry17_age_vect,
entry18_age_vect,
entry19_age_vect,
entry20_age_vect,
entry21_age_vect,
entry22_age_vect,
entry23_age_vect,
req_vld,
sel
);
// &Ports; @19
input [23:0] entry16_age_vect;
input [23:0] entry17_age_vect;
input... | 6.691074 |
module ct_clk_top (
biu_xx_dbg_wakeup,
biu_xx_int_wakeup,
biu_xx_normal_work,
biu_xx_pmp_sel,
biu_xx_snoop_vld,
coreclk,
cp0_xx_core_icg_en,
forever_coreclk,
had_xx_clk_en,
pll_core_clk
);
// &Ports; @23
input biu_xx_dbg_wakeup;
input biu_xx_int_wakeup;
input biu_xx_norm... | 6.961003 |
module ct_f_spsram_1024x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [9 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @27
reg [9 : 0] addr_holding;
// &Wires; @28
wire [9 : 0] A;
wire ... | 7.05322 |
module ct_f_spsram_1024x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 144;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_W... | 7.05322 |
module ct_f_spsram_1024x32 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [9 : 0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @27
reg [9 : 0] addr_holding;
// &Wires; @28
wire [9 : 0] A;
wire ... | 7.05322 |
module ct_f_spsram_1024x59 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [9 : 0] A;
input CEN;
input CLK;
input [58:0] D;
input GWEN;
input [58:0] WEN;
output [58:0] Q;
// &Regs; @27
reg [9 : 0] addr_holding;
// &Wires; @28
wire [9 : 0] A;
wire ... | 7.05322 |
module ct_f_spsram_1024x64 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 64;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WID... | 7.05322 |
module ct_f_spsram_1024x92 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @4
input [9 : 0] A;
input CEN;
input CLK;
input [91:0] D;
input GWEN;
input [91:0] WEN;
output [91:0] Q;
// &Regs; @5
reg [9 : 0] addr_holding;
// &Wires; @6
wire [9 : 0] A;
wire CEN... | 7.05322 |
module ct_f_spsram_128x104 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @4
input [6 : 0] A;
input CEN;
input CLK;
input [103:0] D;
input GWEN;
input [103:0] WEN;
output [103:0] Q;
// &Regs; @5
reg [ 6 : 0] addr_holding;
// &Wires; @6
wire [ 6 : 0] A;
wire ... | 7.05322 |
module ct_f_spsram_128x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 7;
parameter DATA_WIDTH = 144;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WID... | 7.05322 |
module ct_f_spsram_16384x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [13 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @27
reg [13 : 0] addr_holding;
// &Wires; @28
wire [13 : 0] A;
wire ... | 7.05322 |
module ct_f_spsram_2048x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [10 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @27
reg [10 : 0] addr_holding;
// &Wires; @28
wire [10 : 0] A;
wire ... | 6.97682 |
module ct_f_spsram_2048x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 11;
parameter DATA_WIDTH = 144;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_W... | 6.97682 |
module ct_f_spsram_2048x32 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [10:0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @27
reg [ 10:0] addr_holding;
// &Wires; @28
wire [ 10:0] A;
wire C... | 6.97682 |
module ct_f_spsram_2048x59 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [10:0] A;
input CEN;
input CLK;
input [58:0] D;
input GWEN;
input [58:0] WEN;
output [58:0] Q;
// &Regs; @27
reg [ 10:0] addr_holding;
// &Wires; @28
wire [ 10:0] A;
wire C... | 6.97682 |
module ct_f_spsram_2048x88 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 11;
parameter DATA_WIDTH = 88;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WID... | 6.97682 |
module ct_f_spsram_256x100 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @4
input [7 : 0] A;
input CEN;
input CLK;
input [99:0] D;
input GWEN;
input [99:0] WEN;
output [99:0] Q;
// &Regs; @5
reg [7 : 0] addr_holding;
// &Wires; @6
wire [7 : 0] A;
wire CEN... | 6.97682 |
module ct_f_spsram_256x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 144;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WID... | 6.97682 |
module ct_f_spsram_256x196 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @25
input [7 : 0] A;
input CEN;
input CLK;
input [195:0] D;
input GWEN;
input [195:0] WEN;
output [195:0] Q;
// &Regs; @26
reg [ 7 : 0] addr_holding;
// &Wires; @27
wire [ 7 : 0] A;
wire ... | 6.97682 |
module ct_f_spsram_256x23 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [7 : 0] A;
input CEN;
input CLK;
input [22:0] D;
input GWEN;
input [22:0] WEN;
output [22:0] Q;
// &Regs; @27
reg [7 : 0] addr_holding;
// &Wires; @28
wire [7 : 0] A;
wire C... | 6.97682 |
module ct_f_spsram_256x52 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [7 : 0] A;
input CEN;
input CLK;
input [51:0] D;
input GWEN;
input [51:0] WEN;
output [51:0] Q;
// &Regs; @27
reg [7 : 0] addr_holding;
// &Wires; @28
wire [7 : 0] A;
wire C... | 6.97682 |
module ct_f_spsram_256x54 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [7 : 0] A;
input CEN;
input CLK;
input [53:0] D;
input GWEN;
input [53:0] WEN;
output [53:0] Q;
// &Regs; @27
reg [7 : 0] addr_holding;
// &Wires; @28
wire [7 : 0] A;
wire C... | 6.97682 |
module ct_f_spsram_256x59 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [7 : 0] A;
input CEN;
input CLK;
input [58:0] D;
input GWEN;
input [58:0] WEN;
output [58:0] Q;
// &Regs; @27
reg [7 : 0] addr_holding;
// &Wires; @28
wire [7 : 0] A;
wire C... | 6.97682 |
module ct_f_spsram_256x84 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @25
input [7 : 0] A;
input CEN;
input CLK;
input [83:0] D;
input GWEN;
input [83:0] WEN;
output [83:0] Q;
// &Regs; @26
reg [7 : 0] addr_holding;
// &Wires; @27
wire [7 : 0] A;
wire C... | 6.97682 |
module ct_f_spsram_32768x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 15;
parameter DATA_WIDTH = 128;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_... | 7.680748 |
module ct_f_spsram_4096x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [11 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @27
reg [11 : 0] addr_holding;
// &Wires; @28
wire [11 : 0] A;
wire ... | 7.991172 |
module ct_f_spsram_4096x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 12;
parameter DATA_WIDTH = 144;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_W... | 7.991172 |
module ct_f_spsram_4096x32 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @26
input [11:0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @27
reg [ 11:0] addr_holding;
// &Wires; @28
wire [ 11:0] A;
wire C... | 7.991172 |
module ct_f_spsram_4096x84 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 12;
parameter DATA_WIDTH = 84;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WID... | 7.991172 |
module ct_f_spsram_64x108 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @4
input [5 : 0] A;
input CEN;
input CLK;
input [107:0] D;
input GWEN;
input [107:0] WEN;
output [107:0] Q;
// &Regs; @5
reg [ 5 : 0] addr_holding;
// &Wires; @6
wire [ 5 : 0] A;
wire ... | 7.488776 |
module ct_f_spsram_65536x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 16;
parameter DATA_WIDTH = 128;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_... | 7.488776 |
module ct_had_sync_3flop (
clk1,
clk2,
rst1_b,
rst2_b,
sync_in,
sync_out
);
// &Ports; @25
input clk1;
input clk2;
input rst1_b;
input rst2_b;
input sync_in;
output sync_out;
// &Regs; @26
reg sync_ff1_clk1;
reg sync_ff2_clk1;
reg sync_ff3_clk1;
reg sync_ff4_clk1;
... | 6.737718 |
module ct_idu_is_aiq_lch_rdy_1 (
cpurst_b,
vld,
x_create_dp_en,
x_create_entry,
x_create_lch_rdy,
x_read_lch_rdy,
y_clk,
y_create0_dp_en,
y_create0_src_match,
y_create1_dp_en,
y_create1_src_match
);
// &Ports; @25
input cpurst_b;
input vld;
input x_create_dp_en;
in... | 6.918868 |
module ct_idu_is_aiq_lch_rdy_2 (
cpurst_b,
vld,
x_create_dp_en,
x_create_entry,
x_create_lch_rdy,
x_read_lch_rdy,
y_clk,
y_create0_dp_en,
y_create0_src_match,
y_create1_dp_en,
y_create1_src_match
);
// &Ports; @25
input cpurst_b;
input vld;
input x_create_dp_en;
in... | 6.918868 |
module ct_idu_is_aiq_lch_rdy_3 (
cpurst_b,
vld,
x_create_dp_en,
x_create_entry,
x_create_lch_rdy,
x_read_lch_rdy,
y_clk,
y_create0_dp_en,
y_create0_src_match,
y_create1_dp_en,
y_create1_src_match
);
// &Ports; @25
input cpurst_b;
input vld;
input x_create_dp_en;
in... | 6.918868 |
module ct_ifu_icache_tag_array(
cp0_ifu_icg_en,
forever_cpuclk,
icache_ifu_tag_dout,
ifu_icache_index,
ifu_icache_tag_cen_b,
ifu_icache_tag_clk_en,
ifu_icache_tag_din,
ifu_icache_tag_wen,
pad_yy_icg_scan_en
);
input forever_cpuclk;
input cp0_ifu_icg_en;
input [15:0] ifu_... | 7.014914 |
module ct_l2cache_data_array(
data_cen,
data_clk,
data_din,
data_dout,
data_gwen,
data_idx,
data_wen,
pad_yy_icg_scan_en
);
parameter DATA_INDEX_WIDTH = `L2C_DATA_INDEX_WIDTH;
input data_cen;
input data_clk;
input [127:0] data_din;
input ... | 6.922513 |
module ct_l2cache_dirty_array_16way(
dirty_cen,
dirty_clk,
dirty_din,
dirty_dout,
dirty_gwen,
dirty_idx,
dirty_wen
);
parameter TAG_INDEX_WIDTH = `L2C_TAG_INDEX_WIDTH;
input dirty_cen;
input dirty_clk;
input [143:0] dirty_din;
input dirty_gwe... | 6.676706 |
module ct_lsu_idfifo_entry (
cpurst_b,
idfifo_clk,
idfifo_create_id,
idfifo_entry_create_vld_x,
idfifo_entry_id_v
);
// &Ports; @24
input cpurst_b;
input idfifo_clk;
input [2:0] idfifo_create_id;
input idfifo_entry_create_vld_x;
output [2:0] idfifo_entry_id_v;
// &Regs; @25
reg [2... | 7.016307 |
module ct_lsu_rot_data (
data_in,
data_settle_out,
rot_sel
);
// &Ports; @24
input [127:0] data_in;
input [7 : 0] rot_sel;
output [127:0] data_settle_out;
// &Regs; @25
reg [63 : 0] data_settle;
// &Wires; @26
wire [63 : 0] data;
wire [ 127:0] data_in;
wire [63 : 0] data_rot0;
wire... | 6.83036 |
module ct_mmu_sysmap_hit (
addr_ge_bottom_x,
addr_ge_upaddr_x,
sysmap_comp_hit_x,
sysmap_mmu_hit_x
);
// &Ports; @27
input addr_ge_bottom_x;
input sysmap_comp_hit_x;
output addr_ge_upaddr_x;
output sysmap_mmu_hit_x;
// &Regs; @28
// &Wires; @29
wire addr_ge_bottom_x;
wire addr_ge_up... | 6.594601 |
module ct_rst_top (
forever_coreclk,
fpu_rst_b,
had_rst_b,
idu_rst_b,
ifu_rst_b,
lsu_rst_b,
mmu_rst_b,
pad_core_rst_b,
pad_cpu_rst_b,
pad_yy_mbist_mode,
pad_yy_scan_mode,
pad_yy_scan_rst_b
);
// &Ports; @23
input forever_coreclk;
input pad_core_rst_b;
input pad_c... | 8.131552 |
module ct_rtu_encode_32 (
x_num,
x_num_expand
);
// &Ports; @25
input [31:0] x_num_expand;
output [4 : 0] x_num;
// &Regs; @26
// &Wires; @27
wire [4 : 0] x_num;
wire [ 31:0] x_num_expand;
//==========================================================
// encode 32 bits one-hot number to 5 ... | 7.539086 |
module ct_rtu_encode_64 (
x_num,
x_num_expand
);
// &Ports; @25
input [63:0] x_num_expand;
output [5 : 0] x_num;
// &Regs; @26
// &Wires; @27
wire [5 : 0] x_num;
wire [ 63:0] x_num_expand;
//==========================================================
// encode 64 bits one-hot number to 6 ... | 7.539086 |
module ct_rtu_encode_8 (
x_num,
x_num_expand
);
// &Ports; @25
input [7:0] x_num_expand;
output [2:0] x_num;
// &Regs; @26
// &Wires; @27
wire [2:0] x_num;
wire [7:0] x_num_expand;
//==========================================================
// encode 8 bits one-hot number to 3 bits bina... | 7.539086 |
module ct_rtu_expand_32 (
x_num,
x_num_expand
);
// &Ports; @25
input [4 : 0] x_num;
output [31:0] x_num_expand;
// &Regs; @26
// &Wires; @27
wire [4 : 0] x_num;
wire [ 31:0] x_num_expand;
//==========================================================
// expand 5 bits number to 32 bit... | 8.142698 |
module ct_rtu_expand_64 (
x_num,
x_num_expand
);
// &Ports; @25
input [5 : 0] x_num;
output [63:0] x_num_expand;
// &Regs; @26
// &Wires; @27
wire [5 : 0] x_num;
wire [ 63:0] x_num_expand;
//==========================================================
// expand 6 bits number to 64 bit... | 8.142698 |
module ct_rtu_expand_8 (
x_num,
x_num_expand
);
// &Ports; @25
input [2:0] x_num;
output [7:0] x_num_expand;
// &Regs; @26
// &Wires; @27
wire [2:0] x_num;
wire [7:0] x_num_expand;
//==========================================================
// expand 3 bits number to 8 bits one-hot... | 8.142698 |
module ct_spsram_1024x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
... | 7.117555 |
module ct_spsram_1024x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [143:0] D;
input GWEN;
input [143:0] WEN;
output [143:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
... | 7.117555 |
module ct_spsram_1024x32 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
wire... | 7.117555 |
module ct_spsram_1024x59 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [58:0] D;
input GWEN;
input [58:0] WEN;
output [58:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
wire... | 7.117555 |
module ct_spsram_1024x64 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [63:0] D;
input GWEN;
input [63:0] WEN;
output [63:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
wire... | 7.117555 |
module ct_spsram_1024x92 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [91:0] D;
input GWEN;
input [91:0] WEN;
output [91:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
wire... | 7.117555 |
module ct_spsram_128x104 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [6 : 0] A;
input CEN;
input CLK;
input [103:0] D;
input GWEN;
input [103:0] WEN;
output [103:0] Q;
// &Regs; @24
// &Wires; @25
wire [6 : 0] A;
wire CEN;
wire CLK;
w... | 8.244272 |
module ct_spsram_128x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [6 : 0] A;
input CEN;
input CLK;
input [143:0] D;
input GWEN;
input [143:0] WEN;
output [143:0] Q;
// &Regs; @24
// &Wires; @25
wire [6 : 0] A;
wire CEN;
wire CLK;
w... | 8.244272 |
module ct_spsram_128x16 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [6 : 0] A;
input CEN;
input CLK;
input [15:0] D;
input GWEN;
input [15:0] WEN;
output [15:0] Q;
// &Regs; @24
// &Wires; @25
wire [6 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.244272 |
module ct_spsram_16384x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [13 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @24
// &Wires; @25
wire [13 : 0] A;
wire CEN;
wire CL... | 8.449483 |
module ct_spsram_2048x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [10 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @24
// &Wires; @25
wire [10 : 0] A;
wire CEN;
wire CLK... | 8.264404 |
module ct_spsram_2048x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [10 : 0] A;
input CEN;
input CLK;
input [143:0] D;
input GWEN;
input [143:0] WEN;
output [143:0] Q;
// &Regs; @24
// &Wires; @25
wire [10 : 0] A;
wire CEN;
wire CLK... | 8.264404 |
module ct_spsram_2048x32 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [10:0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @24
// &Wires; @25
wire [10:0] A;
wire CEN;
wire CLK;
wire [31... | 8.264404 |
module ct_spsram_2048x32_split (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [10:0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @24
// &Wires; @25
wire [10:0] A;
wire CEN;
wire CLK;
wi... | 8.264404 |
module ct_spsram_2048x59 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [10:0] A;
input CEN;
input CLK;
input [58:0] D;
input GWEN;
input [58:0] WEN;
output [58:0] Q;
// &Regs; @24
// &Wires; @25
wire [10:0] A;
wire CEN;
wire CLK;
wire [58... | 8.264404 |
module ct_spsram_2048x88 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [10:0] A;
input CEN;
input CLK;
input [87:0] D;
input GWEN;
input [87:0] WEN;
output [87:0] Q;
// &Regs; @24
// &Wires; @25
wire [10:0] A;
wire CEN;
wire CLK;
wire [87... | 8.264404 |
module ct_spsram_256x100 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [99:0] D;
input GWEN;
input [99:0] WEN;
output [99:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
wire... | 8.610478 |
module ct_spsram_256x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [143:0] D;
input GWEN;
input [143:0] WEN;
output [143:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
w... | 8.610478 |
module ct_spsram_256x196 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [195:0] D;
input GWEN;
input [195:0] WEN;
output [195:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
w... | 8.610478 |
module ct_spsram_256x23 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [22:0] D;
input GWEN;
input [22:0] WEN;
output [22:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.610478 |
module ct_spsram_256x52 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [51:0] D;
input GWEN;
input [51:0] WEN;
output [51:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.610478 |
module ct_spsram_256x54 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [53:0] D;
input GWEN;
input [53:0] WEN;
output [53:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.610478 |
module ct_spsram_256x59 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [58:0] D;
input GWEN;
input [58:0] WEN;
output [58:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.610478 |
module ct_spsram_256x7 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7:0] A;
input CEN;
input CLK;
input [6:0] D;
input GWEN;
input [6:0] WEN;
output [6:0] Q;
// &Regs; @24
// &Wires; @25
wire [7:0] A;
wire CEN;
wire CLK;
wire [6:0] D;
w... | 8.610478 |
module ct_spsram_256x84 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [83:0] D;
input GWEN;
input [83:0] WEN;
output [83:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.610478 |
module ct_spsram_32768x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [14 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @24
// &Wires; @25
wire [14 : 0] A;
wire CEN;
wire CL... | 7.78709 |
module ct_spsram_4096x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [11 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @24
// &Wires; @25
wire [11 : 0] A;
wire CEN;
wire CLK... | 8.317911 |
module ct_spsram_4096x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [11 : 0] A;
input CEN;
input CLK;
input [143:0] D;
input GWEN;
input [143:0] WEN;
output [143:0] Q;
// &Regs; @24
// &Wires; @25
wire [11 : 0] A;
wire CEN;
wire CLK... | 8.317911 |
module ct_spsram_4096x32 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [11:0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @24
// &Wires; @25
wire [11:0] A;
wire CEN;
wire CLK;
wire [31... | 8.317911 |
module ct_spsram_4096x84 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [11:0] A;
input CEN;
input CLK;
input [83:0] D;
input GWEN;
input [83:0] WEN;
output [83:0] Q;
// &Regs; @24
// &Wires; @25
wire [11:0] A;
wire CEN;
wire CLK;
wire [83... | 8.317911 |
module ct_spsram_512x144 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [8 : 0] A;
input CEN;
input CLK;
input [143:0] D;
input GWEN;
input [143:0] WEN;
output [143:0] Q;
// &Regs; @24
// &Wires; @25
wire [8 : 0] A;
wire CEN;
wire CLK;
w... | 8.033823 |
module ct_spsram_512x22 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [8 : 0] A;
input CEN;
input CLK;
input [21:0] D;
input GWEN;
input [21:0] WEN;
output [21:0] Q;
// &Regs; @24
// &Wires; @25
wire [8 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.033823 |
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