code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module ct_spsram_512x44 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [8 : 0] A;
input CEN;
input CLK;
input [43:0] D;
input GWEN;
input [43:0] WEN;
output [43:0] Q;
// &Regs; @24
// &Wires; @25
wire [8 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.033823 |
module ct_spsram_512x52 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [8 : 0] A;
input CEN;
input CLK;
input [51:0] D;
input GWEN;
input [51:0] WEN;
output [51:0] Q;
// &Regs; @24
// &Wires; @25
wire [8 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.033823 |
module ct_spsram_512x54 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [8 : 0] A;
input CEN;
input CLK;
input [53:0] D;
input GWEN;
input [53:0] WEN;
output [53:0] Q;
// &Regs; @24
// &Wires; @25
wire [8 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.033823 |
module ct_spsram_512x59 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [8 : 0] A;
input CEN;
input CLK;
input [58:0] D;
input GWEN;
input [58:0] WEN;
output [58:0] Q;
// &Regs; @24
// &Wires; @25
wire [8 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.033823 |
module ct_spsram_512x7 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [8:0] A;
input CEN;
input CLK;
input [6:0] D;
input GWEN;
input [6:0] WEN;
output [6:0] Q;
// &Regs; @24
// &Wires; @25
wire [8:0] A;
wire CEN;
wire CLK;
wire [6:0] D;
w... | 8.033823 |
module ct_spsram_512x96 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [8 : 0] A;
input CEN;
input CLK;
input [95:0] D;
input GWEN;
input [95:0] WEN;
output [95:0] Q;
// &Regs; @24
// &Wires; @25
wire [8 : 0] A;
wire CEN;
wire CLK;
wire ... | 8.033823 |
module ct_spsram_64x108 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [5 : 0] A;
input CEN;
input CLK;
input [107:0] D;
input GWEN;
input [107:0] WEN;
output [107:0] Q;
// &Regs; @24
// &Wires; @25
wire [5 : 0] A;
wire CEN;
wire CLK;
wi... | 8.658337 |
module ct_spsram_65536x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [15 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @24
// &Wires; @25
wire [15 : 0] A;
wire CEN;
wire CL... | 7.644643 |
module ct_spsram_8192x128 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [12 : 0] A;
input CEN;
input CLK;
input [127:0] D;
input GWEN;
input [127:0] WEN;
output [127:0] Q;
// &Regs; @24
// &Wires; @25
wire [12 : 0] A;
wire CEN;
wire CLK... | 7.91508 |
module ct_spsram_8192x32 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [12:0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @24
// &Wires; @25
wire [12:0] A;
wire CEN;
wire CLK;
wire [31... | 7.91508 |
module: controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CT_tb;
// Inputs
reg [5:0] Opcode;
reg [5:0] Funct;
// Outputs
wire IsBr;
wire Jump;
wire JType;
wire Reg... | 7.107088 |
module ct_vfmau_lza_32 (
lza_p0,
lza_p1,
lza_precod,
lza_vld
);
// &Ports; @24
input [2:0] lza_precod;
output lza_p0;
output lza_p1;
output lza_vld;
// &Regs; @25
// &Wires; @26
wire lza_p0;
wire lza_p1;
wire [2:0] lza_precod;
wire lza_vld;
assign lza_vld =... | 7.053723 |
module ct_vfmau_lza_42 (
lza_p0,
lza_p1,
lza_precod,
lza_vld
);
// &Ports; @24
input [3:0] lza_precod;
output lza_p0;
output lza_p1;
output lza_vld;
// &Regs; @25
// &Wires; @26
wire lza_p0;
wire lza_p1;
wire [3:0] lza_precod;
wire lza_vld;
assign lza_vld =... | 7.053723 |
module ct_vfmau_lza_simd_half (
addend,
lza_result,
lza_result_zero,
sub_vld,
summand
);
// &Ports; @24
input [23:0] addend;
input sub_vld;
input [23:0] summand;
output [4 : 0] lza_result;
output lza_result_zero;
// &Regs; @25
reg [4 : 0] lza_result;
// &Wires; @26
wire [ 23:... | 7.053723 |
module CU (
input [3:0] opcode,
input clk,
output logic reg_write_en,
output logic mem_write_en,
output logic mem_to_reg,
output logic mem_op,
output reg [1:0] ALU_select
);
// initial begin
// ALU_select <= 2'b00;
// end
always @(posedge clk) begin
case (opcode)
//... | 6.860738 |
module clock_generator ( // Clock in ports
input wire CLK_IN1,
input wire CPUContention,
input wire [2:0] pll_option,
input wire [1:0] turbo_enable,
// Clock out ports
output wire CLK_OUT1,
output wire CLK_OUT2,
output wire CLK_OUT3,
output wire ... | 6.801817 |
module cube_controller (
input CLOCK_50, // Reference clock
input [ 1:0] KEY,
input [ 3:0] SW,
inout [12:0] GPIO_2,
input [ 2:0] GPIO_2_IN,
inout [33:0] GPIO_0,
input [ 1:0] GPIO_0_IN,
inout [33:0] GPIO_1,
input [ 1:0] GPIO_1_IN,
output [ 7:0] LED
);
wire ... | 7.247154 |
module cube_ctrl (
input clk,
input rst_n,
input [1:0] rotate_mode, //00->顺90度,01->180度,11->逆90度
input [5:0] key_n,
output reg [4:0] KEY_Value
);
wire [5:0] KEY_STATE, KEY_FLAG;
//模块例化
KeyPress k0 (
.clk(clk),
.rst_n(rst_n),
.KEY_IN(key_n[0]),
.KEY_FLAG(KEY_FLAG[0]),
... | 7.911935 |
module cube (
input clk_i,
input rst_i,
input [7:0] x_bi,
input start_i,
output busy_o,
output reg [7:0] y_bo
);
localparam IDLE = 3'b000;
localparam STATE1 = 3'b001;
localparam STATE2 = 3'b010;
localparam STATE3 = 3'b011;
localparam STATE4 = 3'b100;
localparam START = 6'sd6;
loc... | 7.387705 |
module cube_tb ();
reg clk;
reg rst;
reg [7:0] x;
wire busy;
reg start;
wire [7:0] y;
cube cube_rt (
.clk_i(clk),
.rst_i(rst),
.x_bi(x),
.start_i(start),
.busy_o(busy),
.y_bo(y)
);
integer i;
reg [7:0] expected_val;
always #10 clk = ~clk;
initial begin
... | 6.676049 |
module curegs (
clk,
rst,
satctrl_o,
mulsign_o,
spec_regs_raddr_i,
spec_regs_waddr_i,
spec_regs_ren_i,
spec_regs_wen_i,
spec_regs_data_i,
spec_regs_data_o
);
`include "specregs.v"
input clk;
input rst;
input [5:0] spec_regs_raddr_i;
input [5:0] spec_regs_waddr_i;
... | 6.575014 |
module RegFileCur (
clk,
reset,
WE,
DataIN,
DataOUT
);
input clk, reset, WE;
input [63:0] DataIN;
output [(16*16*8)-1:0] DataOUT;
reg [(16*16*8)-1:0] CurrentBlock;
reg [4:0] write_count;
always @(posedge clk, posedge reset) begin
if (reset) begin
CurrentBlock <= 2048'b0;
... | 6.547785 |
module RegFileCur (
clk,
reset,
WE,
DataIN,
DataOUT
);
input clk, reset, WE;
input [63:0] DataIN;
output [(16*16*8)-1:0] DataOUT;
reg [0:(16*16*8)-1] CurrentBlock;
reg [4:0] write_count;
always @(posedge clk, posedge reset) begin
if (reset) begin
CurrentBlock <= 2048'b0;
... | 6.547785 |
module DMIToTL ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@87420.2]
input auto_out_a_ready, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@87423.4]
output [8:0] auto_out_a_bits_address, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@87423.4]
input auto_out_d_valid, ... | 6.634693 |
module AsyncResetRegVec_w32_i0 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88785.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88786.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88787.4]
input [31:0] io_d, // @[:e... | 6.68936 |
module AsyncResetRegVec_w1_i0 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88815.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88816.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88817.4]
input io_d, // @[:example.TestHarness.Gem... | 6.68936 |
module IntSyncCrossingSource ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@89834.2]
input auto_in_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@89837.4]
output auto_out_sync_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@89837.4]
);
assign auto_out_sync_0 = auto_in... | 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91299.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91300.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91301.4]
input io_d, // @[:example.... | 6.605499 |
module AsyncValidSync ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91451.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91452.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91453.4]
output io_out // @[:example.TestHarness.GemminiSocT... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91481.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91482.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91483.4]
input io_d, // @[:example.... | 6.605499 |
module AsyncValidSync_1 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91497.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91498.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91499.4]
input io_in, // @[:example.TestHarness.GemminiSo... | 6.70336 |
module AsyncValidSync_2 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91585.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91586.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91587.4]
input io_in, // @[:example.TestHarness.GemminiSo... | 6.70336 |
module SynchronizerShiftReg_w43_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91783.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91784.4]
input [42:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91786.4]
output [42:0] io_q // @[... | 6.820992 |
module SynchronizerShiftReg_w55_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@116649.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@116650.4]
input [54:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@116652.4]
output [54:0] io_q //... | 6.820992 |
module SynchronizerShiftReg_w15_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@117757.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@117758.4]
input [14:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@117760.4]
output [14:0] io_q //... | 6.820992 |
module IntXbar_4 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@123354.2]
input auto_int_in_3_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@123357.4]
input auto_int_in_2_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@123357.4]
input auto_int_in_1_0, // @[:exa... | 6.635383 |
module PE ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@163986.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@163987.4]
input [7:0] io_inR, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@163989.4]
input [7:0] io_inD, // @[:example.TestHarn... | 7.352624 |
module booth_encoder (
x,
single,
double,
neg,
pzero,
nzero
);
input [2:0] x;
output single;
output double;
output neg;
output pzero;
output nzero;
wire w0;
wire w1;
assign single = x[0] ^ x[1];
assign neg = x[2];
assign w0 = ~(x[1] ^ x[2]);
assign w1 = (x[0] ^ ... | 7.829276 |
module booth_selector (
double,
shifted,
single,
y,
neg,
p
);
input double;
input shifted;
input single;
input y;
input neg;
output p;
assign p = (neg ^ ((y & single) | (shifted & double)));
endmodule
| 7.153136 |
module HALF_ADDER (
a,
b,
sum,
cout
);
input a;
input b;
output sum;
output cout;
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 6.537169 |
module compressor_3_2_group (
in1,
in2,
in3,
s,
c
);
parameter GRP_WIDTH = 32;
input [GRP_WIDTH-1:0] in1, in2, in3;
output [GRP_WIDTH-1:0] s, c;
compressor_3_2 compress[GRP_WIDTH-1:0] (
in1,
in2,
in3,
s,
c
);
endmodule
| 7.237792 |
module compressor_3_2 (
in1,
in2,
in3,
s,
c
);
input in1, in2, in3;
output s, c;
assign c = (in1 & in2) | (in2 & in3) | (in3 & in1);
assign s = (in1 & in2 & in3) | (in1 & ~in2 & ~in3) | (~in1 & in2 & ~in3) | (~in1 & ~in2 & in3);
endmodule
| 7.237792 |
module SynchronizerShiftReg_w1_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201601.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201602.4]
input io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201604.4]
output io_q // @[:example.TestHarnes... | 6.820992 |
module IntSyncCrossingSink ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201617.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201618.4]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201620.4]
output auto_out_0 // @[:example.Test... | 6.689384 |
module IntSyncCrossingSink_1 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201645.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201648.4]
input auto_in_sync_1, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201648.4]
output auto_out_0, // @[:... | 6.689384 |
module IntSyncCrossingSink_2 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201661.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201664.4]
output auto_out_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201664.4]
);
assign auto_out_0 = auto_in_s... | 6.689384 |
module _1_97 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@209347.2]
input [53:0] io_x_ppn, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@209350.4]
input io_x_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@209350.4]
input io_x_a, // @[:example... | 7.048251 |
module AsyncResetRegVec_w2_i0 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221788.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221789.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221790.4]
input [1:0] io_d, // @[:ex... | 6.68936 |
module IntSyncCrossingSource_2( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221803.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221804.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221805.4]
input auto_in_0, // @[:example.TestHarness.... | 6.689384 |
module IntSyncCrossingSource_3( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221844.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221845.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221846.4]
input auto_in_0, // @[:example.TestHarness.... | 6.689384 |
module SynchronizerShiftReg_w2_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@265807.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@265808.4]
input [1:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@265810.4]
output [1:0] io_q // @[:... | 6.820992 |
module current_lap_time_char_rom (
input wire [15:0] char_xy,
input wire [15:0] current_lap_time,
output reg [ 6:0] char_code // pixels of the character line
);
wire [3:0] bcd0, bcd1, bcd2, bcd3, minutes;
bin2bcd(
.bin(current_lap_time), .bcd0(bcd0), .bcd1(bcd1), .bcd2(bcd2), .bcd3(b... | 7.768118 |
module current_location #(
parameter DATA_LENGTH = 6
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATA_LENGTH - 1 : 0] start_location,
input wire [DATA_LENGTH - 1 : 0] next_location,
input wire ... | 7.483318 |
module Current_Loop (
iClk,
iRst_n,
iCL_en,
iSin,
iCos,
iId_set,
iIq_set,
iKp_d,
iKi_d,
iKp_q,
iKi_q,
iADC124_MISO,
oADC124_CS_n,
oADC124_SCLK,
oADC124_MOSI,
oPWM_u,
oPWM_v,
oPWM_w,
oModulate_done
);
input wire iClk;
input wire iRst_n;
in... | 6.65084 |
module current_pc (
input wire clk_i,
input wire rst_i,
input wire [31:0] din_i,
output reg [31:0] pc_o
);
always @(posedge clk_i or posedge rst_i) begin
pc_o <= rst_i ? -32'd4 : din_i;
end
endmodule
| 8.341921 |
module current_score_handler (
current_highscore,
clk,
current_score_update,
startGameEn
);
input startGameEn;
input clk; // default 50mhz clock on de2 board
input current_score_update; // enable signal prompting us to increment the current score
output reg [7:0] current_highscore; // 8 bit r... | 8.876268 |
module will store the current and next current
// values for all neurons. it should support reads
// of I and writes to I_next concurrently
// At the end of a timestep, I_next should be copied
// into I and then I_next should have the decay applied
// support 1 read port of i
// support 1 read port of i_next
// suppor... | 7.109441 |
module cursor #(
parameter ROW_BITS = 5,
parameter COL_BITS = 7
) (
input clk,
input reset,
input tick,
output wire [COL_BITS-1:0] x,
output wire [ROW_BITS-1:0] y,
output wire blink_on,
input [COL_BITS-1:0] new_x,
input [ROW_BITS-1:0] new_y,
input wen
);
cursor_blinker cur... | 8.142139 |
module cursor_blinker (
input clk,
input reset,
input tick,
input reset_count,
output wire blink_on
);
localparam BITS = 6;
reg has_incremented;
reg [BITS-1:0] counter;
always @(posedge clk) begin
if (reset) begin
counter <= 0;
has_incremented <= 0;
end else if (reset_cou... | 6.962427 |
module cursor_check (
input [9:0] x0,
y0,
x,
y,
en,
output check
);
wire [9:0] w1;
wire [9:0] w2;
wire [9:0] w3;
wire [9:0] w4;
wire w5, w6;
wire [9:0] w7;
wire [9:0] w8;
wire w9;
assign w1 = (x0 < 10'b0000001000) ? 10'b0000000000 : x0 - 10'b0000001000;
assign w2 = (y0 < 10... | 6.71439 |
module cursor_logic (
//input
clk,
Xdata,
Ydata,
//output
position
);
input clk;
input [9:0] Xdata;
input [9:0] Ydata;
reg [2:0] Xpos = 1;
reg [2:0] Ypos = 1;
output [3:0] position;
reg [2:0] direction = 0;
`define NEUTRAL 0
`define LEFT 1
`define RIGHT 2
`define UP 3
`d... | 6.514049 |
module: cursor_logic
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cursor_logic_tb;
// Inputs
reg clk;
reg [9:0] Xdata;
reg [9:0] Ydata;
// Outputs
wire [3:0] position;
/... | 7.268971 |
module cursor_pair #(
parameter IMAGE = "XILINX"
) (
input wire [11:0] xidx0,
input wire [11:0] yidx0,
output reg [ 1:0] data0,
output reg mask0,
input wire [11:0] xidx1,
input wire [11:0] yidx1,
output reg [ 1:0] data1,
output reg mask1,
input wire ... | 8.645261 |
module cursor_ram (
doa,
addra,
clka,
rsta
);
output [15:0] doa;
input [8:0] addra;
input clka;
input rsta;
EG_LOGIC_BRAM #(
.DATA_WIDTH_A(16),
.ADDR_WIDTH_A(9),
.DATA_DEPTH_A(384),
.DATA_WIDTH_B(16),
.ADDR_WIDTH_B(9),
.DATA_DEPTH_B(384),
.MODE("... | 6.826776 |
module CurvePeriphTop (
sda_io,
scl_in,
done_int,
clk,
reset
);
// I2C inputs
inout sda_io;
input scl_in;
// done INT output
output done_int;
// TODO: We should actually use a clock generator here, instead of an input clock
input clk;
input reset;
// I2C comment connections
/... | 7.283196 |
module cur_mem (
input clk,
input rst,
input read_en,
output reg [31:0] cur_data
);
reg [ 7:0] cur_mem[0:8300000];
reg [31:0] addr;
initial $readmemh("./data_preprocess/data/cur_processed.txt", cur_mem);
always @(posedge clk) begin
if (rst) addr <= 0;
... | 6.753596 |
module: cursor_ctrl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cur_test;
// Inputs
reg clk;
reg rst;
reg mode;
reg [6:0] win_ctrl_cmd;
reg [7:0] view_width;
// Outputs
... | 7.160526 |
module: cus27
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// License: https://www.apache.org/licenses/LICENSE-2.0
//
////////////////////////////////////////////////////////////////////////////////
module cus27_tb;
// Inputs
reg rst;
reg clk_48m;
// Outpu... | 7.326894 |
module cus35 (
input wire rst_n,
input wire CLK_6M,
input wire nVRES,
input wire nHSYNC,
input wire nOCS,
input wire RnW,
input wire [12:0] A,
inout wire [7:0] D,
output wire O16VA,
output wire O8VA,
output wire O4VA,
output wire O2VA,
output wire O1VA,
output wi... | 7.937111 |
module: cus35
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`include "test_bench/assert.vh"
module cus35_tb;
// Inputs
reg rst;
reg CLK_6M;
reg nVRES;
reg nHSYNC;
reg nOCS;
reg... | 6.817092 |
module cus41 #(
parameter WATCHDOG_WIDTH = 4
) (
input wire rst_n,
input wire [15:11] MA,
input wire nMWE,
input wire nVBLA,
input wire CLK_0,
input wire CLK_1,
input wire CLK_6M,
input wire nSWE,
input wire SA15,
input wire SA14,
input wire SA13,
input wire SA12,
... | 8.023121 |
module cus42 #(
parameter LAYER_A_AUTOSCROLL = 0,
parameter LAYER_B_AUTOSCROLL = 0
) (
input wire rst_n,
input wire CLK_6M,
input wire CLK_2H,
input wire nHSYNC,
input wire nVSYNC,
input wire nGCS,
input wire nRCS,
input wire nLATCH,
input wire FLIP,
input wire [13:0] CA... | 8.327081 |
module cus42_synchronous #(
) (
input wire rst,
input wire CLK_6M,
input wire nHSYNC,
input wire nVSYNC,
output reg [8:0] H,
output reg [8:0] V
);
reg CLK_6M_last;
reg hsyncLast;
reg vsyncLast;
always @(CLK_6M or nHSYNC or nVSYNC or rst) begin
if (rst) begin
H <= 0;
V ... | 7.611397 |
module cus43 #(
parameter LAYER_DISABLE_MASK = 0,
parameter LAYER_A_PRIORITY = 0,
parameter LAYER_B_PRIORITY = 0
) (
input rst_n,
input wire [2:0] PRI,
input wire [7:0] CLI,
input wire [2:0] DTI,
input wire [11:0] GDI,
input wire nOE, // hard to decipher text from schematics (h... | 7.553928 |
module cus43_layer #(
parameter ASSIGNED_LAYER = 0,
parameter LAYER_DISABLE_MASK = 0,
parameter LAYER_PRIORITY = 0
) (
input rst_n,
input wire CLK_6M,
input wire CLK_2H,
input wire [2:0] PRI,
input wire [7:0] CLI,
input wire [2:0] DTI,
input wire [11:0] GDI,
input wire [2:0]... | 7.40893 |
module: TILEGEN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CUS43_tb(
);
// Inputs
reg clk_in;
reg rst;
wire [7:0] R;
wire [7:0] G;
wire [7:0] B;
wire HSYNC;
wire VSYN... | 7.238032 |
module custdesign (
x,
clk,
reset,
y
);
input x, clk, reset;
output y;
wire a, abar, b, bbar, r2, s2;
srff sr1 (
.s(b),
.r(bbar),
.clk(clk),
.reset(reset),
.q(a),
.qbar(abar)
);
assign r2 = a ^ x;
assign s2 = ~r2;
srff sr2 (
.s(s2),
.r(... | 6.656873 |
module: Custom7decoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Custom7decoder_tb;
// Inputs
reg c0;
reg c1;
reg c2;
// Outputs
wire a;
wire b;
wire c;
wire d;
wir... | 7.099555 |
module customcells(
in,
out,
);
input in;
output out;
// Internal wires
wire net1;
//combinatoric
N_customcells #(.Ntimes(123)) some_customcells (.in(in), .out(net1));
assign out = ~net1;
endmodule
| 7.011821 |
module N_customcells #(
parameter Ntimes = 4
) (
in,
out
);
input in;
output out;
wire [Ntimes:1] _intsig_a_;
wire [Ntimes:1] _intsig_b_;
genvar j;
generate
for (j = 1; j <= Ntimes; j = j + 1) begin
sky130_customcell name_of_cell (
.in (_intsig_a_[j]),
.out(_intsig... | 6.616149 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module i_col_counter (
clk,
clear,
rollover_val,
count_enable,
rollover_flag,
value
);
input [12:0] rollover_val;
output [12:0] value;
input clk, clear, count_enable;
output rollover_flag;
flex_counter_NUM_CNT_BITS13_3 colCounter (
.clk(clk),
.n_rst(1'b0),
.clear(cl... | 8.142075 |
module j_row_counter_DW01_dec_0 (
A,
SUM
);
input [12:0] A;
output [12:0] SUM;
wire n1, n3, n5, n7, n9, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27;
INVX2 U1 (
.A(A[10]),
.Y(n1)
);
INVX2 U2 (
.A(n12),
.Y(SUM[9])
);
INVX2 U3 (... | 6.911547 |
module j_row_counter (
clk,
clear,
rollover_val,
count_enable,
rollover_flag,
value
);
input [12:0] rollover_val;
output [12:0] value;
input clk, clear, count_enable;
output rollover_flag;
wire \_0_net_[12] , \_0_net_[11] , \_0_net_[10] , \_0_net_[9] ,
\_0_net_[8] , \_0_net_... | 6.911547 |
module custom_acc_top (
input clk,
input reset,
//input [7:0] i_controle,
//output [7:0] o_controle
input i_start,
output o_finish
);
parameter NUM_CICLOS = 50000000;
reg r_estado;
reg [63:0] r_contador;
wire w_start;
reg r_finish;
assign w_start = i_start;
assign o_finish ... | 6.520119 |
module custom_apb_button #(
parameter ADDRWIDTH = 12
) (
//SYSTEM
input wire pclk,
input wire presetn,
//APB
input wire psel,
input wire [ADDRWIDTH-1:0] paddr,
input wire penable,
input wire pwrite,
input wire [ 31:0]... | 8.286603 |
module custom_apb_led (
//led core ports
input wire clk,
input wire rst,
input wire [31:0] ledNumIn,
output reg [ 3:0] ledNumOut // When high, the LED on board turns off
);
always @(posedge clk or negedge rst) begin
if (~rst) ledNumOut <= 4'b1111;
else if (ledNumIn >= 4... | 8.09291 |
module custom_apb_timer #(
parameter ADDRWIDTH = 12,
parameter CLK_FREQ = 32'd50000000
) (
//SYSTEM
input wire pclk,
input wire presetn,
output reg [ 31:0] cp_timerCnt, // ckp
input ui_clk,
output reg [ 31:0] ui_cnt,
//APB
input wire ... | 8.479344 |
module BUF (
A,
Y
);
input A;
output Y;
assign Y = A;
endmodule
| 7.249964 |
module NOT (
A,
Y
);
input A;
output Y;
assign Y = ~A;
endmodule
| 7.213424 |
module NAND (
A,
B,
Y
);
input A, B;
output Y;
assign Y = ~(A & B);
endmodule
| 8.177563 |
module AND (
A,
B,
Y
);
input A, B;
output Y;
assign Y = (A & B);
endmodule
| 7.482495 |
module NOR (
A,
B,
Y
);
input A, B;
output Y;
assign Y = ~(A | B);
endmodule
| 8.177256 |
module OR (
A,
B,
Y
);
input A, B;
output Y;
assign Y = (A | B);
endmodule
| 7.211786 |
module XOR (
A,
B,
Y
);
input A, B;
output Y;
assign Y = (A ^ B);
endmodule
| 7.868477 |
module XNOR (
A,
B,
Y
);
input A, B;
output Y;
assign Y = ~(A ^ B);
endmodule
| 7.729097 |
module DFF (
C,
D,
Q
);
input C, D;
output reg Q;
always @(posedge C) Q <= D;
endmodule
| 7.813248 |
module cmp19_e (
ai,
bi,
a_eql_b
);
input [18:0] ai;
input [18:0] bi;
output a_eql_b; // ai equal to bi.
/* Logic
assign a_eql_b = ( ai[18:0] == bi[18:0] ) ;
*/
/*Use this portion for RTL simulation.*/
wire [18:0] bit_eql; // bit-wise equal output
wire [ 4:0] level_1; // 8-equal_not ou... | 6.979534 |
module cmp20_e (
ai,
bi,
a_eql_b
);
input [19:0] ai;
input [19:0] bi;
output a_eql_b; // ai equal to bi.
/* Logic
assign a_eql_b = ( ai[19:0] == bi[19:0] ) ;
*/
/*Use this portion for RTL simulation.*/
wire [19:0] bit_eql; // bit-wise equal output
wire [ 4:0] level_1; // 8-equal_not out... | 6.642886 |
module sum2_fa6 (
g1,
g2,
p0,
p1,
p2,
sum1a,
sum2a,
sum1b,
sum2b
);
output sum1a, sum2a, sum1b, sum2b; // sum outputs.
input g1, g2; // individual generate inputs.
input p0, p1, p2; // individual propagate inputs.
//input G; // global carry input. (pseudo-g... | 6.937688 |
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