code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module pgnx_fa6 (
a,
b,
g_l,
p_l
); // level 1 propagate and generate signals
input a, b;
output g_l, p_l;
assign g_l = !(a & b); //nand to make initial generate
assign p_l = !(a | b); //nor to make initial propagate
endmodule
| 6.779864 |
module pg2l_fa6 (
gd_l,
gu_l,
pd_l,
pu_l,
g,
p
);
input gd_l, gu_l, pd_l, pu_l;
output g, p;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
assign p = !(pd_l | pu_l); //nor to make pseudo generate
endmodule
| 6.958323 |
module aoig_fa6 (
gd,
gu,
pu,
g_l
);
input gd, gu, pu;
output g_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
endmodule
| 7.518988 |
module oaig_fa6 (
gd_l,
gu_l,
pu_l,
g
);
input gd_l, gu_l, pu_l;
output g;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
endmodule
| 6.517598 |
module baoi_fa6 (
gd,
gu,
pd,
pu,
g_l,
p_l
);
input gd, gu, pd, pu;
output g_l, p_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
assign p_l = ~(pd & pu); // nand to make group prop
endmodule
| 8.057739 |
module gr6 (
a,
b,
gr
);
input [5:0] a;
input [5:0] b;
output gr; // carry out
// -------------------- carry tree level 1 ----------------------------
// produce the generate for the least significant bit (sch: glsbs)
wire g0_l = !((a[0] & b[0]));
// produce the propagates and generates ... | 6.635208 |
module pgnx_gr6 (
a,
b,
g_l,
p_l
); // level 1 propagate and generate signals
input a, b;
output g_l, p_l;
assign g_l = !(a & b); //nand to make initial generate
assign p_l = !(a | b); //nor to make initial propagate
endmodule
| 7.091515 |
module pg2l_gr6 (
gd_l,
gu_l,
pd_l,
pu_l,
g,
p
);
input gd_l, gu_l, pd_l, pu_l;
output g, p;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
assign p = !(pd_l | pu_l); //nor to make pseudo generate
endmodule
| 6.995019 |
module aoig_gr6 (
gd,
gu,
pu,
g_l
);
input gd, gu, pu;
output g_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
endmodule
| 7.335908 |
module baoi_gr6 (
gd,
gu,
pd,
pu,
g_l,
p_l
);
input gd, gu, pd, pu;
output g_l, p_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
assign p_l = ~(pd & pu); // nand to make group prop
endmodule
| 7.934726 |
module cmp32zero (
ai,
a_eql_z
);
input [31:0] ai;
output a_eql_z; // ai equal to all_zero.
/* Logic
assign a_eql_z = ( ai[31:0] == 32'b0 ) ;
*/
/* Use this portion for RTL simulation.*/
wire [31:0] bit_eql; // bit-wise equal output
wire [ 7:0] level_1; // 8-equal_not output
wire [ 3:0] lev... | 7.986344 |
module prop0_inc32 (
p2grp_l,
ain
);
output p2grp_l;
input [1:0] ain;
assign p2grp_l = !(ain[1] & ain[0]);
endmodule
| 6.69433 |
module prop1_inc32 (
pgrp,
pu_in,
pd_in
);
output pgrp;
input pu_in, pd_in;
assign pgrp = !(pu_in | pd_in);
endmodule
| 6.662637 |
module gen1_inc32 (
ggrp,
pu_in,
gd_in
);
output ggrp;
input pu_in, gd_in;
assign ggrp = !(pu_in | gd_in);
endmodule
| 6.621642 |
module prop2_inc32 (
pgrp_l,
pu_in,
pd_in
);
output pgrp_l;
input pu_in, pd_in;
assign pgrp_l = !(pu_in & pd_in);
endmodule
| 7.299844 |
module gen2_inc32 (
ggrp_l,
pu_in,
gd_in
);
output ggrp_l;
input pu_in, gd_in;
assign ggrp_l = !(pu_in & gd_in);
endmodule
| 6.953452 |
module prop3_inc32 (
pgrp,
pu_in,
pd_in
);
output pgrp;
input pu_in, pd_in;
assign pgrp = !(pu_in | pd_in);
endmodule
| 6.609195 |
module gen4_inc32 (
ggrp_l,
pu_in,
gd_in
);
output ggrp_l;
input pu_in, gd_in;
assign ggrp_l = !(pu_in & gd_in);
endmodule
| 6.675676 |
module sum4s_i32 (
csel,
sin1,
sin2,
sin3,
sin4,
sin1b,
sin2b,
sin3b,
sin4b,
sum1,
sum2,
sum3,
sum4
);
output sum1, sum2, sum3, sum4; // sum outputs.
input sin1, sin2, sin3, sin4; // sel inputs assuming csel=1
input sin1b, sin2b, sin3b, sin4b; // sel_l input... | 7.725746 |
module presum_i32 (
p0,
p1,
p2,
p3,
p4,
s1,
s2,
s3,
s4,
s1b,
s2b,
s3b,
s4b
);
input p0, p1, p2, p3, p4;
output s1, s2, s3, s4;
output s1b, s2b, s3b, s4b;
assign s1b = p1;
assign s2b = p2;
assign s3b = p3;
assign s4b = p4;
assign s1 = p1 ^ p0;
assi... | 7.056604 |
module sum4s_fa32 (
csel,
sin1,
sin2,
sin3,
sin4,
sin1b,
sin2b,
sin3b,
sin4b,
sum1,
sum2,
sum3,
sum4
);
output sum1, sum2, sum3, sum4; // sum outputs.
input sin1, sin2, sin3, sin4; // sel inputs assuming csel=1
input sin1b, sin2b, sin3b, sin4b; // sel_l inpu... | 7.84328 |
module sum4_fa16 (
g1,
g2,
g3,
g4,
p0,
p1,
p2,
p3,
p4,
sum1a,
sum2a,
sum3a,
sum4a,
sum1b,
sum2b,
sum3b,
sum4b
);
output sum1a, sum2a, sum3a, sum4a, sum1b, sum2b, sum3b, sum4b; // sum outputs.
input g1, g2, g3, g4; // individual generate inputs.
... | 6.939408 |
module pgnx_fa16 (
a,
b,
g_l,
p_l
); // level 1 propagate and generate signals
input a, b;
output g_l, p_l;
assign g_l = !(a & b); //nand to make 2bit pseudo generate
assign p_l = !(a | b); //nor to make 2bit pseudo propagate
endmodule
| 7.210353 |
module pg2lg_fa16 (
gd_l,
gu_l,
g
);
input gd_l, gu_l;
output g;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
endmodule
| 6.818715 |
module pg2l_fa16 (
gd_l,
gu_l,
pd_l,
pu_l,
g,
p
);
input gd_l, gu_l, pd_l, pu_l;
output g, p;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
assign p = !(pd_l | pu_l); //nor to make pseudo generate
endmodule
| 7.433245 |
module aoig_fa16 (
gd,
gu,
pu,
g_l
);
input gd, gu, pu;
output g_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
endmodule
| 7.594368 |
module oaig_fa16 (
gd_l,
gu_l,
pu_l,
g
);
input gd_l, gu_l, pu_l;
output g;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
endmodule
| 6.78996 |
module baoi_fa16 (
gd,
gu,
pd,
pu,
g_l,
p_l
);
input gd, gu, pd, pu;
output g_l, p_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
assign p_l = ~(pd & pu); // nand to make group prop
endmodule
| 8.47096 |
module boai_fa16 (
gd_l,
gu_l,
pd_l,
pu_l,
g,
p
);
input gd_l, gu_l, pu_l, pd_l;
output g, p;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
assign p = ~(pu_l | pd_l); // nor to make group prop
endmodule
| 7.298522 |
module cmp16_e (
ai,
bi,
a_eql_b
);
input [15:0] ai;
input [15:0] bi;
output a_eql_b; // ai equal to bi.
/* Logic
assign a_eql_b = ( ai[15:0] == bi[15:0] ) ;
*/
wire [15:0] ben; // bit-wise equal_not output
wire [ 7:0] lv1; // 8-equal output
wire [ 3:0] lv2; // 4-equal_not output... | 7.108282 |
module cmp16zero (
ai,
a_eql_z
);
input [15:0] ai;
output a_eql_z; // ai equal to all_zero.
/* Logic
assign a_eql_z = ( ai[15:0] == 16'b0 ) ;
*/
/*Behaviral model's performence is at 1.28 ns.*/
wire [15:0] bit_eql; // bit-wise equal output
wire [ 3:0] level_1; // 8-equal_not output
wire [ ... | 7.627721 |
module lbd32 (
zr_num,
di
);
output [5:0] zr_num;
input [31:0] di;
reg [3:0] b3_num, b2_num, b1_num, b0_num;
reg w5, w4, w3, w2, w1, w0;
/* Logic */
always @(di) begin
casex (di[31:24]) //synopsys parallel_case
8'b00000000: b3_num = 4'b1000; // 8 zeros
8'b00000001: b3_num = 4'b0... | 6.70768 |
module sum4s_fa28 (
csel,
sin1,
sin2,
sin3,
sin4,
sin1b,
sin2b,
sin3b,
sin4b,
sum1,
sum2,
sum3,
sum4
);
output sum1, sum2, sum3, sum4; // sum outputs.
input sin1, sin2, sin3, sin4; // sel inputs assuming csel=1
input sin1b, sin2b, sin3b, sin4b; // sel_l inpu... | 7.429987 |
module lsft31_63i_32o (
lsf_out,
hi,
lo,
lsa
);
output [31:0] lsf_out;
input [31:0] hi;
input [31:1] lo;
input [4:0] lsa;
/* Logic
assign lsf[62:0] = {hi[31:0],lo[31:1]} << lsa[4:0] ;
assign lsf_out[31:0] = lsf[62:31];
*/
// The following module has indentical functionality as above assig... | 6.617182 |
module rsft31_63i_32o (
rsf_out,
gbit,
sticky,
nxstin,
hi,
lo,
rsa,
stin
);
output [31:0] rsf_out;
output gbit; // 1 bit below LSB of result.
output sticky; // 2-bit below LSB
output nxstin; // Or of GBIT and STICKY
input [30:0] hi;
input [31:0] lo;
input [4:0] rsa;
... | 8.150048 |
module pg4bt_lt32 (
gs_3_0,
ps_2_n1,
g_in,
p_in,
pn_3
);
output gs_3_0; // carry_generated.
output ps_2_n1; // carry_propgated. lower 1-bit
input [3:0] g_in; // generate inputs.
input [2:0] p_in; // propgate inputs. lower 1-bit
input pn_3; // next lower bit prop input.
/* or use t... | 6.88638 |
module contains the 32-bit comparator that can handle both signed
* and unsigned comparisons.
*
******************************************************************************/
module cmp_legs_32(gt,
eq,
lt,
in1,
in2,
sign);
input [31:0] in1; // Operand on the LHS to be compare... | 7.358377 |
module mx21_64_l (
mx_out,
sel,
in0,
in1
);
output [63:0] mx_out;
input sel;
input [63:0] in0, in1;
wire [63:0] sel_not, mux_sel;
assign sel_not = {64{~sel}};
assign mux_sel = {64{sel}};
assign mx_out = ~(mux_sel & in1 | sel_not & in0);
endmodule
| 7.609952 |
module sum2_fa8 (
g1,
g2,
p0,
p1,
p2,
sum1a,
sum2a,
sum1b,
sum2b
);
output sum1a, sum2a, sum1b, sum2b; // sum outputs.
input g1, g2; // individual generate inputs.
input p0, p1, p2; // individual propagate inputs.
//input G; // global carry input. (pseudo-g... | 7.035706 |
module pgnx_fa8 (
a,
b,
g_l,
p_l
); // level 1 propagate and generate signals
input a, b;
output g_l, p_l;
assign g_l = !(a & b); //nand to make initial generate
assign p_l = !(a | b); //nor to make initial propagate
endmodule
| 7.663914 |
module pg2lg_fa8 (
gd_l,
gu_l,
g
);
input gd_l, gu_l;
output g;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
endmodule
| 6.98723 |
module pg2l_fa8 (
gd_l,
gu_l,
pd_l,
pu_l,
g,
p
);
input gd_l, gu_l, pd_l, pu_l;
output g, p;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
assign p = !(pd_l | pu_l); //nor to make pseudo generate
endmodule
| 7.78818 |
module aoig_fa8 (
gd,
gu,
pu,
g_l
);
input gd, gu, pu;
output g_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
endmodule
| 7.933364 |
module oaig_fa8 (
gd_l,
gu_l,
pu_l,
g
);
input gd_l, gu_l, pu_l;
output g;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
endmodule
| 6.881815 |
module baoi_fa8 (
gd,
gu,
pd,
pu,
g_l,
p_l
);
input gd, gu, pd, pu;
output g_l, p_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
assign p_l = ~(pd & pu); // nand to make group prop
endmodule
| 8.565398 |
module sum2_fa10 (
g1,
g2,
p0,
p1,
p2,
sum1a,
sum2a,
sum1b,
sum2b
);
output sum1a, sum2a, sum1b, sum2b; // sum outputs.
input g1, g2; // individual generate inputs.
input p0, p1, p2; // individual propagate inputs.
//input G; // global carry input. (pseudo-... | 7.061423 |
module pgnx_fa10 (
a,
b,
g_l,
p_l
); // level 1 propagate and generate signals
input a, b;
output g_l, p_l;
assign g_l = !(a & b); //nand to make initial generate
assign p_l = !(a | b); //nor to make initial propagate
endmodule
| 6.901382 |
module pg2lg_fa10 (
gd_l,
gu_l,
g
);
input gd_l, gu_l;
output g;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
endmodule
| 6.691843 |
module pg2l_fa10 (
gd_l,
gu_l,
pd_l,
pu_l,
g,
p
);
input gd_l, gu_l, pd_l, pu_l;
output g, p;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
assign p = !(pd_l | pu_l); //nor to make pseudo generate
endmodule
| 7.483338 |
module aoig_fa10 (
gd,
gu,
pu,
g_l
);
input gd, gu, pu;
output g_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
endmodule
| 7.510002 |
module oaig_fa10 (
gd_l,
gu_l,
pu_l,
g
);
input gd_l, gu_l, pu_l;
output g;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
endmodule
| 6.621634 |
module baoi_fa10 (
gd,
gu,
pd,
pu,
g_l,
p_l
);
input gd, gu, pd, pu;
output g_l, p_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
assign p_l = ~(pd & pu); // nand to make group prop
endmodule
| 8.038303 |
module boai_fa10 (
gd_l,
gu_l,
pd_l,
pu_l,
g,
p
);
input gd_l, gu_l, pu_l, pd_l;
output g, p;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
assign p = ~(pu_l | pd_l); // nor to make group prop
endmodule
| 7.048729 |
module mj_s_dcd8to256 (
data,
decodeout
);
input [7:0] data;
output [255:0] decodeout;
wire [15:0] sel, bottom;
wire [255:0] decodeout_l;
// decode top order bits
wire [ 7:0] data_l = ~data;
mj_s_dcd4to16 decodeupper (
.data(data[7:4]),
.data_l(data_l[7:4]),
.decodeout_l(s... | 6.690641 |
module mj_s_dcd4to16 (
data,
data_l,
decodeout_l
);
input [3:0] data, data_l;
output [15:0] decodeout_l;
wire [3:0] sel, bottom;
//wire [15:0] decodeout_l;
// decode top order bits
decode2to4 decodeupper (
.datain (data[3:2]),
.datain_l(data_l[3:2]),
.dataout (sel[3:0])
... | 7.483331 |
module finalsel4 (
sel,
data,
out
);
input sel;
input [3:0] data;
output [3:0] out;
assign out[3] = ~(data[3] & sel);
assign out[2] = ~(data[2] & sel);
assign out[1] = ~(data[1] & sel);
assign out[0] = ~(data[0] & sel);
endmodule
| 6.73016 |
module fram32_8 (
clk,
write_n, // Write enable
write_ptr, // Write Address
read_ptr, // Read Address
data_in, // Write Data
data_out // Read Data
);
parameter f_width = 32, //fifo data with
p_width = 3, //fifo pointer with
f_depth = 8; //fifo data depth
input clk;
input write... | 7.439565 |
module fram37_8 (
clk,
write_n, // Write enable
write_ptr, // Write Address
read_ptr, // Read Address
data_in, // Write Data
data_out // Read Data
);
parameter f_width = 37, //fifo data with
p_width = 3, //fifo pointer with
f_depth = 8; //fifo data depth
input clk;
input write... | 7.038903 |
module fram48_8 (
clk,
write_n, // Write enable
write_ptr, // Write Address
read_ptr, // Read Address
data_in, // Write Data
data_out // Read Data
);
parameter f_width = 48, //fifo data with
p_width = 3, //fifo pointer with
f_depth = 8; //fifo data depth
input clk;
input write... | 7.040736 |
module fram58_4 (
clk,
write_n, // Write enable
write_ptr, // Write Address
read_ptr, // Read Address
data_in, // Write Data
data_out // Read Data
);
parameter f_width = 58, //fifo data with
p_width = 2, //fifo pointer with
f_depth = 4; //fifo data depth
input clk;
input write_... | 7.020215 |
module g2_dec32 (
ggrp,
gu_in,
gd_in
);
output ggrp; // group generate.
input gu_in; // upper generate input.
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp = ~(gu_in & gd_in); // group generate.
endmodule
| 6.685309 |
module sum4s_dec32 (
csel,
sin1,
sin2,
sin3,
sin4,
sin1b,
sin2b,
sin3b,
sin4b,
sum1,
sum2,
sum3,
sum4
);
output sum1, sum2, sum3, sum4; // sum outputs.
input sin1, sin2, sin3, sin4; // sel inputs assuming csel=1
input sin1b, sin2b, sin3b, sin4b; // sel_l inp... | 7.447527 |
module lev2and (
in1,
in2,
out
);
input in1, in2;
output out;
wire out;
assign out = ~(in1 | in2);
endmodule
| 7.917482 |
module local3_inc10 (
in1,
in2,
in3,
out1a,
out2a,
out3a
);
input in1, in2, in3;
output out1a, out2a, out3a;
wire out1a, out2a, out3a;
assign out1a = ~in1;
assign out2a = in1 ^ in2;
assign out3a = (in1 & in2) ^ in3;
endmodule
| 6.899324 |
module local4_inc10 (
in1,
in2,
in3,
in4,
out1a,
out2a,
out3a,
out4a
);
input in1, in2, in3, in4;
output out1a, out2a, out3a, out4a;
wire out1a, out2a, out3a, out4a;
assign out1a = ~in1;
assign out2a = in1 ^ in2;
assign out3a = (in1 & in2) ^ in3;
assign out4a = (in1 & in... | 6.820111 |
module mj_s_or7 (
in,
out
);
input [6:0] in;
output out;
assign out = |in[6:0];
endmodule
| 6.602289 |
module mj_s_or5 (
in,
out
);
input [4:0] in;
output out;
assign out = |in[4:0];
endmodule
| 7.26204 |
module mj_s_or12 (
in,
out
);
input [11:0] in;
output out;
assign out = |in[11:0];
endmodule
| 7.183317 |
module mj_s_and6 (
in,
out
);
input [5:0] in;
output out;
assign out = &in[5:0];
endmodule
| 7.77314 |
module cmp30_e (
ai,
bi,
a_eql_b
);
input [29:0] ai;
input [29:0] bi;
output a_eql_b; // ai equal to bi.
assign a_eql_b = (ai[29:0] == bi[29:0]);
endmodule
| 6.632804 |
module cmp32_e (
ai,
bi,
a_eql_b
);
input [31:0] ai;
input [31:0] bi;
output a_eql_b; // ai equal to bi.
/* Logic
assign a_eql_b = ( ai[31:0] == bi[31:0] ) ;
*/
wire [31:0] bit_eql; // bit-wise equal output
wire [ 7:0] level_1; // 8-equal_not output
wire [ 3:0] level_2; // 4-equal
as... | 6.722144 |
module comp_ge_8 (
in1,
in2,
ge
);
input [7:0] in1;
input [7:0] in2;
output ge;
assign ge = (in1 >= in2);
endmodule
| 6.803477 |
module cla_adder_32 (
in1,
in2,
cin,
sum,
cout
);
input [31:0] in1;
input [31:0] in2;
input cin;
output [31:0] sum;
output cout;
/*assign {cout,sum} = in1 + in2 + cin;*/
fa32 i_fa32 (
.ai (in1),
.bi (in2),
.cin (cin),
.sum (sum),
.cout(cout)
);
e... | 6.67347 |
module local3_inc23 (
in1,
in2,
in3,
out1a,
out2a,
out3a
);
input in1, in2, in3;
output out1a, out2a, out3a;
wire out1a, out2a, out3a;
assign out1a = ~in1;
assign out2a = in1 ^ in2;
assign out3a = (in1 & in2) ^ in3;
endmodule
| 6.692739 |
module local4_inc23 (
in1,
in2,
in3,
in4,
out1a,
out2a,
out3a,
out4a
);
input in1, in2, in3, in4;
output out1a, out2a, out3a, out4a;
wire out1a, out2a, out3a, out4a;
assign out1a = ~in1;
assign out2a = in1 ^ in2;
assign out3a = (in1 & in2) ^ in3;
assign out4a = (in1 & in... | 6.869436 |
module comp_gr_6 (
in1,
in2,
gr
);
input [5:0] in1;
input [5:0] in2;
output gr;
wire [5:0] in2_l;
/*assign gr = (in1 > in2);*/
gr6 i_gr6 (
.gr(gr),
.a (in1),
.b (in2_l)
);
assign in2_l = ~in2;
endmodule
| 6.924398 |
module cla_adder_6 (
in1,
in2,
cin,
sum,
cout
);
input [5:0] in1;
input [5:0] in2;
input cin;
output [5:0] sum;
output cout;
/*assign {cout,sum} = in1 + in2 + cin;*/
fa6 i_fa6 (
.sum(sum),
.cout(cout),
.a(in1),
.b(in2),
.c(cin)
);
endmodule
| 6.579697 |
module incr_32 (
in,
out
);
input [31:0] in;
output [31:0] out;
/* assign out = in + 1; */
inc32 i_incr_32 (
.ai (in),
.sum(out)
);
endmodule
| 7.653026 |
module dec_32 (
in,
out
);
input [31:0] in;
output [31:0] out;
/* assign out = in - 1; */
dec32 i_dec_32 (
.ai (in),
.sum(out)
);
endmodule
| 7.298341 |
module contains the 32-bit comparator that can handle both signed
* and unsigned comparisons.
*
******************************************************************************/
module cmp_32(in1,
in2,
sign,
gt,
eq,
lt);
input [31:0] in... | 7.358377 |
module implements 19-bit equality comparator
*
******************************************************************************/
module cmp_eq_19(in1,
in2,
eq
);
input [18:0] in1; // Operand 1 to be compared
input [18:0] in2; // Operand 2 t... | 6.810121 |
module implements unsigned 16-bit comparator with gt, eq, and lt outputs
*
******************************************************************************/
module ucmp_16(in1,
in2,
gt,
eq,
lt);
input [15:0] in1; // Operand 1 to be compared
... | 6.792637 |
module implements 8-bit equality comparator
*
******************************************************************************/
module cmp_eq_8(in1,
in2,
eq
);
input [7:0] in1; // Operand 1 to be compared
input [7:0] in2; // Operand 2 to be ... | 6.826105 |
module implements an 8-bit adder
*
******************************************************************************/
module cla_adder_8(in1,
in2,
cin,
sum,
cout
);
input [7:0] in1;
input [7:0] in2;
input c... | 6.667836 |
module mx21_32_l (
mx_out,
sel,
in0,
in1
);
output [31:0] mx_out;
input sel;
input [31:0] in0, in1;
wire [31:0] sel_not, mux_sel;
assign sel_not = {32{~sel}};
assign mux_sel = {32{sel}};
assign mx_out = ~(mux_sel & in1 | sel_not & in0);
endmodule
| 8.204888 |
module compare_lt_32 (
out,
in0,
in1
);
input [31:0] in0, in1;
output out;
/* assign out = (in0 < in1) ? 1'h1 : 1'h0; */
cmp32_ks_lt i_compare_lt_32 (
.ai(in0),
.bi(in1),
.a_ltn_b(out)
);
endmodule
| 7.224582 |
module pri_encode (
out,
in
);
// Leading zero output: if all 32 bits are zero output 32.
input [31:0] in;
output [5:0] out;
lbd32 f_dpcl_lbd32 (
.zr_num(out),
.di(in)
);
endmodule
| 7.569994 |
module rshifter (
rshiftout,
high,
low,
stin,
sticky,
saout
);
input [31:0] low;
input [30:0] high;
input stin; // Input from prevoius STICKY
input [4:0] saout; // Shift Amount.
output [31:0] rshiftout;
output sticky; // Or of all bits below the GBIT.
rsft31_63i_32o fpu_dp_ce... | 6.958892 |
module lshift (
out,
high,
low,
shifta
);
// performs the 32-bit Left Shift.
input [31:0] high;
input [30:0] low; // high 31 bits of the m0out bus.
input [4:0] shifta;
output [31:0] out;
lsft31_63i_32o f_dpcl_lshift (
.lsf_out(out),
.hi(high),
.lo(low),
.lsa(shifta... | 7.328798 |
module compare_zero_32 (
out,
in
);
// Performs an EQUALITY comparision to zero:
input [31:0] in;
output out;
cmp32zero f_dpcl_cmp32zero (
.a_eql_z(out),
.ai(in)
);
endmodule
| 7.682988 |
module encoder16 (
ptrap_in_e,
trap_vec_e
);
output [15:0] ptrap_in_e;
input [15:0] trap_vec_e;
wire [3:0] ptrap_in_e1, ptrap_in_e2;
wire [3:0] ptrap_in_e3;
wire [3:0] ptrap_in_e0;
wire e2, e1, e0;
wire c2, c1;
/*always @(trap_vec_e[15:0]) begin
casex (trap_vec_e[15:0])
16'b1xxxxxxxxxxxx... | 7.892662 |
module trp (
ptrap_in,
trap_v
);
output [3:0] ptrap_in;
input [3:0] trap_v;
reg [3:0] ptrap_in;
always @(trap_v) begin
casex (trap_v[3:0])
4'b1xxx: ptrap_in = 4'h8;
4'b01xx: ptrap_in = 4'h4;
4'b001x: ptrap_in = 4'h2;
4'b0001: ptrap_in = 4'h1;
default: ptrap_in = 4'h0;
... | 6.714965 |
module buf_64 (
out,
in
);
output [63:0] out;
input [63:0] in;
assign out = in;
endmodule
| 6.826302 |
module multha (
ai,
bi,
so,
co
);
input ai, bi;
output so, co;
assign {co, so} = ai + bi;
endmodule
| 7.277323 |
module adder_33 (
op_a,
op_b,
cin,
sum,
cout
);
input [32:0] op_a;
input [32:0] op_b;
input cin;
output [32:0] sum;
output cout;
wire [32:0] sum;
assign {cout, sum} = op_a + op_b + cin;
endmodule
| 6.925439 |
module incre_32 (
inp,
out
);
input [31:0] inp;
output [31:0] out;
wire [31:0] out;
assign out = inp + 1;
endmodule
| 6.756868 |
module inc16 (
ai,
sum
);
input [15:0] ai;
output [15:0] sum;
assign sum[15:0] = ai[15:0] + 1'b1;
endmodule
| 6.808609 |
module fa9 (
a,
b,
c,
sum,
cout
);
input [8:0] a;
input [8:0] b;
output [8:0] sum;
input c; // carry in
output cout; // carry out
assign {cout, sum} = a + b + c;
endmodule
| 6.898539 |
module buf10_drv_32 (
in,
out
);
input [31:0] in;
output [31:0] out;
assign out = in;
endmodule
| 7.438408 |
module inv10_drv_32 (
in,
out
);
input [31:0] in;
output [31:0] out;
assign out = ~in;
endmodule
| 8.509307 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.