code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module inv4_drv_32 (
in,
out
);
input [31:0] in;
output [31:0] out;
assign out = ~in;
endmodule
| 8.977076 |
module effects the IO of the DDC chain.
//By default, this entire module is a simple pass-through.
//To implement DSP logic before the DDC:
//Implement custom DSP between frontend and ddc input.
//To implement DSP logic after the DDC:
//Implement custom DSP between ddc output and baseband.
//To bypass the DDC with c... | 7.900239 |
module effects the IO of the DUC chain.
//By default, this entire module is a simple pass-through.
//To implement DSP logic before the DUC:
//Implement custom DSP between baseband and duc input.
//To implement DSP logic after the DUC:
//Implement custom DSP between duc output and frontend.
//To bypass the DUC with c... | 7.900239 |
module is used to re-write receive packets to the host.
//This module provides a packet-based ram interface for manipulating packets.
//The user writes a custom engine (state machine) to read the input packet,
//and to produce a new output packet.
//By default, this entire module is a simple pass-through.
module cust... | 9.406588 |
module is used to re-write transmit packets from the host.
//This module provides a packet-based ram interface for manipulating packets.
//The user writes a custom engine (state machine) to read the input packet,
//and to produce a new output packet.
//By default, this entire module is a simple pass-through.
module c... | 9.406588 |
module custom_lkh_routing #(
parameter TOPOLOGY = "CUSTOM_NAME",
parameter ROUTE_NAME = "CUSTOM_NAME",
parameter ROUTE_TYPE = "DETERMINISTIC",
parameter RAw = 3,
parameter EAw = 3,
parameter DSTPw = 4
) (
current_r_addr,
dest_e_addr,
src_e_addr,
destport,
reset,
clk
);
... | 7.376651 |
module timers (
clk,
n_rst,
shift_in_ena,
shift_out_ena,
iteration_ena,
samples_in_count,
samples_loaded_count,
samples_in_done,
samples_out_done,
fft_done,
iteration_count,
stage_count,
samples_out_count,
samples_written_count,
iteration_done,
samples_loa... | 6.843997 |
module custom_ni_routing #(
parameter NOC_ID = 0,
parameter TOPOLOGY = "CUSTOM_NAME",
parameter ROUTE_NAME = "CUSTOM_NAME",
parameter ROUTE_TYPE = "DETERMINISTIC",
parameter RAw = 4,
parameter EAw = 4,
parameter DSTPw = 4
) (
dest_e_addr,
src_e_addr,
destport
);
input [EAw-1 :... | 7.050729 |
module Custom_XOR (
out,
a,
b
);
input a, b;
output out;
wire w0, w1, w2, w3, w4, w5, w6;
and and0 (w0, a, b);
and and1 (w2, w1, a);
and and2 (w3, w1, b);
and and3 (w6, w4, w5);
not not0 (w1, w0);
not not1 (w4, w2);
not not2 (w5, w3);
not not3 (out, w6);
endmodule
| 7.853034 |
module cutDMEMtoRf (
input [2:0] width_sign,
input [1:0] pos,
input sign,
input [31:0] Dmem_data,
output reg [31:0] Rf_data
);
always @(*) begin
if (width_sign == 3'b001) begin
Rf_data <= Dmem_data;
end else if (width_sign == 3'b010) begin
if (pos == 2'b00) begin
Rf_da... | 7.356244 |
module: CU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cutest;
// Inputs
reg [5:0] opcode;
reg [10:0] ALUfunc;
reg clk;
reg reset;
reg equal;
// Outputs
wire pc_enable;... | 6.786456 |
module cutRftoDMEM (
input [2:0] width_sign,
input [1:0] pos,
input sign,
input [31:0] Rf_data,
input [31:0] dmem_idata,
output reg [31:0] dmem_odata
);
always @(*) begin
if (width_sign == 3'b001) begin
dmem_odata <= Rf_data;
end else if (width_sign == 3'b010) begin
if (po... | 8.091968 |
module cutter (
input [31:0] data_in,
input [2:0] sel,
input sign,
output [31:0] data_out
);
reg [31:0] temp;
always @(*) begin
case (sel)
3'b001: temp <= {(sign && data_in[15]) ? 16'hffff : 16'h0000, data_in[15:0]};
3'b010: temp <= {(sign && data_in[7]) ? 24'hffffff : 24'h000000... | 7.99217 |
module cut_packet_hls_deadlock_idx0_monitor ( // for module cut_packet_cut_packet_inst
input wire clock,
input wire reset,
input wire [1:0] axis_block_sigs,
input wire [0:0] inst_idle_sigs,
input wire [0:0] inst_block_sigs,
output wire block
);
// signal declare
reg monitor_find_block;
... | 6.970023 |
module cut_packet_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire ... | 6.670087 |
module cut_packet_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
re... | 6.670087 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/cu_comb/cu_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad,
o_pad,
p_pad,
q_pad,
r_pad,
s_pad,
t... | 6.939825 |
module CU_DP (
input [7:0] in,
input clk,
input rst,
input start,
output [63:0] out,
output [6:0] cs,
output done
);
wire ren, shift, wen, rstreg, rst2;
wire [1:0] sel1, wa, ra1, ra2;
wire [2:0] sel2;
CU u0 (
.rst1(rst),
.start(start),
.clk(clk),
.rst2(rst2)... | 7.081863 |
module CU_fft_controller (
input clock,
input reset,
input ready,
input e_done_fft_core,
input dv_fft_core,
input tc_counter,
output reg sclr_fft_core,
output reg scale_sch_we_fft_core,
output reg start_fft_core,
output reg unload_fft_core,
outpu... | 8.12147 |
module CU (
input clk,
input [31:0] insn, // Instrução
input LU,
LS,
EQ, // Sinais resultados de comparações da ALU
output addr_sel,
alu_sel_a,
alu_sel_b,
pc_next_sel,
pc_alu_sel, // Seletores, sinais que selecionam saídas de multiplexadores
output rd_clk,
mem_clk,
... | 6.860738 |
module cu_mux (
input [4:0] opCode,
input selector,
output [4:0] out
);
assign out = selector == 0 ? opCode : 5'b0;
endmodule
| 8.40431 |
module CU_ram_wr_controller (
input clock,
input reset,
input strobe,
input sel_ram,
input tc_cnt,
output reg wr_en_ram_0,
output reg wr_en_ram_1,
output reg en_cnt,
output reg sclr_cnt,
output reg ready
);
reg [6:0] present_state, next_state;
//sta... | 6.931206 |
module cu_reg_rst_load (
input clk,
input reset,
input load_enable,
input [15:0] data_in,
output reg [15:0] data_out
);
always @(negedge clk) begin
if (load_enable) data_out <= data_in;
if (reset) data_out <= 16'b0;
end
endmodule
| 6.821153 |
module cu_sim ();
reg mwreg, ewreg, em2reg, mm2reg, rsrtequ;
reg [4:0] mrn, ern, rs, rt;
reg [5:0] func, op;
reg cpdone; //use to judge whether the compare is successful
wire jalr;
wire [3:0] aluc;
wire [1:0] pcsource;
wire [1:0] fwda, fwdb; //foewarding
wire nostall; //stall pipeline due to lw d... | 7.58815 |
module cu_simulator ( /*AUTOARG*/
// Outputs
cu2dispatch_wf_done,
cu2dispatch_wf_tag_done,
// Inputs
clk,
rst,
all_wf_dispatched,
dispatch2cu_wf_dispatch,
dispatch2cu_lds_base_dispatch,
dispatch2cu_sgpr_base_dispatch,
dispatch2cu_start_pc_dispatch,
dispatch2cu_vgpr_base_... | 6.558148 |
module: ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CU_testbench;
// Inputs
reg [7:0] IR_value;
reg [7:0] PC_value;
reg CLK;
reg RESET;
reg Sign_value;
reg Co... | 7.944032 |
module cu_top (
input clk,
input rst_n,
output [7:0] led,
input usb_rx,
output usb_tx
);
wire rst;
reset_conditioner reset_conditioner (
.clk(clk),
.in (!rst_n),
.out(rst)
);
assign led = rst ? 8'hAA : 8'h55;
assign usb_tx = usb_rx;
endmodule
| 7.841715 |
module: CU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CU_TV;
// Inputs
reg [10:0] Opcode;
// Outputs
wire Reg2Loc;
wire ALUSrc;
wire [2:0] ALUOp;
wire Branch;
wire Mem... | 6.786456 |
module CVCoreWrapper (
input clk,
input rst,
input [ 7:0] id,
input broadcast,
input cfg,
// data loader signals
input din_valid,
input [15:0] din_data,
output dout_valid,
input dout_ready,
output [15:0] dout_data,
... | 7.251571 |
module CVG #(
parameter W = 4,
k = 4'b1011
) (
out
);
output reg [W-1:0] out; //Create a W bit reg
initial begin
out = k; //Continuosly assign output to given parameter
end
endmodule
| 6.851657 |
module DFF_AR (
q,
ck,
d,
ar
);
output q;
input ck, d, ar;
CVDFF dff (
q,
d,
ck,
1'd1,
ar,
1'b0
);
endmodule
| 7.337433 |
module DFF_CEAR (
q,
ck,
d,
ce,
ar
);
output q;
input ck, d, ar, ce;
CVDFF dff (
q,
d,
ck,
ce,
ar,
1'd0
);
endmodule
| 6.675741 |
module CVDFF (
q,
d,
clk,
ce,
ar,
spare
);
output q;
reg q;
initial q = 0;
input clk; // Clock (positive edge triggered)
input d; // Data input
input ce; // Clock enable
input ar; // Asynchronous reset
input spare;
integer last_d;
integer last_clk;
always @(posedge c... | 6.651824 |
module CVXOR2 (
o,
i1,
i2
);
input i1, i2;
output o;
assign #3 o = i1 != i2;
endmodule
| 7.374551 |
module CVXOR3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
assign #2 o = (i1 != i2) != i3;
endmodule
| 7.513365 |
module CVXOR4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
assign #2 o = (i1 != i2) != (i3 != i4);
endmodule
| 7.310707 |
module CVAND2 (
o,
i1,
i2
);
input i1, i2;
output o;
assign #2 o = i1 & i2;
endmodule
| 7.522236 |
module CVAND3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
assign #2 o = i1 & i2 & i3;
endmodule
| 7.11898 |
module CVAND4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
assign #2 o = i1 & i2 & i3 & i4;
endmodule
| 7.229101 |
module CVAND5 (
o,
i1,
i2,
i3,
i4,
i5
);
input i1, i2, i3, i4, i5;
output o;
assign #2 o = i1 & i2 & i3 & i4 & i5;
endmodule
| 7.251795 |
module CVOR2 (
o,
i1,
i2
);
input i1, i2;
output o;
assign #2 o = i1 | i2;
endmodule
| 7.083204 |
module CVOR3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
assign #2 o = i1 | i2 | i3;
endmodule
| 6.977594 |
module CVOR4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
assign #2 o = i1 | i2 | i3 | i4;
endmodule
| 7.190037 |
module CVOR5 (
o,
i1,
i2,
i3,
i4,
i5
);
input i1, i2, i3, i4, i5;
output o;
assign #2 o = i1 | i2 | i3 | i4 | i5;
endmodule
| 6.70269 |
module CVINV (
o,
i
);
output o;
input i;
assign #2 o = ~i;
endmodule
| 7.151525 |
module CV_INT_FL1_MULTIPLIER_US // Fixed latency of 1, fully-pipelined, unsigned multiplier. Used from 5 to 16 bits of result width or so.
#(
parameter RWIDTH = 16,
parameter A0WIDTH = 16,
parameter A1WIDTH = 16,
parameter trace_me = 0
) (
input clk,
input reset,
output [RWIDTH-1:0] RR... | 7.199682 |
module CV_INT_FL2_MULTIPLIER_US // Fixed latency of 2, fully-pipelined, unsigned multiplier. Typically used for 16 to 32 bits.
#(
parameter RWIDTH = 32,
parameter A0WIDTH = 32,
parameter A1WIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output reg [RWIDTH-1:0] RR,
i... | 7.844871 |
module CV_INT_FL3_MULTIPLIER_US // Fixed latency of 2, fully-pipelined, unsigned multiplier. Typically used for 16 to 32 bits.
#(
parameter RWIDTH = 32,
parameter A0WIDTH = 32,
parameter A1WIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output reg [RWIDTH-1:0] RR,
i... | 9.801357 |
module CV_INT_FL1_MULTIPLIER_S // Fixed latency of 1, fully-pipelined, signed multiplier. Used from 5 to 16 bits of result width or so.
#(
parameter RWIDTH = 16,
parameter A0WIDTH = 16,
parameter A1WIDTH = 16,
parameter trace_me = 0
) (
input clk,
input reset,
output signed [RWIDTH-1:0... | 7.199682 |
module CV_INT_FL2_MULTIPLIER_S // Fixed latency of 2, fully-pipelined, signed multiplier. Typically used for 16 to 32 bits.
#(
parameter RWIDTH = 32,
parameter A0WIDTH = 32,
parameter A1WIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output reg signed [RWIDTH-1:0] RR,
... | 7.844871 |
module CV_INT_FL3_MULTIPLIER_S // Fixed latency of 3, fully-pipelined, signed multiplier. Typically used for 16 to 32 bits on Xilinx. Altera is quicker?
#(
parameter RWIDTH = 32,
parameter A0WIDTH = 32,
parameter A1WIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output ... | 9.801357 |
module CV_INT_FL5_MULTIPLIER_S // Fixed latency of 5, fully-pipelined, signed multiplier. Typically used for 64 bits or so.
#(
parameter RWIDTH = 32,
parameter A0WIDTH = 32,
parameter A1WIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output reg signed [RWIDTH-1:0] RR,
... | 7.309025 |
module CV_INT_FL5_MULTIPLIER_US // Fixed latency of 5, fully-pipelined, un-signed multiplier. Typically used for 64 bits or so.
#(
parameter RWIDTH = 32,
parameter A0WIDTH = 32,
parameter A1WIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output reg [RWIDTH-1:0] RR,
... | 7.309025 |
module CV_INT_FL1_ADDER // Fixed latency of 1, fully-pipelined, adder with signed and unsigned overflow outputs.
#(
parameter RWIDTH = 32,
parameter A0WIDTH = 32,
parameter A1WIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output [ RWIDTH-1:0] RR,
input [A0WIDTH-1:0... | 6.915515 |
module CV_INT_FL_DIVIDER_US // slower_on_average than vari-latency.
#(
parameter RWIDTH = 32,
parameter NWIDTH = 32,
parameter DWIDTH = 32,
parameter trace_me = 0,
parameter divmod = 1
) (
input clk,
input reset,
output reg rdy,
input REQ,
output [RW... | 6.908328 |
module CV_INT_VL_DIVIDER_US #(
parameter RWIDTH = 32,
parameter NWIDTH = 32,
parameter DWIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
input REQ,
output ACK,
output [RWIDTH-1:0] RR,
input [NWIDTH-1:0] NN,
input [DWIDTH-1:0] DD,
output FAIL
);
... | 7.52146 |
module CV_INT_VL_MODULUS_US #(
parameter RWIDTH = 32,
parameter NWIDTH = 32,
parameter DWIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output ACK,
input REQ,
output [RWIDTH-1:0] RR,
input [NWIDTH-1:0] NN,
input [DWIDTH-1:0] DD,
output FAIL
)... | 7.195249 |
module CV_INT_VL_MODULUS_S #(
parameter RWIDTH = 32,
parameter NWIDTH = 32,
parameter DWIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output ACK, // Result ready.
input REQ, //... | 7.195249 |
module CV_INT_VL_DIVMOD_US #(
parameter divmod = 1,
parameter RWIDTH = 32,
parameter NWIDTH = 32,
parameter DWIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output reg ACK,
input REQ,
output [RWIDTH-1:0] RR,
input [NWIDTH-1:0] NN,
input [DWIDTH-1:... | 7.52146 |
module CV_INT_VL_DIVIDER_S #(
parameter RWIDTH = 32,
parameter NWIDTH = 32,
parameter DWIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output ACK, // Result ready.
input REQ, //... | 7.52146 |
module CV_SP_SSRAM_FL0 #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10,
parameter WORDS = 1024,
parameter LANE_WIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output [ DATA_WIDTH-1:0] rdata,
in... | 7.985482 |
module CV_SP_SSRAM_FL1 #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10,
parameter WORDS = 1024,
parameter LANE_WIDTH = 32,
parameter trace_me = 0
) (
input clk,
input reset,
output reg [ DATA_WIDTH-1:0] r... | 7.985482 |
module CV_2P_SSRAM_FL1 #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10,
parameter WORDS = 1024,
parameter LANE_WIDTH = 32,
parameter trace_me = 0
) (
input clk, // TODO this clock should be part of the port for a future domain crossing variant.
input reset,
// Port 0
outpu... | 8.035101 |
module. error is asserted if a packet is larger than the quantum
// error can be reset by asserting reset or clear.
module cvita_chunker # (
parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF
) (
input clk,
input reset,
input clear,
input [15:0] frame_size,
input [63:0] i_tda... | 6.554729 |
module cvita_dechunker #(
parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF
) (
input clk,
input reset,
input clear,
input [15:0] frame_size,
input [63:0] i_tdata,
input i_tvalid,
output i_tready,
output [63:0] o_tdata,
output o_tlast,
... | 6.724661 |
module cvita_to_axis (
input wire clk,
input wire [63:0] i_tdata,
input wire i_tlast,
input wire i_tvalid,
output wire i_tready,
output wire [63:0] m_axis_tdata,
output wire m_axis_tlast,
output wire m_axis_tvalid,
input wire m_axis_tre... | 6.809322 |
modules.
// Check also David Bishop’s IEEE Proposed library 1 . http://www.eda.org/fphdl/
//
// Overall, this file should be junked and using good quality output from FloPoCo instead should be substituted.
// In theory, the ALU name and clock-enable details should be specifiable in IP-XACT sometime soon, as is suppo... | 7.429217 |
module CV_FP_FL4_MULTIPLIER_SP (
input clk,
input reset,
output [31:0] RR,
input [31:0] XX,
input [31:0] YY,
output FAIL
);
reg [7:0] exp_l_1, exp_r_1;
reg [22:0] maint_l_1, maint_r_1;
reg s_l_1, s_r_1;
reg [7:0] exp_l_2, exp_r_2;
reg [31:0] arg_l_1, arg_r_1; // Fixed pipeline late... | 6.969528 |
module CV_FP_FL3_MULTIPLIER_DP (
input clk,
input reset,
output [63:0] RR,
input [63:0] XX,
input [63:0] YY,
output FAIL
);
wire [10:0] exp1, exp2;
wire [51:0] mant1, mant2;
wire s1, s2;
reg [63:0] arg1, arg2, res0, res1; // Fixed pipeline latency (FL) 3.
reg fl0, fl1;
assign {s1,... | 6.874072 |
module RAD4_IDIVCELL #(
parameter h_offset = 0,
parameter d_offset = 0
) (
input clk,
input [23:0] num_in,
output reg [23:0] num_out,
input [23:0] den_in,
output reg [23:0] den_out,
input [23:0] quot_in,
output reg [23:0] quot_out,
input [12:0] mei... | 7.043673 |
module RAD4_FDIVCELL #(
parameter h_offset = 0,
parameter d_offset = 24
) (
input clk,
input [23:0] num_in,
output reg [23:0] num_out,
input [23:0] den_in,
output reg [23:0] den_out,
input [25:0] quot_in,
output reg [25:0] quot_out,
input [12:0] me... | 6.75915 |
module CV_FP_FL4_ADDER_DP (
input clk,
input reset,
output [63:0] RR,
input [63:0] XX,
input [63:0] YY, // denominator
output FAIL
);
CV_FP_FL4_ADDSUB_DP addcore (
clk,
reset,
RR,
XX,
YY,
FAIL,
1'b0
);
endmodule
| 6.711563 |
module CV_FP_FL4_ADDER_SP (
input clk,
input reset,
output [31:0] RR,
input [31:0] XX, // numerator
input [31:0] YY, // denominator
output FAIL
);
CV_FP_FL4_ADDSUB_SP addcore (
clk,
reset,
RR,
XX,
YY,
FAIL,
1'b0
);
endmodule
| 6.711563 |
module top (
input clk,
output clkin,
modout,
lock
);
wire clkout;
// PLL running at 255 MHz (near max 275 MHz)
// Generated using icepll utility in icestorm package [ icepll -i 12 -o 255 ]
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(4'b0000)... | 7.233807 |
module cw_exp #
(
)
(
input wire clk,
input wire rstn,
input wire tx_try_complete,
input wire quit_retrans,
input wire [31:0] cw_combined,
input wire retrans_trigger,
input wire [1:0] tx_queue_idx,
`DEBUG_PREFIX output reg [3:0] cw_exp
);
// (* mark_debug = "true", DONT_TOUCH = "TRUE" *... | 7.243935 |
module cxapbasyncbridge (
// Slave Interface
//Clock and reset signals
input pclkens,
input pclks,
input presetsn,
//APB3 Bus
input [31:0] paddrs,
input [31:0] pwdatas,
input pwrites,
input penables,
input psels,
output [31:0] prdatas,
output pslverrs,
output p... | 7.308556 |
module should be used
// wherever an unsafe asynchronous input must be used.
//
//------------------------------------------------------------------------------
module cxapbasyncbridge_cdc_capt_sync (clk, resetn, d_async, sync_en, q);
parameter WIDTH = 4;
// -------------------------------------------... | 8.056742 |
module cxapbasyncbridge_cdc_comb_and (
q,
d_async,
valid
);
parameter WIDTH = 4; // Width of the payload
// ------------------------------------------------------
// port declaration
// ------------------------------------------------------
output [WIDTH-1:0] q;
input [WIDTH-1:0] d_async; //... | 7.308556 |
module cxapbasyncbridge_cdc_corrupt (
clk,
sync,
d,
q
);
parameter WIDTH = 1;
// ------------------------------------------------------
// port declaration
// ------------------------------------------------------
input clk;
input sync;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
// ... | 7.308556 |
module cxapbasyncbridge_cdc_corrupt_gry (
clk,
resetn,
sync,
d_async,
q_async
);
parameter WIDTH = 1;
// ------------------------------------------------------
// port declaration
// ------------------------------------------------------
input clk;
input resetn;
input sync;
input [... | 7.308556 |
module cxapbasyncbridge_cdc_launch_data (
clk,
resetn,
enable,
in_cdc,
out_async
);
parameter WIDTH = 1;
// ------------------------------------------------------
// port declaration
// ------------------------------------------------------
input clk;
input resetn;
input enable;
in... | 7.308556 |
module cxapbasyncbridge_cdc_launch_gry (
clk,
resetn,
enable,
in_cdc,
out_async
);
parameter WIDTH = 1;
// ------------------------------------------------------
// port declaration
// ------------------------------------------------------
input clk;
input resetn;
input enable;
inp... | 7.308556 |
module cxapbasyncbridge_cdc_random (
din,
dout
);
// ------------------------------------------------------
// parameter declaration
// ------------------------------------------------------
parameter WIDTH = 4;
parameter HIER_LEN = 100;
// ------------------------------------------------------
... | 7.308556 |
module CRC_CAL (
CLK4,
D,
CRC_ARM,
CRC_ENB,
CRC_Q
);
input CLK4;
input [15:0] D;
input CRC_ARM;
input CRC_ENB;
output [15:0] CRC_Q;
wire [15:0] R_D;
reg [15:0] R_Q;
// CRC combination logic block
CRC_CL CF (
.D(D), // one input is the data block
.C(R_Q), // othe... | 7.223731 |
module Top (
input reset,
input clk4,
input IDE_CS,
output dna_pass,
output [3:0] KILL
);
wire [63:0] dna64bits;
wire dna_valid;
wire SR_ena;
wire [9:0] addra;
wire [15:0] douta;
// constant holder for RAM implementation
// begin
//wire [15:0] dina;
//wire wea;
//... | 6.64497 |
module instantiates a fast, non-synthesisable execution engine.
// The simulation engine supports semihosted printing, so does not
// require retarget code.
//-----------------------------------------------------------------------------
module CXDT
#(
parameter IMAGENAME = "image.bin",
parameter IMAGEPLU... | 7.670485 |
module cxs_link_credit_manager (
input clk,
input resetn,
input dec_credits,
input incr_credits,
input [4:0] refill_credits,
output reg credits_available,
output [3:0] cur_credits,
output credit_maxed
);
wire credit_update;
wire [3:0] incremented_credits;
wire [3:0] decremented... | 7.234119 |
module, to store incoming flits
*
*/
module cxs_rxflit_ram
#(
parameter AWIDTH = 12, // Address Width
parameter WWIDTH = 128, // Data Width
parameter RWIDTH = 32, // Data Width
parameter OREG_A = "TRUE", // Optional Port A output pipeline registers
parameter OREG_B = "TRUE" // Optional P... | 9.674427 |
module cxs_txflit_mgmt (
input clk,
input rst_n,
//to/from register interface
input [14:0] own_flit,
input credit_avail,
input link_up,
output reg read_req,
output reg flit_pending,
output reg [ 3:0] read_addr,
output reg flit_va... | 7.708089 |
module, to store flits before giving to DUT
*
*/
module cxs_txflit_ram #(
parameter AWIDTH = 12, // Address Width
parameter WWIDTH = 128, // Data Width
parameter RWIDTH = 128, // Data Width
parameter OREG_A = "TRUE", // Optional Port A output pipeline registers
parameter OREG_B = "TRUE" // Optio... | 9.136395 |
module Mux5_2 (
in0,
in1,
sel,
out
);
input [4:0] in0, in1;
input sel;
output [4:0] out;
reg [4:0] out;
always @(*) begin
if (sel == 1) out = in1;
else out = in0;
end
endmodule
| 6.735215 |
module Mux32_2 (
in0,
in1,
sel,
out
);
input [31:0] in0, in1;
input sel;
output [31:0] out;
reg [31:0] out;
always @(*) begin
if (sel == 1) out = in1;
else out = in0;
end
// assign out = sel == 1 ? in1 : in0;
endmodule
| 7.327179 |
module Mux32_4 (
in0,
in1,
in2,
in3,
sel,
out
);
input [31:0] in0, in1, in2, in3;
input [1:0] sel;
output [31:0] out;
reg [31:0] out;
always @(*) begin
if (sel == 00) out = in0;
else if (sel == 2'b01) out = in1;
else if (sel == 2'b10) out = in2;
else if (sel == 2'b11) ... | 6.991636 |
module SigExt16_32 (
in,
out
);
input [15:0] in;
output [31:0] out;
reg [31:0] out;
always @(in) begin
if (in[15] == 1) out = {16'b1111111111111111, in};
else out = {16'b0000000000000000, in};
end
endmodule
| 7.020847 |
module SHL2_26 (
in,
out
);
input [25:0] in;
output [27:0] out;
reg [27:0] out;
always @(in) begin
out = in << 2;
end
endmodule
| 6.531721 |
module SHL2_32 (
in,
out
);
input [31:0] in;
output [31:0] out;
reg [31:0] out;
always @(in) begin
out = in << 2;
end
endmodule
| 6.697798 |
module PC_Reg (
D,
Q,
PCWr,
clk
);
input clk, PCWr;
input [31:0] D;
output [31:0] Q;
reg [31:0] Q;
initial begin
Q = -1;
end
always @(posedge clk) begin
if (PCWr == 1) Q = D;
end
endmodule
| 6.861789 |
module ALU (
in1,
in2,
mod,
out,
zf
);
input [2:0] mod;
output [31:0] out;
reg [31:0] out;
output zf;
reg zf;
input [31:0] in1, in2;
always @(in1 or in2 or mod) begin
case (mod)
`ADD: out = in1 + in2;
`SUB: out = in1 - in2;
`AND: out = in1 & in2;
`OR: out =... | 7.37871 |
module ALU_CU (
ALUOP,
func,
clk,
ALUCtrl
);
input clk;
input [1:0] ALUOP;
input [5:0] func; // function字段, R型指令使用
output [2:0] ALUCtrl;
reg [2:0] ALUCtrl;
always @(ALUOP or func) begin
if (ALUOP == 2'b00) ALUCtrl = `ADD; // LW 和 SW
else if (ALUOP == 2'b01) ALUCtrl = `SUB;
els... | 6.84921 |
module MCU (
op_code,
clk,
regDst,
jump,
regWr,
branch,
memtoReg,
ALUOP,
memWr,
memRd,
ALUSrc
);
input clk;
input [5:0] op_code; // 操作码
output [1:0] ALUOP;
reg [1:0] ALUOP;
output regDst, jump, regWr, branch, memtoReg, memWr, memRd, ALUSrc;
reg regDst, jump, regW... | 6.565192 |
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