code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Inst_Mem(addr, inst, clk);
output[31:0] inst; // 32位指令
reg[31:0] inst;
input[31:0] addr; // 32位地址线
input clk;
reg[31:0] instr[4*1024*1024-1:0]; // 存储矩阵(注意此处本来应该还有个1024的！！ 因为说数组过大报warning)
initial begin
//---------------------------第一个程序(简单算术运算)-------------------------------------------------------... | 6.715273 |
module RF (
R_Reg1,
R_Reg2,
R_data1,
R_data2,
W_Reg,
W_data,
we,
clk
);
input [4:0] R_Reg1, R_Reg2, W_Reg; // 5位地址线
input [31:0] W_data;
input clk, we;
output [31:0] R_data1, R_data2;
reg [31:0] R_data1, R_data2;
reg [31:0] Reg[31:0];
initial begin
//-----------------... | 6.685832 |
module Data_Mem (
addr,
R_data,
W_data,
clk,
R,
W
);
output [31:0] R_data; // 32位数据线
reg [31:0] R_data;
input [31:0] addr, W_data; // 32位地址线
input clk, R, W;
reg[31:0] mem[4*1024*1024-1:0]; // 存储矩阵(注意此处本来应该还有个1024的！！ 因为说数组过大报warning)
initial begin
mem[11] = 32'h0D;
mem[12]... | 7.300967 |
module Transfer_CU (
EX_MA_RegWr,
EX_MA_MemtoReg,
EX_MA_MemWr, // 完成
ID_EX_IR,
EX_MA_IR,
MA_WB_IR,
ID_EX_MemWr,
MA_WB_RegWr,
ALUSrc_A,
ALUSrc_B,
MemSrc,
ALUSrc
);
input EX_MA_RegWr, EX_MA_MemtoReg, EX_MA_MemWr, ID_EX_MemWr, MA_WB_RegWr, ALUSrc;
input [31:0] ID_EX_IR,... | 7.545614 |
module sram_cy6264 #(
parameter FILE_NAME = "",
// CY6424-70 timing and naming conventions (or thereabouts)
// read
parameter tAA = 70, // address access time
parameter tOHA = 5, // output data hold time from address change
parameter tACE = 70, // CE access time
parameter... | 8.781743 |
module cpu (
input sys_clk,
input sys_rst_n,
output [31:0] bus_address,
inout [15:0] bus_data,
output bus_rw, // 0: device -> cpu 1:cpu -> device
input bus_data_valid,
input bus_write_ack
);
reg [15:0] cs;
reg [15:0] pc;
always @(*) begin
end... | 6.869387 |
module cpu (
input sys_clk,
input sys_rst_n,
output [31:0] bus_address,
inout [15:0] bus_data,
output bus_rw, // 0: device -> cpu 1:cpu -> device
input bus_data_valid,
input bus_write_ack
);
reg [15:0] cs;
reg [15:0] pc;
always @(*) begin
end... | 6.869387 |
module CY7C67200_IF ( // HOST Side
iDATA,
oDATA,
iADDR, //for HPI register selection
iRD_N,
iWR_N,
iCS_N,
iRST_N,
iCLK,
oINT,
// CY7C67200 Side
// OTG_ID, //HPI mode selection(host or peripheral)
HPI_DATA,
HPI_ADDR,
HPI_RD_N,
HPI_WR_N,
HPI... | 7.209619 |
module cyc1000_clock_gen (
input wire i_clk,
output wire o_clk,
output wire o_rst
);
wire [4:0] clk;
wire clk_fb;
wire locked;
reg [9:0] r;
assign o_clk = clk[0];
assign o_rst = r[9];
always @(posedge o_clk)
if (locked) r <= {r[8:0], 1'b0};
else r <= 10'b1111111111;... | 6.637684 |
module CYCLE_COUNTER #(
parameter DWIDTH = 32
) (
input clk,
input rst,
output [DWIDTH - 1:0] cycle
);
wire [DWIDTH - 1:0] cycle_value, cycle_next;
REGISTER_R #(
.N(DWIDTH),
.INIT(0)
) cycle_reg (
.clk(clk),
.rst(rst),
.q (cycle_value),
.d (cycle_next)
);
... | 6.772085 |
module calculates the average over incoming values.
* It adds a predefined number of values (which must be a power of 2)
* to an internal accumulator register and divides it
* to output an average value.
*/
module average
#(
parameter bitwidth_sample = 12,
parameter bitwidth_accumulator = 16
... | 7.448165 |
module CycleStatistic (
input wire pcen,
input wire Jmp,
input wire clk,
input wire rst,
input wire pcsel,
output reg [31:0] TotalCycle,
output reg [31:0] CoBranchCycle,
output reg [31:0] UnBranchCycle
);
always @(posedge clk) begin
if (rst) begin
TotalCycle <= 0;
CoBra... | 7.122419 |
module cycle_colour (
input CLK,
input pushbutton,
output reg [2:0] colour = 3'b000
);
wire slow_clock;
wire pulse;
button_clk slowclk (
CLK,
slow_clock
);
single_pulse sp1 (
slow_clock,
pushbutton,
pulse
);
always @(posedge slow_clock) begin
colour = (pulse... | 6.591747 |
module name - cycle_control
// Version: V3.4.0.20220401
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
// global time synchronization
// generate report pulse base on global time
////////////////////////////////////////... | 7.351732 |
module cycle_controller (
clk,
rst,
op_in,
pol_in,
no_in,
ts_in,
op_out,
pol_out,
cc_cmp_out,
cc_cmpff_out
);
//-----------------------------------------------
// Parameters and Definitions
//-----------------------------------------------
parameter mw = `MARCH_MAX_OPS;
... | 7.344795 |
module control_mux (
op_in,
pol_in,
cyc_cnt_in,
op_out,
pol_out
);
//-----------------------------------------------
// Parameters and Definitions
//-----------------------------------------------
parameter mw = `MARCH_MAX_OPS;
parameter rw = `MARCH_SEQ_SIZE;
parameter cs = `CYCLE_COUNT... | 7.537861 |
module cycle_counter (
clk,
r_in,
cyc_cnt_out
);
//-----------------------------------------------
// Parameters and Definitions
//-----------------------------------------------
parameter mw = `MARCH_MAX_OPS;
parameter rw = `MARCH_SEQ_SIZE;
parameter cs = `CYCLE_COUNTER_SIZE;
//-------------... | 7.010616 |
module cycle_depth (
input CLK,
input pushbutton,
output reg [1:0] depth = 2'b00
);
wire slow_clock;
wire pulse;
button_clk slowclk (
CLK,
slow_clock
);
single_pulse sp1 (
slow_clock,
pushbutton,
pulse
);
always @(posedge slow_clock) begin
depth = (pulse == ... | 6.632203 |
module mgc_in_wire (
d,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] d;
input [width-1:0] z;
wire [width-1:0] d;
assign d = z;
endmodule
| 6.848125 |
module mgc_in_wire_en (
ld,
d,
lz,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
output [width-1:0] d;
output lz;
input [width-1:0] z;
wire [width-1:0] d;
wire lz;
assign d = z;
assign lz = ld;
endmodule
| 6.69754 |
module mgc_in_wire_wait (
ld,
vd,
d,
lz,
vz,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
output vd;
output [width-1:0] d;
output lz;
input vz;
input [width-1:0] z;
wire vd;
wire [width-1:0] d;
wire lz;
assign d = z... | 6.823121 |
module mgc_out_stdreg (
d,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input [width-1:0] d;
output [width-1:0] z;
wire [width-1:0] z;
assign z = d;
endmodule
| 7.174555 |
module mgc_out_stdreg_en (
ld,
d,
lz,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
input [width-1:0] d;
output lz;
output [width-1:0] z;
wire lz;
wire [width-1:0] z;
assign z = d;
assign lz = ld;
endmodule
| 7.174555 |
module mgc_out_stdreg_wait (
ld,
vd,
d,
lz,
vz,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
output vd;
input [width-1:0] d;
output lz;
input vz;
output [width-1:0] z;
wire vd;
wire lz;
wire [width-1:0] z;
assign z ... | 7.174555 |
module mgc_out_prereg_en (
ld,
d,
lz,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
input [width-1:0] d;
output lz;
output [width-1:0] z;
wire lz;
wire [width-1:0] z;
assign z = d;
assign lz = ld;
endmodule
| 6.907486 |
module mgc_inout_stdreg_en (
ldin,
din,
ldout,
dout,
lzin,
lzout,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input ldin;
output [width-1:0] din;
input ldout;
input [width-1:0] dout;
output lzin;
output lzout;
inout [width-1:0] z;
wire [width-1:0] di... | 6.612118 |
module mgc_inout_stdreg_wait (
ldin,
vdin,
din,
ldout,
vdout,
dout,
lzin,
vzin,
lzout,
vzout,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input ldin;
output vdin;
output [width-1:0] din;
input ldout;
output vdout;
input [width-1:0] dout;
... | 6.612118 |
module mgc_inout_buf_wait (
clk,
en,
arst,
srst,
ldin,
vdin,
din,
ldout,
vdout,
dout,
lzin,
vzin,
lzout,
vzout,
z
);
parameter integer rscid = 0; // resource ID
parameter integer width = 8; // fifo width
parameter ph_clk = 1'b1; // clock polarity 1=r... | 6.732804 |
module mgc_inout_fifo_wait (
clk,
en,
arst,
srst,
ldin,
vdin,
din,
ldout,
vdout,
dout,
lzin,
vzin,
lzout,
vzout,
z
);
parameter integer rscid = 0; // resource ID
parameter integer width = 8; // fifo width
parameter integer fifo_sz = 8; // fifo depth
... | 6.94329 |
module mgc_bsync_vld (
vd,
vz
);
parameter integer rscid = 0; // resource ID
parameter ready = 0;
parameter valid = 1;
output vd;
input vz;
wire vd;
assign vd = vz;
endmodule
| 6.550953 |
module mgc_bsync_rv (
rd,
vd,
rz,
vz
);
parameter integer rscid = 0; // resource ID
parameter ready = 1;
parameter valid = 1;
input rd;
output vd;
output rz;
input vz;
wire vd;
wire rz;
assign rz = rd;
assign vd = vz;
endmodule
| 6.756473 |
module funccall_inout (
d,
ad,
bd,
z,
az,
bz
);
parameter integer ram_id = 1;
parameter integer width = 8;
parameter integer addr_width = 8;
output [width-1:0] d;
input [addr_width-1:0] ad;
input bd;
input [width-1:0] z;
output [addr_width-1:0] az;
output bz;
wire [ wi... | 7.9851 |
module modulario_en_in (
vd,
d,
vz,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
output vd;
output [width-1:0] d;
input vz;
input [width-1:0] z;
wire [width-1:0] d;
wire vd;
assign d = z;
assign vd = vz;
endmodule
| 8.930615 |
module mgc_out_reg_pos (
clk,
en,
arst,
srst,
ld,
d,
lz,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
parameter ph_en = 1'b1;
parameter ph_arst = 1'b1;
parameter ph_srst = 1'b1;
input clk;
input en;
input arst;
input srst;
input ld;
input [width-... | 7.222065 |
module mgc_out_reg_neg (
clk,
en,
arst,
srst,
ld,
d,
lz,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
parameter ph_en = 1'b1;
parameter ph_arst = 1'b1;
parameter ph_srst = 1'b1;
input clk;
input en;
input arst;
input srst;
input ld;
input [width-... | 7.259562 |
module mgc_out_reg (
clk,
en,
arst,
srst,
ld,
d,
lz,
z
); // Not Supported
parameter integer rscid = 1;
parameter integer width = 8;
parameter ph_clk = 1'b1;
parameter ph_en = 1'b1;
parameter ph_arst = 1'b1;
parameter ph_srst = 1'b1;
input clk;
input en;
input arst;
... | 7.171083 |
module mgc_out_buf_wait (
clk,
en,
arst,
srst,
ld,
vd,
d,
vz,
lz,
z
); // Not supported
parameter integer rscid = 1;
parameter integer width = 8;
parameter ph_clk = 1'b1;
parameter ph_en = 1'b1;
parameter ph_arst = 1'b1;
parameter ph_srst = 1'b1;
input clk;
inp... | 7.427993 |
module mgc_out_fifo_wait (
clk,
en,
arst,
srst,
ld,
vd,
d,
lz,
vz,
z
);
parameter integer rscid = 0; // resource ID
parameter integer width = 8; // fifo width
parameter integer fifo_sz = 8; // fifo depth
parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=fal... | 8.250191 |
module mgc_pipe (
clk,
en,
arst,
srst,
ldin,
vdin,
din,
ldout,
vdout,
dout,
size,
req_size
);
parameter integer rscid = 0; // resource ID
parameter integer width = 8; // fifo width
parameter integer sz_width = 8; // width of size of elements in fifo
parameter ... | 7.579732 |
module name - cycle_start_judge
// Version: V3.4.0.20220420
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/100ps
module cycle_start_judge(
input ... | 7.351732 |
module creates a 8 bit Cyclical Right Shift Register using asynchronous D Flip Flops.
*/
module cyclical_right_shift_register_8_async(clk, resetn, enable, select, d, q);
//Define the inputs and outputs
input clk;
input resetn;
input enable;
input select;
input [7:0] d;
output [7:0] q;
wire [7:0]mux_out;
... | 8.1836 |
module cyclone10_top (
// Clocks and Reset
input c10_clk50m,
input c10_resetn,
// 40 pin GPIO header
inout [35:0] gpio,
// 4 Green LEDs
output [3:0] user_led,
// 4 Push buttons
input [3:0] user_pb,
// Ethernet
input enet_clk_125m,
input enet_rx_clk,
... | 6.721704 |
module cycloneiiils_dffe (
Q,
CLK,
ENA,
D,
CLRN,
PRN
);
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);... | 7.248911 |
module cycloneiiils_mux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf (A_in, A);
buf (B_in, B);
buf (S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in ==... | 7.248911 |
module cycloneiiils_mux41 (
MO,
IN0,
IN1,
IN2,
IN3,
S
);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf (IN0_in, IN0);
buf (IN1_in, IN1);
buf (IN2_in, IN2);
bu... | 7.248911 |
module cycloneiiils_and1 (
Y,
IN1
);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
| 7.248911 |
module cycloneiiils_and16 (
Y,
IN1
);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[... | 7.248911 |
module cycloneiiils_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.248911 |
module cycloneiiils_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.248911 |
module cycloneiiils_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.248911 |
module cycloneiiils_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.248911 |
module cycloneiiils_latch (
D,
ENA,
PRE,
CLR,
Q
);
input D;
input ENA, PRE, CLR;
output Q;
reg q_out;
specify
$setup(D, negedge ENA, 0);
$hold(negedge ENA, D, 0);
(D => Q) = (0, 0);
(negedge ENA => (Q +: q_out)) = (0, 0);
(negedge PRE => (Q +: q_out)) = (0, 0);
... | 7.248911 |
module cycloneiiils_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 7.248911 |
module cycloneiiils_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;... | 7.248911 |
module cycloneiiils_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial b... | 7.248911 |
module cycloneiiils_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;... | 7.248911 |
module cycloneiiils_pll_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial... | 7.248911 |
module cycloneiiils_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter dont_touch = "off... | 7.248911 |
module cycloneiiils_ff (
d,
clk,
clrn,
aload,
sclr,
sload,
asdata,
ena,
devclrn,
devpor,
q
);
parameter power_up = "low";
parameter x_on_violation = "on";
parameter lpm_type = "cycloneiiils_ff";
input d;
input clk;
input clrn;
input aload;
input sclr;
inpu... | 7.248911 |
module cycloneiiils_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
r... | 7.248911 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_ram_register (
d,
clk,
aclr,
devclrn,
... | 7.458522 |
module cycloneiiils_mac_data_reg (
clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_... | 7.248911 |
module cycloneiiils_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULL... | 7.248911 |
module cycloneiiils_mac_mult_internal (
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input sign... | 7.248911 |
module cycloneiiils_mac_out (
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneiiils_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = ... | 7.248911 |
module cycloneiiils_io_ibuf (
i,
ibar,
o
);
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "cycloneiiils_io_ibuf";
// SIMULATION_ONLY_PARAMETERS_END
//Input Ports Declaration
inp... | 7.248911 |
module cycloneiiils_io_obuf (
i,
oe,
seriesterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter lpm_type = "cycloneiiils_io_obuf";
//Input Ports Declaration
input i;
input oe;
input devoe;
... | 7.248911 |
module cycloneiiils_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "cycloneiiils_ddio_oe";
//Inp... | 7.248911 |
module cycloneiiils_pseudo_diff_out (
i,
o,
obar
);
parameter lpm_type = "cycloneiiils_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always @(i) begin
if (i == 1'b1) begin
o_tmp = 1'b1;
obar_tmp = 1'... | 7.248911 |
module cycloneiiils_io_pad (
padin,
padout
);
parameter lpm_type = "cycloneiiils_io_pad";
//INPUT PORTS
input padin; //Input Pad
//OUTPUT PORTS
output padout; //Output Pad
//INTERNAL SIGNALS
wire padin_ipd;
wire padout_opd;
//INPUT BUFFER INSERTION FOR VERILOG-XL
buf padin_buf (padin_i... | 7.248911 |
module cycloneiiils_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
reg clk_last_value;
wire reset;
// DEFAULT... | 7.248911 |
module cycloneiiils_clkctrl (
inclk,
clkselect,
ena,
devpor,
devclrn,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
input ena;
input devpor;
input devclrn;
output outclk;
tri1 devclrn;
tri1 devpor;
parameter clock_type = "auto";
parameter ena_register_mode = "fallin... | 7.248911 |
module cycloneiiils_rublock (
clk,
shiftnld,
captnupdt,
regin,
rsttimer,
rconfig,
regout
);
parameter sim_init_config = "factory";
parameter sim_init_watchdog_value = 0;
parameter sim_init_status = 0;
parameter lpm_type = "cycloneiiils_rublock";
input clk;
input shiftnld;
inp... | 7.248911 |
module cycloneiiils_controller (
nceout
);
output nceout;
parameter lpm_type = "cycloneiiils_controller";
endmodule
| 7.248911 |
module cycloneiiils_jtag (
tms,
tck,
tdi,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user
);
input tms;
input tck;
input tdi;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
outp... | 7.248911 |
module cycloneiiils_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
cyclecomplete,
regout
);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output cyclecomplete;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
paramete... | 7.248911 |
module cycloneiiils_oscillator (
oscena,
clkout1,
observableoutputport,
clkout
);
parameter lpm_type = "cycloneiiils_oscillator";
input oscena;
output clkout1;
output observableoutputport;
output clkout;
// LOCAL_PARAMETERS_BEGIN
parameter OSC_PW = 6250; // fixed 80HZ running clock
... | 7.248911 |
module cycloneiii_mux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf (A_in, A);
buf (B_in, B);
buf (S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1... | 6.510186 |
module cycloneiii_mux41 (
MO,
IN0,
IN1,
IN2,
IN3,
S
);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf (IN0_in, IN0);
buf (IN1_in, IN1);
buf (IN2_in, IN2);
buf ... | 6.510186 |
module cycloneiii_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.537109 |
module cycloneiii_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.393095 |
module cycloneiii_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.116156 |
module cycloneiii_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.717795 |
module cycloneiii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 7.1216 |
module cycloneiii_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter dont_touch = "off";... | 7.490704 |
module cycloneiii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg... | 7.004297 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_ram_register (
d,
clk,
aclr,
devclrn,
... | 7.458522 |
module cycloneiii_mac_data_reg (
clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tm... | 8.426815 |
module cycloneiii_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUP... | 8.426815 |
module cycloneiii_mac_mult_internal (
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;... | 8.426815 |
module cycloneiii_mac_out (
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneiii_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = data... | 8.426815 |
module cycloneiii_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "cycloneiii_ddio_oe";
//Input P... | 6.965351 |
module cycloneiii_pseudo_diff_out (
i,
o,
obar
);
parameter lpm_type = "cycloneiii_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always @(i) begin
if (i == 1'b1) begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
... | 7.199791 |
module cycloneiii_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout
);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneiii_crcblock";
endmodul... | 6.584159 |
module cycloneiii_oscillator (
oscena,
clkout
);
parameter lpm_type = "cycloneiii_oscillator";
input oscena;
output clkout;
// LOCAL_PARAMETERS_BEGIN
parameter OSC_PW = 6250; // fixed 80HZ running clock
// LOCAL_PARAMETERS_END
// INTERNAL wire
reg int_osc; // internal oscillator
spec... | 7.591053 |
module cycloneii_mux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf (A_in, A);
buf (B_in, B);
buf (S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1)... | 6.536375 |
module cycloneii_mux41 (
MO,
IN0,
IN1,
IN2,
IN3,
S
);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf (IN0_in, IN0);
buf (IN1_in, IN1);
buf (IN2_in, IN2);
buf (... | 6.536375 |
module cycloneii_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.664777 |
module cycloneii_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.44559 |
module cycloneii_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.15714 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.