code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cycloneii_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.782791 |
module cycloneii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter start_delay = 1;
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0, t_access =... | 7.051311 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_ram_register (
d,
clk,
aclr,
devclrn,
... | 7.458522 |
module cycloneii_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user
);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
... | 6.667965 |
module cycloneii_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout
);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneii_crcblock";
endmodule
| 6.663903 |
module cycloneii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 6.781223 |
module cycloneii_lcell_ff (
datain,
clk,
aclr,
sclr,
sload,
sdata,
ena,
devclrn,
devpor,
regout
);
parameter x_on_violation = "on";
parameter lpm_type = "cycloneii_lcell_ff";
input datain;
input clk;
input aclr;
input sclr;
input sload;
input sdata;
input ena;... | 6.806143 |
module cycloneii_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter lpm_type = "cyclonei... | 6.806143 |
module cycloneii_mac_data_reg (
clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tmp... | 8.110529 |
module cycloneii_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUPs... | 8.110529 |
module cycloneii_mac_mult_internal (
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
... | 8.110529 |
module cycloneii_mac_out (
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneii_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_... | 8.110529 |
module cycloneive_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.040254 |
module cycloneive_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 6.970999 |
module cycloneive_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.025924 |
module cycloneive_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.30132 |
module cycloneive_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 6.568999 |
module cycloneive_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
... | 6.504388 |
module cycloneive_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter dont_touch = "off";... | 7.516967 |
module cycloneive_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg... | 7.267338 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_ram_register (
d,
clk,
aclr,
devclrn,
... | 7.458522 |
module cycloneive_mac_data_reg (
clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tm... | 8.178525 |
module cycloneive_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUP... | 8.178525 |
module cycloneive_mac_mult_internal (
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;... | 8.178525 |
module cycloneive_mac_out (
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneive_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = data... | 8.178525 |
module cycloneive_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "cycloneive_ddio_oe";
//Input P... | 6.784328 |
module cycloneive_pseudo_diff_out (
i,
o,
obar
);
parameter lpm_type = "cycloneive_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always @(i) begin
if (i == 1'b1) begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
... | 7.214659 |
module cycloneive_asmiblock (
dclkin,
scein,
oe,
sdoin,
data0out
);
input dclkin;
input scein;
input oe;
input sdoin;
output data0out;
parameter lpm_type = "cycloneive_asmiblock";
parameter enable_sim = "false";
wire dclk_wire, ncs, data0;
assign dclk_wire = (oe === 1'b0) ? dcl... | 6.871751 |
module cycloneive_rublock (
clk,
shiftnld,
captnupdt,
regin,
rsttimer,
rconfig,
regout
);
parameter sim_init_config = "factory";
parameter sim_init_watchdog_value = 0;
parameter sim_init_status = 0;
parameter lpm_type = "cycloneive_rublock";
input clk;
input shiftnld;
input c... | 6.505394 |
module cycloneive_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout
);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneive_crcblock";
endmodul... | 6.844914 |
module cycloneive_oscillator (
oscena,
clkout
);
parameter lpm_type = "cycloneive_oscillator";
input oscena;
output clkout;
// LOCAL_PARAMETERS_BEGIN
parameter OSC_PW = 6250; // fixed 80HZ running clock
// LOCAL_PARAMETERS_END
// INTERNAL wire
reg int_osc; // internal oscillator
spec... | 7.338529 |
module cycloneiv_mux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf (A_in, A);
buf (B_in, B);
buf (S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1)... | 6.609348 |
module cycloneiv_mux41 (
MO,
IN0,
IN1,
IN2,
IN3,
S
);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf (IN0_in, IN0);
buf (IN1_in, IN1);
buf (IN2_in, IN2);
buf (... | 6.609348 |
module cycloneiv_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.74319 |
module cycloneiv_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.581385 |
module cycloneiv_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.490658 |
module cycloneiv_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.917969 |
module cycloneiv_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 6.900127 |
module cycloneiv_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter dont_touch = "off";
... | 7.431884 |
module cycloneiv_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "cycloneiv_ddio_oe";
//Input Por... | 6.667407 |
module cycloneiv_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg ... | 6.993445 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiv_ram_register (
d,
clk,
aclr,
devclrn,
... | 7.458522 |
module cycloneiv_mac_data_reg (
clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tmp... | 8.164588 |
module cycloneiv_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUPs... | 8.164588 |
module cycloneiv_mac_mult_internal (
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
... | 8.164588 |
module cycloneiv_mac_out (
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneiv_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_... | 8.164588 |
module cycloneiv_pseudo_diff_out (
i,
o,
obar
);
parameter lpm_type = "cycloneiv_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always @(i) begin
if (i == 1'b1) begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
... | 6.997822 |
module cycloneiv_rublock (
clk,
shiftnld,
captnupdt,
regin,
rsttimer,
rconfig,
regout
);
parameter sim_init_config = "factory";
parameter sim_init_watchdog_value = 0;
parameter sim_init_status = 0;
parameter sim_init_config_is_application = "false";
parameter sim_init_watchdog_ena... | 6.90405 |
module cycloneiv_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout
);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneiv_crcblock";
endmodule
... | 6.686316 |
module cycloneiv_oscillator (
oscena,
observableoutputport,
clkout
);
parameter lpm_type = "cycloneiv_oscillator";
input oscena;
output observableoutputport;
output clkout;
// LOCAL_PARAMETERS_BEGIN
parameter OSC_PW = 6250; // fixed 80HZ running clock
// LOCAL_PARAMETERS_END
// INTER... | 6.928734 |
module cycloneiv_asmiblock (
dclkin,
scein,
oe,
sdoin,
data0out
);
input dclkin;
input scein;
input oe;
input sdoin;
output data0out;
parameter lpm_type = "cycloneiv_asmiblock";
parameter enable_sim = "false";
wire dclk_wire, ncs, data0;
assign dclk_wire = (oe === 1'b0) ? dclki... | 7.120613 |
module cycloneiv_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begi... | 6.56787 |
module cycloneiv_post_divider (
clk,
reset,
cout
);
// PARAMETER
parameter dpa_divider = 1;
// INPUT PORTS
input clk;
input reset;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
... | 7.273936 |
module cycloneiv_hssi_tx_pma_sub_reg (
input wire clk,
input tri1 ena,
input wire d,
input tri1 clrn,
input tri1 prn,
output wire q
);
// BUFFER INPUTS
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
$setuphold(posedge clk, d, 0, 0);
(posedge cl... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_out_block #(
parameter bypass_serializer = "false",
parameter invert_clock = "false",
parameter use_falling_clock_edge = "false"
) (
input wire clk,
input wire datain,
input wire devclrn,
input wire devpor,
output wire dataout
);
// INTERNAL VARIAB... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_parallel_register #(
parameter channel_width = 4
) (
input wire clk,
input wire enable,
input wire [channel_width - 1:0] datain,
input wire devclrn,
input wire devpor,
output wire [channel_width - 1:0] dataout
);
// INTERNAL VARIABLES AND NETS
reg clk_la... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 (
input wire clk,
input wire reset_n,
output reg clkout
);
wire next_val;
// SPR:328849 - initialize clkout because reset_n is optional
initial clkout = 1'b0;
// state definition
always @(posedge clk or negedge reset_n) begin
if (!reset... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen (
input wire clk,
input wire reset_n,
output wire clkout
);
wire clk8m, clk4m, clk2m;
cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 div_1 (
.clk(clk),
.reset_n(reset_n),
.clkout(clk8m)
);
cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync (
input wire clk,
input wire reset_n,
input wire rcv_det,
output reg rcv_det_out
); // synthesis syn_black_box
reg rcv_det_mid;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
rcv_det_out <= 1'b0;
rcv_d... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm (
input wire clk,
input wire reset_n,
input wire com_pass,
input wire probe_pass,
output reg det_on,
output reg detect_valid,
output reg rcv_found
); // synthesis syn_black_box
reg [2:0] STATE;
reg [2:0] NEXTSTATE;
reg... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control (
input wire clk,
input wire rcv_det_en,
input wire rcv_det_pdb,
input wire com_pass,
input wire probe_pass,
output wire det_on,
output wire detect_valid,
output wire rcv_found
);
wire rcv_det_syn;
cycloneiv_hssi_tx_pm... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital (
input wire oscclk,
input wire rcv_det_pdb,
input wire rcv_det_en,
input wire com_pass,
input wire probe_pass,
output wire det_on,
output wire detect_valid,
output wire rcv_found
);
wire clk;
cycloneiv_hssi_tx_pma_sub... | 8.011405 |
module is the behavior model for rx_det block
// If there is rx - set parameter RX_EXIST to 1, set to 0 otherwise
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det
//
// Description : Receiver detect
//
////////////////////////////... | 7.595207 |
module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneiv_hssi_rx_pma_sub_deser
#(
parameter channel_width = 8
)
(
input wire fclk,
input wire... | 6.910834 |
module cycloneiv_hssi_rx_pma_sub_clkdiv (
input wire rxfclk,
input wire clr,
input wire [3:0] deser_fact,
output reg loaden,
output reg clkdivrx
);
integer clk_count;
reg first_clkcount;
reg clkdivrx_prev;
reg rxloaden;
initial begin
first_clkcount = 1'b0;
clkdivrx_prev = 1'b0;
... | 8.011405 |
module cycloneiv_hssi_pcs_reset (
hard_reset,
clk_2_b,
refclk_b_in,
scan_mode,
rxpcs_rst,
txpcs_rst,
rxrst_int,
txrst_int
);
input hard_reset;
input clk_2_b;
input refclk_b_in;
input scan_mode;
input rxpcs_rst;
input txpcs_rst;
output rxrst_int;
output txrst_int;
reg... | 8.011405 |
module cycloneiv_hssi_tx_digis_txclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_rx_digis_rxclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_clk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_clk_ctl (
pclk_pma,
refclk_dig,
mdc,
ser_clk,
ser_mode,
scan_mode,
scan_clk,
rfreerun_centrl,
rcentrl_clk_sel,
rrefclk_out_div2,
hard_reset,
txrst,
refclk_pma_out,
mdc_b,
refclk_out,
rauto_speed_ena,
rfreq_sel,
gen2ngen1_b... | 8.011405 |
module cycloneiv_hssi_cmu_rxclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_txclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode ... | 8.011405 |
module cycloneiv_hssi_cmu_dprio_bit_pma (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
pma_cram_test,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode;... | 8.011405 |
module cycloneiv_hssi_calibration_block (
clk,
powerdn,
testctrl,
calibrationstatus,
nonusertocmu
);
// *** End of Section 3 ***
// *** Section 4 -- Parameter declarations and default values ***
parameter lpm_type = "cycloneiv_hssi_calibration_block";
parameter cont_cal_mode = "false";
... | 8.011405 |
module cycloneiv_pciehip_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode e... | 7.364512 |
module cycloneiv_pciehip_compute_bit (
input wire [63:0] datain,
input wire s,
output wire r
);
// begin
assign r = datain[0] ^ datain[1] ^ datain[2] ^ datain[3] ^ datain[4] ^ datain[5] ^ datain[6] ^ datain[7] ^ datain[10] ^ datain[13] ^ datain[14] ^ datain[17] ^
datain[2... | 7.364512 |
module cycloneiv_pciehip_ecc_gen (
input wire [63:0] datain, // Data on which ECC is required
input wire [ 7:0] syndrome, // Syndrome uses 8'h00 while generating
output wire [ 7:0] result // Result
);
//-----------------------------------------------------------------------------
// Instan... | 7.364512 |
module cycloneiv_pciehip_ecc_decoder (
flag,
derr,
derr_cor
);
input [2:0] flag;
output derr;
output derr_cor;
assign derr = flag[2] & ~(flag[1]) & flag[0];
assign derr_cor = ~(flag[2]) & flag[1] & flag[0];
endmodule
| 7.364512 |
module cycloneiv_pciehip_pulse_ext (
core_clk,
rstn,
srst,
derr_cor,
derr_cor_ext
);
input core_clk;
input rstn;
input srst;
input derr_cor;
output derr_cor_ext;
reg n1, derr_cor_ext;
wire n2;
// Pulse width extender
always @(negedge rstn or posedge core_clk) begin
if (rstn... | 7.364512 |
module cycloneiv_pciehip_pciexp_dcfiforam (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q
);
parameter addr_width = 4;
parameter data_width = 32;
input [data_width - 1:0] data;
input wren;
input [addr_width - 1:0] wraddress;
input [addr_width - 1:0] rdaddress;
input wr... | 7.364512 |
module cycloneiv_pciehip_pciexp_dcram_rtry (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input ... | 7.364512 |
module cycloneiv_pciehip_pciexp_dcram_rxvc (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input ... | 7.364512 |
module cyclonev_mux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf (A_in, A);
buf (B_in, B);
buf (S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ... | 6.709715 |
module cyclonev_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.465056 |
module cyclonev_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.523731 |
module cyclonev_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.226678 |
module cyclonev_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.821261 |
module cyclonev_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 7.151514 |
module
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclonev_mlab_cell
(
portadatain,
portaaddr,
portabyteenamasks,
portbaddr,
clk0, clk1,
ena0, ena1,
ena2,
clr,
devclrn,
devpor,
portbdataout
);
... | 8.13663 |
module cyclonev_io_obuf (
i,
oe,
dynamicterminationcontrol,
seriesterminationcontrol,
parallelterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter shift_series_termination_control = "false";
... | 7.364407 |
module cyclonev_ddio_oe (
oe,
octreadcontrol,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "cyclonev_ddio_o... | 7.605688 |
module cyclonev_pseudo_diff_out (
i,
o,
obar,
// ports new for StratixV
dtcin,
dtc,
dtcbar,
oein,
oeout,
oebout
);
parameter lpm_type = "cyclonev_pseudo_diff_out";
input i;
output o;
output obar;
// ports new for StratixV
input dtcin, oein;
output dtc, dtcbar, oeo... | 7.259989 |
module cyclonev_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg main... | 8.828183 |
module cyclonev_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 202;
// INTERNAL VARIABLES
reg dout_tmp;
reg... | 8.828183 |
module cyclonev_bias_block (
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "cyclonev_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;
r... | 8.828183 |
module cyclonev_dll_offset_ctrl (
clk,
offsetdelayctrlin,
offset,
addnsub,
aload,
offsetctrlout,
offsettestout
);
parameter use_offset = "false";
parameter static_offset = 0;
parameter use_pvt_compensation = "false";
input clk;
input [6:0] offsetdelayctrlin;
input [6:0] offset... | 7.0951 |
module cyclonev_dll (
clk,
upndnin,
upndninclkena,
delayctrlout,
dqsupdate,
dftcore,
aload,
upndnout,
locked,
dffin
);
parameter input_frequency = "0 MHz";
parameter delayctrlout_mode = "normal";
parameter jitter_reduction = "false";
parameter use_upndn... | 7.627928 |
module cyclonev_input_phase_alignment (
datain,
levelingclk,
zerophaseclk,
areset,
enainputcycledelay,
enaphasetransferreg,
dataout,
dffin,
dff1t,
dffphasetransfer
);
parameter power_up = "low";
parameter async_mode = "no_reset";
parameter add_input_cycle_delay = "false";
... | 7.398664 |
module cyclonev_termination_logic (
s2pload,
serdata,
scanenable,
scanclk,
enser,
seriesterminationcontrol,
parallelterminationcontrol
);
parameter lpm_type = "cyclonev_termination_logic";
parameter a_iob_oct_test = "a_iob_oct_test_off";
input s2pload;
input serdata;
input scane... | 6.934247 |
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