code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module data_hazard_unit (
//data read from regfiles
input [31:0] reg_rs_data,
input [31:0] reg_rt_data,
//data from if stage
input [ 4:0] de_rs_addr,
input [ 4:0] de_rt_addr,
//data from exe stage
input exe_reg_en,
input [ 4:0] exe_reg_waddr,
input [31:0] exe_reg_wd... | 7.861513 |
module Data_holder (
input [31:0] in,
input clk,
(* KEEP = "TRUE" *) output reg [31:0] out
);
always @(negedge clk) begin
out <= in;
end
endmodule
| 7.30182 |
module data_hs_phy (
/* byte clock */
input wire byte_clk,
/* bit clock: 4x byte clock */
input wire bit_clk,
/* reset signal */
input wire byte_rst,
bit_rst,
/* data */
input wire [7:0] data,
/* enable signal */
input wire enable,
/* controls the tri-stating of the hs l... | 7.450477 |
module fwdunit (
input [4:0] idex_rs1,
input [4:0] idex_rs2,
input exmem_RegWrite,
input [4:0] exmem_rd,
input memwb_RegWrite,
input [4:0] memwb_rd,
input [1:0] ALUOp,
output reg [1:0] forwardA,
output reg [1:0] forwardB
);
//Limitations of the module
// 1. It assumes all ins... | 7.222782 |
module data_in (
input DCK,
input rst,
input DAI,
input DEN,
output reg [ 8:0] AB,
output reg [15:0] DB
);
reg [15:0] cnt_DCK;
reg [ 8:0] cnt_pixel;
reg [15:0] data_in_tmp;
always @(posedge DCK, posedge rst) begin
if (rst) cnt_DCK <= 16'b0;
else if (DEN) cnt_DCK <= cnt_DCK + ... | 6.811861 |
module Data_Integration (
input clk,
input rst_n,
input [15:0] data_in,
output [15:0] data_out
);
parameter hpixel_end = 11'd800, vline_end = 11'd480;
reg [10:0] hcount;
reg [10:0] vcount;
wire hcount_ov; //行扫描一行结束时为1
wire vcount_ov; //列扫描一行结束时为1
assign hcount_ov = (hcount == hpixe... | 6.95298 |
module data_invert (
ram_invert,
odd,
even,
out
);
input ram_invert;
// input BHE, A0;
input [7:0] odd, even;
output [15:0] out;
// reg [7:0]odd_r, even_r;
// always @(even)
// begin
// even_r<=even;
// end
// always @(odd)
// begin
// odd_r<=odd;
// end
// assign out ... | 6.640724 |
module data_in_re (
sel,
choose,
result,
data,
pc,
lo,
Byte,
lower,
set,
we_data
);
input [1:0] sel, choose;
input [31:0] result, data, pc, lo;
input Byte, lower, set;
output [31:0] we_data;
wire [31:0] pc4, D1, DataB, D2; //
wire ss; //set成功
wire [7:0] dataB; /... | 6.701701 |
module data_in_redir_labbkb_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 11;
parameter MEM_SIZE = 1125;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *)... | 7.018963 |
module data_in_redir_labbkb (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd1125;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:... | 7.018963 |
module is the sub level RTL code of SDRAM Controller ASIC verilog
code. It is the Controller input Data Port register block.
Hossein Amidi
(C) April 2002
*********************************************************/
// DEFINES
`timescale 1ns / 10ps
module data_in_reg(// Input
reset,
clk0,
dm,
... | 6.572195 |
module data_join #(
parameter INPUT_WIDTH = 4,
parameter OUTPUT_WIDTH = 8,
parameter CNT_WIDTH = 1
) (
input clk,
input rstn,
input input_valid,
output input_enable,
output output_valid,
input output_enable,
input [INPUT_WIDTH - 1 : 0] data_in,
output [OUTPUT_WI... | 8.031128 |
module data_lane (
/* byte clock */
input wire byte_clk,
/* bit clock: 4x byte clock */
input wire bit_clk,
/* reset signals */
input wire byte_rst,
bit_rst,
/* data */
input wire [7:0] data,
/* enable signal (valid data present) */
input wire enable,
/* data accepted, a... | 8.195805 |
module data_load (
input clk,
input rst_n,
input [7:0] d_in,
input load,
output reg [9215:0] buffer,
output ack
);
reg [10:0] count_load;
always @(posedge clk or negedge rst_n)
if (!rst_n) count_load <= 11'b0;
else if (ack) count_load <= 0;
else if (load) count_load <= count_loa... | 6.8957 |
module data_mem (
input [9:0] a, //read and write (dm_addr)
input [31:0] d, //write data
input [7:0] dpra, //read only (im_addr)
input clk,
input [1:0] we, //dm_wr_ctrl
output reg [31:0] spo, //mem[a]
output [31:0] dpo, //mem[dpra]
//supplementary
input [2:0] dm_rd_ctrl
);
re... | 7.214114 |
module Data_Memory (
CLK,
WR,
A,
D_IN,
Q
);
input CLK, WR;
input [3:0] A;
input [3:0] D_IN;
output [3:0] Q;
// write your code for reading/writing
reg [3:0] SRAM[16:0];
always @(posedge CLK) begin
SRAM[0] = 4'b0010;
SRAM[1] = 4'b0011;
SRAM[2] = 4'b0000;
SRAM[3] = 4'b00... | 7.239913 |
module DATA_MEMORY(
input clk,
input [31:0] Bus_A, [31:0] Bus_B,
input MW1,
output reg [31:0] data_out
);
reg [31:0] mem_data [0:31];
always @(posedge clk)
begin
case(MW1)
0: data_out = mem_data[Bus_A];
1: data_out = mem_data[Bus_B... | 7.17721 |
module data_memory_tb;
// reg clk;
reg [31:0] Bus_A, Bus_B;
reg MW1;
wire [15:0] data_out;
DATA_MEMORY uut (
.Bus_A(Bus_A),
.Bus_B(Bus_B),
.MW1(MW1),
.data_out(data_out)
);
// always #50 clk = ~clk;
integer i;
initial begin
// clk = 0;
Bus_A = 0;
#100;
... | 6.648716 |
module Data_Memory_Block (
output [7:0] ans_dm,
input [7:0] ans_ex,
input [7:0] DM_data,
input mem_rw_ex,
input mem_en_ex,
input mem_mux_sel_dm,
input reset,
input clk
);
////////////////////////////////////////////////Declartions////////////////////////////////////////////////////////... | 7.659134 |
module: Data_Memory_Block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Data_Memory_Block_tb;
// Inputs
reg [7:0] ans_ex;
reg [7:0] DM_data;
reg mem_rw_ex;
reg mem_en_ex;
re... | 7.225528 |
module data_memory_block_testbench ();
wire [31:0] read_data;
reg [31:0] adress; //adress will be 18 bits
reg [31:0] write_data;
reg mem_read, mem_write, clk;
data_memory_block my_memory (
read_data,
adress[17:0],
write_data,
mem_write,
mem_read,
clk
);
initial b... | 7.009558 |
module data_memory_test ();
reg i_clk, i_rst_n, i_write, i_read;
reg [`ADDR_WIDTH-1:0] i_addr;
reg [`D_WIDTH-1:0] i_data;
wire [`D_WIDTH-1:0] o_data;
///instantiating the memory module ///
DATA_MEM DUT (
i_clk,
i_rst_n,
i_addr,
i_write,
i_data,
i_read,
o_data
);... | 6.648716 |
module Data_Memory_testbench ();
parameter BITSIZE = 64;
reg [BITSIZE - 1:0] address, writeData;
reg memWrite, memRead;
reg clk, rst;
wire [BITSIZE-1:0] readData;
Data_Memory DM (
.address(address),
.writeData(writeData),
.memWrite(memWrite),
.memRead(memRead),
.clk(clk),
... | 6.873171 |
module data_mem_alt #(parameter DATA_WIDTH = 32, ADDR_WIDTH = 29, MEM_DEPTH = 1 << ADDR_WIDTH)
(
input [ADDR_WIDTH - 1:0] wr_addr, rd_addr,
input [DATA_WIDTH - 1:0] wr_data,
input clk, wr_en, rd_en, reset,
output reg rd_data_valid, wr_rdy, rd_rdy,
output reg [DATA_WIDTH - 1:0] rd_data
);
/... | 7.879198 |
module data_mem (
clk,
resetn,
en,
stalled,
d_writedata,
d_address,
op,
d_loadresult,
ecause,
boot_daddr,
boot_ddata,
boot_dwe,
bus_address,
bus_byteen,
bus_we,
bus_en,
bus_writedata,
bus_readdata,
bus_wait,
bus_ecause
);
parameter D_... | 7.214114 |
module store_data_translator (
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout
); // shifted data to coincide with address
parameter WIDTH = 32;
input [WIDTH-1:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d... | 8.280191 |
module load_data_translator (
d_readdatain,
d_address,
load_size,
load_sign_ext,
d_loadresult
);
parameter WIDTH = 32;
input [WIDTH-1:0] d_readdatain;
input [1:0] d_address;
input [1:0] load_size;
input load_sign_ext;
output [WIDTH-1:0] d_loadresult;
reg [WIDTH-1:0] d_loadresult;
... | 9.105161 |
module data_mem (
input clk,
input we_i,
input [`dm_addr_width-1:0] addr_i,
input [ 31:0] din_i,
output reg [ 31:0] dout_o
);
reg [31:0] ram0 [0:`dm_depth-1];
reg [31:0] dout_r0;
always@ (posedge clk) ... | 7.214114 |
module data_mem (
clk,
resetn,
en,
stalled,
d_writedata,
d_address,
boot_daddr,
boot_ddata,
boot_dwe,
op,
d_loadresult
);
parameter D_ADDRESSWIDTH = 32;
parameter DM_DATAWIDTH = 32;
parameter DM_BYTEENAWIDTH = 4; // usually should be DM_DATAWIDTH/8
//parameter DM_A... | 7.214114 |
module store_data_translator (
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout
); // shifted data to coincide with address
parameter WIDTH = 32;
input [WIDTH-1:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d... | 8.280191 |
module load_data_translator (
d_readdatain,
d_address,
load_size,
load_sign_ext,
d_loadresult
);
parameter WIDTH = 32;
input [WIDTH-1:0] d_readdatain;
input [1:0] d_address;
input [1:0] load_size;
input load_sign_ext;
output [WIDTH-1:0] d_loadresult;
reg [WIDTH-1:0] d_loadresult;
... | 9.105161 |
module data_mem_tb ();
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 8;
localparam CLK_PERIOD = 20;
reg [(DATA_WIDTH - 1):0] data;
reg [ (ADDR_WIDTH-1):0] addr;
reg wEn, clk, rEn;
wire [(DATA_WIDTH-1):0] mem_out;
/////create clock/////
initial begin
clk = 1'b0;
forever begin
#(C... | 6.733638 |
module: data_mem
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
`include "mips_16_defs.v"
module data_mem_tb_0_v;
// Inputs
reg clk;
reg [15:0] mem_access_addr;
reg ... | 6.99097 |
module data_mem_wrapper (
input wire clock,
input wire [31:0] address,
input wire [31:0] data_in,
input wire read_write,
input wire enable,
input wire access_size,
input wire byte_s,
output wire [31:0] data_mem_out,
output wire busy
);
reg [31:0] write_back_mem_in;
wire [31:... | 7.121152 |
module: MLRU
// fuction: pseudo mbit LRU (mLRU)
// author: Zong-Ru Li
// date: 03/28/2021
// desription: to be done
//===============================================
module MLRU(
input clk,
input rst_n,
input i_valid_1,
input i_valid_2,
input [3:0] I_BANK_0,
input [3:0] I_BANK_1,
input [3:... | 7.230503 |
module data_mod (
input wire clk,
input wire reset_n,
input wire rdy,
input wire [7:0] data_in,
output reg [4:0] dmod,
output reg mod_en,
output wire rd
);
parameter zeroo = 4'hf, zero = 4'h0, one = 4'h1, two = 4'h2, there = 4'h3, four = 4'h4, five = 4'h... | 6.519149 |
module has 32 bits. However, it is actually a complex number. Thus getting its modulus to
be the length of the bar is necessary. In this module, an ip-core called sqrt is used to ge the desquare number
of the square sum of the real and imaginary part.
also, the incoming signal fft_sop, fft_eop, as well as fft_valid ar... | 7.469062 |
module DATA_MUX (
input SELECTOR,
input [63:0] DATA_A,
input [63:0] DATA_B,
output [63:0] OUT
);
assign OUT = (SELECTOR == 0) ? DATA_A : DATA_B;
endmodule
| 7.699929 |
module data_mux_1 (
input clk,
input [7:0] selector,
input [15:0] data_300_1,
input [15:0] data_301_1,
input [15:0] data_302_1,
input [15:0] data_303_1,
input [15:0] data_304_1,
input [15:0] data_305_1,
input [15:0] data_306_1,
input [15:0] data_307_1,
input [15:0] dat... | 7.528147 |
module data_mux_2 (
input clk,
input [ 7:0] selector,
input [15:0] data_300_2,
input [15:0] data_301_2,
input [15:0] data_302_2,
input [15:0] data_303_2,
input [15:0] data_304_2,
input [15:0] data_305_2,
input [15:0] data_306_2,
... | 7.906851 |
module data_mux_2_1 (
input in0,
input in1,
input sel,
output out
);
`ifdef BEHAVIORAL
assign out = sel ? in1 : in0;
`else
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
$display("ERROR : %m : replace this section with user technol... | 6.55578 |
module data_mux3_1 (
in_1,
in_2,
in_3,
sel,
out
);
parameter data_wl = 16;
input [data_wl-1:0] in_1;
input [data_wl-1:0] in_2;
input [data_wl-1:0] in_3;
input [1:0] sel; //selection of input 1->in_1 and so on
output [data_wl-1:0] out;
reg [data_wl-1:0] out;
always @(in_1 or in_2... | 8.256077 |
module data_mux_reg (
data,
aluout,
lui,
pcaddress,
MemToReg,
finalres
);
input [0:31] data, aluout, lui, pcaddress;
input [0:1] MemToReg;
output [0:31] finalres;
assign finalres = MemToReg == 0? aluout:
MemToReg == 2? lui:
MemToReg == 3? pcaddress:
MemToReg == 1? data : 0;
endmo... | 7.622214 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module Data_organizer #(
parameter size = 32
) (
input [size-1 : 0] data_in,
input [2:0] Type_sel,
output [size-1 : 0] data_out
);
wire [size-1 : 0] mask1;
wire [size-1 : 0] mask2;
wire [1 : 0] size_sel;
wire sign;
assign size_sel = Type_sel[1:0];
assign sign = ~Type_sel[2];
defparam M... | 8.149525 |
module data_out (
input wire clk_lcd,
output wire [7:0] R,
output wire [7:0] G,
output wire [7:0] B,
input wire den,
input wire [10:0] hsync,
input wire [10:0] vsync
);
reg [7:0] r_R;
reg [7:0] r_G;
reg [7:0] r_B;
parameter HSYNC_BLANK_WIDTH = 256; // thb
parameter HSYNC_WIDTH =... | 6.867929 |
module data_pack #(
parameter be_parallelism = 32,
parameter parallelism_per_control = 4,
parameter data_width = 16,
parameter BAND_WIDTH = 256
) (
//////////////////clock & control signals/////////////////
input wire clk,
input wire rst_n,
input wire is_pad,
//////////////////Up da... | 7.8977 |
module data_packer #(
// ******************************************************************
// Parameters
// ******************************************************************
parameter integer IN_WIDTH = 64,
parameter integer OUT_WIDTH = 128,
parameter integer OP_WIDTH = 16
) (
// *******... | 7.333013 |
module data_packet_fifo (
input reset,
input clock,
input [31:0] ram_data_in,
input write_enable,
output reg have_space,
output reg [31:0] ram_data_out,
output reg pkt_waiting,
output reg isfull,
output reg [ 1:0] usb_ram_... | 7.320175 |
module data_path (
input clk,
input rst,
input [7:0] data_in,
input insel,
input we,
input [2:0] raa,
input [2:0] rab,
input [2:0] wa,
input [2:0] opalu,
input [2:0] sh,
input selpc,
input selk,
input ldpc,
input ldflag,
input wr_en,
rd_en,
input [10:0... | 6.77594 |
module Data_Path_RV32I #(
parameter n = 32
) (
input clk,
rst,
shift_done,
input jalr_ctl,
jump,
wr_mem,
store_sel,
alu_src,
wr_reg,
input [2:0] mux_sel_reg_file,
branch,
input [3:0] alu_opcode,
input [n-1:0] dataout_mem, // output of dmem
input [n-1:0] instr... | 8.593321 |
module data_port (
input clk,
output [7:0] data_out,
input input_pin_0,
input input_pin_1,
input input_pin_2,
input input_pin_3,
input input_pin_4,
input input_pin_5,
input input_pin_6,
input input_pin_7
);
wire [7:0] data;
assign data[0] = input_pin_0;
assign data[1] = ... | 7.089223 |
module is used LFSR to generate random data for memory
// data write or memory data read comparison.The first data is
// seeded by the input prbs_seed_i which is connected to memory address.
//Reference:
//Revision History:
//**************************************************************************... | 7.856982 |
module data_producer #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
parameter TCQ = 1
) (
// pcie Core
//input pcie_user_clk,
//input pcie_user_rst_n,
//DMA input data channel
//input data_clk,
input clk_100,
input [ ... | 6.563972 |
module data_ram (
input wire ce,
input wire we,
input wire [19:0] addr,
input wire [3:0] sel,
inout wire [`WordBus] data,
output reg ack
);
reg [`WordBus] data_mem[0:`DataMemNum-1];
initial $readmemh("inst_rom.data", data_mem);
reg [`WordBus] data_o;
assign data = (we == 0) ? data_o : ... | 7.846612 |
module data_ram_delay (
input s_aclk,
input s_aresetn,
input [3:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb... | 7.268468 |
module: data_ram
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module data_ram_tb;
// Inputs
reg clk;
reg [9:0] address;
reg memRead;
reg memWrite;
reg [63:0] writeData;
reg cs;
... | 6.889428 |
module data_rate (
clock,
reset,
trigger,
output_data_rate
);
input clock, reset;
input trigger;
output reg output_data_rate;
reg [399:0] state;
reg [ 15:0] counter;
reg [ 7:0] data1;
reg [ 7:0] data2;
reg [ 7:0] data3;
reg [ 7:0] data4;
reg [ 7:0] data5;
reg [ 7:0] data6;
... | 6.647685 |
module data_receive (
reset,
Rx_EN,
RxD,
Rx_sample_ENABLE,
Rx_DATA,
Rx_VALID,
Rx_PERROR,
Rx_FERROR
);
input reset;
input Rx_EN;
input RxD;
input Rx_sample_ENABLE;
output [7:0] Rx_DATA;
output Rx_VALID;
output Rx_PERROR;
output Rx_FERROR;
reg [7:0] Rx_DATA;
reg Rx_V... | 6.993301 |
module data_reciever (
input clk,
input [7:0] in_data,
input in_data_ready,
output reg [31:0] out_data,
output reg out_data_ready
);
reg [1:0] byte_counter;
initial begin
byte_counter = 0;
out_data = 0;
out_data_ready = 0;
end
always @(posedge clk) begin
if (out_data_ready... | 6.657619 |
module data_reciever_testbench;
reg clk;
reg [7:0] in_data;
reg in_data_ready;
wire [31:0] out_data;
wire out_data_ready;
data_reciever dut (
.clk(clk),
.in_data(in_data),
.in_data_ready(in_data_ready),
.out_data(out_data),
.out_data_ready(out_data_ready)
);
initial begi... | 6.657619 |
module ##########
/* This module is an asynchronous module which do modifications to the data memory outputs
according to the instruction */
`timescale 1ns/100ps
module Data_ref_module (
func3,
data_mem_in,
data_ref_out,
to_data_memory,
DATA2
);
input [2:0] func3;
input [31:0] data_mem_in,... | 8.355574 |
module data_reg (
clk,
reset,
data_on_dr,
dr_on_data,
load_dr
);
input clk;
input reset;
input load_dr;
input [7:0] data_on_dr;
output [7:0] dr_on_data;
reg [7:0] dr_on_data;
always @(posedge clk) begin : DR_Block
if (reset) dr_on_data <= 8'd0;
else begin
if (load_dr) dr... | 6.940476 |
module data_resolve (
input clk,
input rstn,
input [3:0] byte_gate,
input [3:0] found_sot,
input [3:0] hs_mode,
input [8:0] data_offs,
input [31:0] data,
output reg [15:0] byte_read,
output reg package_valid
);
wire [7:0] ecc_result;
csi_rx_hdr_ecc csi_rx_hdr_ecc_inst (
... | 7.14045 |
module Data_retrieve(Start,Tx_tick,Wen,Addr,fin);
input Start;
input Tx_tick;
output reg [15:0] Addr=16'b0;
output reg Wen=1'b0;
output reg fin=0;
reg STATE=0;
//always @(posedge Start)
//begin
//Wen<=~Wen;
//end
//always @(posedge Tx_tick)
//begin
// if (Addr==16'd65535)
// begin
// fin<=1;
// end
// Addr<=... | 7.114851 |
module Data_retriever (
clk,
addr,
wen,
fin,
start,
Tx_tick
);
input clk, Tx_tick, start;
output reg [17:0] addr = 18'b0;
output reg wen = 0;
output reg fin = 0;
reg flag = 0;
reg [1:0] STATE = 2'b00;
parameter IDLE = 2'b0;
parameter TRANSMITTING = 2'b01;
parameter DONE = 2'b... | 7.114851 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 22/7/2022 Mina Hanna final version
//---------------------------------------------... | 8.923686 |
module data_sampling (
input wire data_in,
input wire [4:0] prescale,
input wire [4:0] edge_cnt,
input wire en_sampler,
input wire clk,
input wire rst,
output wire sampled_bit
);
reg [2:0] register;
always @(posedge clk or negedge rst) begin
if (!r... | 7.169594 |
module data_sampling (
input wire clk,
input wire rx_in,
input wire [2:0] edge_cnt,
//input wire bit_cnt,
output reg sampled_bit
);
//internal
reg [2:0] temp;
//RTL
always @(posedge clk) begin
if (edge_cnt == 3'b011 /*| edge_cnt == 3'b100 | edge_cnt... | 7.169594 |
module Data_Screening (
data,
enable_out
);
input wire [3:0] data;
output wire enable_out;
assign enable_out = data[3:0] >= 4'd1 && data[3:0] <= 4'd3 ? 1 : 0;
endmodule
| 7.02663 |
module data_seeker ( // only 1 master may be waiting for rdata
input clk, // data comes with a clock
input reset,
input slave1,
input slave0,
input [1:0] stat1,
input [1:0] stat0,
output reg [31:0] rdata1,
output reg [31:0] rdata0,
output reg data_read0,
output reg data_rea... | 8.19356 |
module Data_Sel (
input [7:0] DataIn,
input [7:0] Direccion,
input [2:0] NUM,
input [7:0] RY,
input [7:0] Resultado,
input [2:0] SEL,
output reg [7:0] Dato_Registro
);
always @(*)
case (SEL)
0: Dato_Registro <= DataIn;
1: Dato_Registro <= Direccion;
2: Dato_Registro ... | 8.402518 |
module Data_Selector2 (
input [31:0] A,
B,
input Sign,
output reg [31:0] Y
);
always @(A or B or Sign) begin
Y = Sign ? B : A; //ѡźΪ1ѡAǰIJ
end
endmodule
| 7.78003 |
module Data_Selector3 (
input [4:0] A,
B,
C,
input [1:0] Sign,
output reg [4:0] Y
);
always @(A or B or C or Sign) begin
if (Sign == 2'b00) Y = A;
else if (Sign == 2'b01) Y = B;
else Y = C;
end
endmodule
| 7.78003 |
module Data_Selector4 (
input [4:0] A,
B,
C,
D,
input [1:0] Sign,
output [4:0] Y
);
if (Sign == 2'b00) assign Y = A;
else if (Sign == 2'b01) assign Y = B;
else if (Sign == 2'b10) assign Y = C;
else assign Y = D;
endmodule
| 7.78003 |
module Data_Sel_tb;
reg [7:0] DataIn;
reg [7:0] Direccion;
reg [2:0] NUM;
reg [7:0] RY;
reg [7:0] Resultado;
reg [2:0] SEL;
wire [7:0] Dato_Registro;
Data_Sel uut (
.DataIn(DataIn),
.Direccion(Direccion),
.NUM(NUM),
.RY(RY),
.Resultado(Resultado),
.SEL(SEL),
... | 6.985747 |
module Data_send (
input clk,
input rst,
input send_start, // Start to send data after this bit is set to 1
input tx_ready, // Send one byte of data after tx_ready
input [ 7:0] MEM_data,
output reg [13:0] MEM_read_sel,
ou... | 7.86435 |
module data_size_selector (
output reg [1:0] DataSize,
input [31:0] IR,
input [1:0] DSS
);
parameter WORD = 2'b10;
wire [1:0] misc_sel_out, reg_sel_out;
misc_sel misc (
misc_sel_out,
{IR[20], IR[6], IR[5]}
);
reg_sel reg_sel (
reg_sel_out,
IR[22]
);
always @(*) begin
... | 6.860563 |
module misc_sel (
output reg [1:0] dataSize,
input [2:0] LSH
);
parameter BYTE = 2'b00;
parameter HALF = 2'b01;
parameter DWORD = 2'b11;
always @(*) begin
case (LSH)
3'b000: dataSize = 0;
3'b001: dataSize = HALF;
3'b010: dataSize = DWORD;
3'b011: dataSize = DWORD;
3... | 7.148394 |
module reg_sel (
output reg [1:0] dataSize,
input B
);
parameter BYTE = 2'b00;
parameter WORD = 2'b10;
always @(*) begin
case (B)
1'b0: dataSize = WORD;
1'b1: dataSize = BYTE;
default: dataSize = 0;
endcase
end
endmodule
| 7.496041 |
module data_solve (
clk,
data,
ready,
nextdata_n,
asc,
count,
clra,
clrk,
realdata
);
input [7:0] data;
input ready, clk;
output reg nextdata_n;
output reg [7:0] count;
output reg [7:0] realdata;
output reg [7:0] asc;
output reg clra;
output reg clrk;
reg kill=0;
... | 7.281835 |
module data_sort (
input clk,
input rst_n,
input in_vld,
input signed [15:0] din,
output signed [15:0] dout,
output out_vld
);
parameter DATA_MIN = 16'h8000;
//----------
//cmd_path;
//----------
reg [4:0] cnt;
wire in_vld_rise;
reg in_vld_d;
wire direction;
wire cmp_en;
re... | 6.58141 |
module data_split #(
parameter INPUT_WIDTH = 8,
parameter OUTPUT_WIDTH = 4,
parameter CNT_WIDTH = 1
) (
input clk,
input rstn,
output input_enable,
input input_valid,
input output_enable,
output output_valid,
input [INPUT_WIDTH - 1 : 0] data_in,
output [OUTPUT_W... | 7.727141 |
module data_sram_like (
input wire clk,
input wire rst,
// input from cpu
input wire cpu_data_en,
input wire [3 : 0] cpu_data_wen,
input wire [ 31:0] cpu_data_addr,
input wire [ 31:0] cpu_data_wdata,
input wire cpu_longest_stall,
// output to cp... | 7.32893 |
module data_sram_to_sram_like (
input clk,
input rst,
//sram
input flush,
input [31:0] data_sram_wdata,
input [31:0] data_sram_addr,
input [ 3:0] data_sram_wen,
input data_sram_en,
output [31:0] data_sram_rdata,
output data_stall,
//sram_like
... | 8.042543 |
module: data_store
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module data_store_tb;
// Inputs
reg clk;
reg [31:0] lm_din;
reg [4:0] lm_addr;
reg lm_we;
reg [31:0] rm_din;
reg [... | 6.813616 |
module data_swap #(
parameter WIDTH = 32
) (
//OUTPUTS
output [WIDTH - 1:0] data_swap,
//INPUTS
input [WIDTH - 1:0] data_in,
input [1:0] swap_type
);
//=====================================================================================
// Swap Types
//===================================... | 6.690797 |
module data_swapper_64 (
input [2:0] swap_lanes,
input [63:0] i_tdata,
output [63:0] o_tdata
);
localparam SWAP_32B = 3'b100;
localparam SWAP_16B = 3'b010;
localparam SWAP_8B = 3'b001;
wire [63:0] data_p1, data_p2;
assign data_p1 = (|(swap_lanes & SWAP_32B)) ? {i_tdata[31:0], i_tdata[63:32]} :... | 6.657098 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 19/7/2022 Mina Hanna final version
//---------------------------------------------... | 8.923686 |
module data_sync_block #(
parameter C_NUM_SYNC_REGS = 5
) (
input wire clk,
input wire data_in,
output wire data_out
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{1'b1}};
//--------------------------------------------------------------... | 7.667525 |
module data_synchronizer (
input clock,
input reset,
input set_stb,
input [ 7:0] set_addr,
input [31:0] set_data,
input [31:0] xk_fft_core,
input dv_fft_core,
output [31:0] xk,
output dv_synchronizer
);
wire tc;
wire [15:0] q;
wi... | 7.377337 |
module data_sync_bk (
input rst_n,
output o_sync_out,
input i_ad_gclk,
input i_c1_ad_clk, //
input [15:0] i_c1_adi_din, //
input [15:0] i_c1_adq_din, //
input i_c1_ad_din_vl,
output [15:0] o_c1_adi_dout,
output [15:0] o_c1_adq_dout,
output o_dout_v... | 7.869864 |
module data_tag (
input clock,
input reset,
input strobe,
input enable,
output tag
);
reg strobe_en;
reg strobe_en_neg;
reg reset_int;
always @(posedge clock) begin
reset_int <= (~enable && strobe_en && strobe_en_neg) || reset;
end
assign tag = strobe_en && ~strobe_en_neg;
... | 7.523819 |
module data_tag2 (
input clock,
input reset,
input strobe,
input enable,
output tag
);
wire sync1;
wire sync2;
assign tag = sync1 && ~sync2;
synchronizer sync (
.snd_clk(clock),
.rcv_clk(strobe),
.snd_signal(enable),
.rcv_signal1(),
.rcv_signal2(sync1),
... | 7.002856 |
module data_tag_tb;
//test vector to load data from file
parameter TEST_VECTOR_LENGTH = 500;
parameter CLK_PER_2 = 10;
parameter ENABLE_PER = 5000;
parameter STROBE_PER = 50;
parameter SIM_TIME = 1e5;
reg clk, rst;
reg enable;
wire strobe;
wire tag;
initial begin
clk = 1'b1;
forever #(... | 6.706955 |
module Testbench_DM;
reg clk = 0;
reg clr = 1;
reg [ 2:0] wm = 3'b000;
reg [ 2:0] rm = 3'b000;
reg [(32-1):0] addr_t = 32'h8000_0000;
reg [(32-1):0] din_s = 0;
wire [(32-1):0] dout_s;
reg [ 9:0] opc_in;
Data dut (
.clk(clk),
.rst(clr),
.w_... | 6.584864 |
module data_test2 (
input rst, //reset
input clk,
output reg din_stb,
input [ 1:0] din_ready,
output reg [ 1:0] din_activate,
output reg [31:0] din,
input [23:0] din_size,
input dout_ready,
output reg dout_activate,
input [31:0] dout,
... | 6.67261 |
module data_top (
input wire rst,
input wire clk,
input wire tx_con_clk,
input wire up_clk,
input wire up_wr,
input wire up_rd,
input wire [32-1:0] up_addr,
input wire [31 : 0] up_data_wr,
output wire [31 : 0] up_data_rd,
input wire rgmi... | 6.607699 |
module data_to_alu (
input enrs1,
input enrs2,
input [31:0] rs1,
input [31:0] rs2,
input [11:0] imm,
output [31:0] data1,
output [31:0] data2
);
wire [31:0] immtemp = {imm, 20'h00000};
assign data1 = enrs1 ? rs1 : data1;
assign data2 = enrs2 ? rs2 : (immtemp >>> 20);
/* always ... | 6.681284 |
module DATA_TRANS (
input wire CLK_20M,
input wire CLK_50M,
input wire RESET_n,
input wire [15:0] DATA_IN_U10,
input wire [15:0] DATA_IN_U11,
input wire [15:0] DATA_IN_U12,
input wire [15:0] DATA_IN_U13,
input wire [15:0] DATA_IN_U14,
input wire [15:0] DATA_IN_U15,
input wire [1... | 6.648304 |
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