code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module data_transfer(
PCIe_CLK,
CONF_CLK,
TRN_RESET_N,
CONF_FIFO_CLR,
WR_RQST,
WR_DATA,
FIFO_EMPTY,
FIFO_PROG_FULL,
PAUSE,
CONF_ERROR,
RST_CONF_ERROR,
CONF_DATA,
CONF_ENABLE,
);
input PCIe_CLK;
input CONF_CLK;
input TRN_RESET_N;
input ... | 6.675523 |
module data_transmitter_testbench;
reg clk;
reg [31:0] in_data;
reg in_data_ready;
reg data_request;
wire [7:0] out_data;
wire out_data_ready;
data_transmitter dut (
.clk(clk),
.in_data(in_data),
.data_request(data_request),
.in_data_ready(in_data_ready),
.out_data(out_data... | 7.008558 |
module data_transmit_tb ();
reg clk, rst;
reg [24:0] data;
reg [11:0] addr;
reg data_valid;
always begin
#5 clk <= ~clk;
end
initial begin
clk <= 0;
rst <= 1;
#20 rst <= 0;
#10 data <= 25'd1200;
addr <= 12'd255;
#10 data_valid <= 1;
end
Data_Transmit DATA_TRANSMIT_0 (
... | 7.008558 |
module data_transmit_top (
input wire Sys_clk,
input wire rst_n,
input wire SW3,
input wire RX,
output wire TX,
output wire led_on
);
assign led_on = ~SW3; // Using Led To Denote
// -------------The CLK WIZARD
clk_wiz_0 clk_wiz_test (
// Clock out ports
.clk_out1(clk), ... | 7.008558 |
module data_trans_FIFO(
input wire reset_n, start, clk, byte,
input wire [7 : 0] data_in,
input wire rd_en,
output wire [7 : 0] data_o, //??????
output wire empty, //?????
output wire full
);
wire [7 : 0] data_o_in;
wire data_wr_en;
data_trans u2(.reset_n(reset_n),.star... | 6.666248 |
module data_trans_FIFO_mod(
input wire reset_n, start, clk, byte,
input wire [7 : 0] data_in,
output wire full,
output wire [4:0] dmod,
output wire mod_en
);
wire [7 : 0] data_o_in;
wire data_wr_en;
wire [7 : 0] data_o_ino;
wire empty;
wire rd_en;
data_trans u1(.reset_n(reset_n),.s... | 6.666248 |
module data_trans_FIFO_mod_tb;
reg reset_n, clk;
reg [7 : 0] data_in;
reg start, byt;
wire [4 : 0] data_mod;
wire mod_en, full;
data_trans_FIFO_mod umodulation (
.reset_n(reset_n),
.clk(clk),
.data_in(data_in),
.start(start),
.byte(byt),
.dmod(data_mod),
.mod_en(mod... | 6.666248 |
module data_trans_FIFO_tb();
reg clk,reset_n;
reg start,byte;
reg [7:0] data_in;
reg rd_en;
wire [7:0] data_o;
wire full;
wire empty;
integer i;
data_trans_FIFO u0(reset_n, start, clk, byte, data_in, rd_en, data_o, empty, full);
always #200 clk = ~clk;
initial begin
clk = 0;
reset_n = 0;
start = 0;
rd_en = 0;
@(po... | 6.666248 |
module data_unpacker #(
// ******************************************************************
// Parameters
// ******************************************************************
parameter integer IN_WIDTH = 128,
parameter integer OUT_WIDTH = 64
)
// *************************************************... | 7.85089 |
module Data_Width_Converter_tb;
reg [11:0] count;
reg clk, rst, enable, start_read;
wire [7:0] w_time, w_channels, tx_byte;
wire w_sample_clk_posedge, w_rollover, w_triggered_state, w_event, finished_read,r_ack, t_rdy, buffer_full, tx_DV, tx_active, tx_serial, tx_done, post_read;
wire [15:0] data;
Pulse... | 7.735042 |
module data_window_3x3 (
input clk,
input rst,
input [7:0] din,
output [7:0] dout1_1,
output [7:0] dout1_2,
output [7:0] dout1_3,
output [7:0] dout2_1,
output [7:0] dout2_2,
output [7:0] dout2_3,
output [7:0] dout3_1,
output [7:0] dout3_2,
output [7:0] dout3_3,
outpu... | 7.424201 |
module data_write (
user_input_data,
clk90,
reset90_r,
reset270_r,
write_enable,
write_en_val,
write_en_val1,
write_data_falling,
write_data_rising,
data_mask_f,
data_mask_r
);
input [143:0] user_input_data;
input clk90;
input reset90_r;
input reset270_r;
input w... | 6.576504 |
module Data_Writer (
clk,
Rx_tick,
Din,
Wen,
Addr,
Dout,
fin
);
input Rx_tick, clk;
input [7:0] Din;
output reg [15:0] Addr = 16'b0;
output reg [7:0] Dout;
output reg Wen = 1'b0;
output reg fin = 0;
reg flag = 0;
reg [1:0] STATE = 2'b0;
parameter IDLE = 2'b0;
parameter... | 6.81603 |
module Data_write_Decoder_Module (
//inputs
input [2:0] Data_write_address_,
input Enable_write_,
//outputs
output [7:0] Enabler
);
reg [7:0] enabler;
assign Enabler = enabler;
parameter
reg1 = 3'b000,
reg2 = 3'b001,
reg3 = 3'b010,
reg4 = 3'b011,
reg5 = 3'b100,
reg6 = 3'b101,
re... | 7.630186 |
module data_xdomain #(
parameter size = 16
) (
input clk_in,
input gate_in,
input [size-1:0] data_in,
input clk_out,
output reg gate_out,
output reg [size-1:0] data_out
);
initial gate_out = 0;
initial data_out = 0;
reg [size-1:0] data_latch = 0;
always @(posedge clk_in) if (gate_in... | 7.906634 |
module datetime (
input clk,
input rst,
input [31:0] addr_i,
output [31:0] data_o,
input [31:0] data_i,
input [ 1:0] sel_i,
input rd_i,
input we_i,
output ack_o
);
parameter CLOCK_FREQ = 100_000_000;
reg [31:0] unix_time_reg;
reg [31:0] counter;
... | 6.535024 |
module date_function_without_leap_year (
clk,
rst_before,
content_ctrl,
ssd_ctrl,
show
);
input clk, rst_before, content_ctrl;
output [3:0] ssd_ctrl;
output [7:0] show;
wire clk_1hz, rst;
wire [1:0] clk_quick;
wire [3:0] result1;
wire [3:0] result2;
wire [3:0] result3;
wire [3:0] ... | 6.835437 |
module date_memory (
clock_in,
address,
writeData,
memWrite,
memRead,
reset,
readData
);
input clock_in;
input [31:0] writeData;
input [31:0] address;
input memWrite;
input memRead;
input reset;
output [31:0] readData;
reg [31:0] readData;
reg [ 7:0] memFile [127:0];
i... | 7.139361 |
module Date_path (
input wire jump_dp,
mem_write_dp,
reg_write_dp,
reg_dest_dp,
alu_src_dp,
memtoreg_dp,
pcsrc_dp,
input wire [ 2:0] alu_control_dp,
input wire clk_dp,
reset_dp,
input wire [31:0] instr_dp,
read_data_dp,
output wire [31:0] pc_dp,
... | 7.015406 |
module DatMem (
chipSel,
clk,
addr,
dat,
write
);
input chipSel;
input clk;
input [7:0] addr;
inout [31:0] dat;
input write;
reg [31:0] DM[0:255];
wire x;
reg [31:0] outDat = 32'b0;
assign x = (~write & chipSel);
assign dat = x ? outDat : 32'bz;
always @(posedge clk) b... | 6.547877 |
module datop (
input CLK,
input RST,
output rd_en,
input [127:0] din,
input empty,
output reg [5:0] da1,
output reg [5:0] da2,
output reg da_valid
);
localparam s_idle = 1'd0;
localparam s_running = 1'd1;
reg state;
reg [127:0] d;
localparam... | 6.8954 |
module DAXI (
//AXI4-lite master memory interface
//AXI4-lite global signal
input ACLK,
input ARESETn,
//AXI4-lite Write Address Channel
output AWVALID,
input AWREADY,
output [`AXI_ADDR_WIDTH - 1 : 0] AWADDR,
output [ ... | 7.219813 |
module day4seqdec (
input a,
clk,
rst,
output reg y
);
parameter idle = 0;
parameter s0 = 1;
parameter s1 = 2;
parameter s2 = 3;
reg [1:0] state = idle;
always @(posedge clk) begin
case (state)
idle:
if (rst) begin
state = idle;
y <= 1'b0;
end else be... | 6.567274 |
module day4seqdec (
input a,
clk,
rst,
output reg y
);
parameter idle = 0;
parameter s0 = 1;
parameter s1 = 2;
parameter s2 = 3;
reg [1:0] state = idle;
always @(posedge clk) begin
case (state)
idle:
if (rst) begin
state = idle;
y <= 1'b0;
end else be... | 6.567274 |
module da_coder (
input wire [2:0] origin,
output reg [2:0] coded
);
always @(origin) begin
case (origin)
0: coded = 0;
1: coded = 4;
2: coded = 2;
3: coded = 6;
4: coded = 1;
5: coded = 5;
6: coded = 3;
7: coded = 7;
endcase
end
endmodule
| 7.971959 |
module da_converter (
input wire rst_n,
input wire real _28RFH,
input wire _FpPCH,
input wire _FmPCH,
output wire _pPCH,
output wire _mPCH,
input wire _pPGH,
input wire _mPGH,
output wire _TpPGH,
output wire _TmPGH,
input wire _DD0,
input wire _DD1,
input wire... | 7.054371 |
module da_ctrl (
input en,
input [13:0] din,
output dac_wrt,
output dac_clk,
output [13:0] dac_data
);
wire wrt_phase_delay;
wire clk_phase_delay;
assign dac_wrt = en ? wrt_phase_delay : 0;
assign dac_clk = en ? clk_phase_delay : 0;
assign dac_data = en ? din : 0;
endmodule
| 6.716497 |
module DA_CU (
clk,
rst_n,
data_in,
data_out,
REG1,
REG2,
state,
start
);
input clk, rst_n, start;
output [2:0] state;
input [3:0] data_in;
output [3:0] REG1, REG2;
output [3:0] data_out;
wire ld_1, ld_2, sel_1, op, en;
data_path DATAPATH (
clk,
rst_n,
se... | 6.779771 |
module DA_CU_TB ();
reg [3:0] data_in;
wire [2:0] state;
reg clk, rst_n, start;
wire [3:0] data_out;
wire [3:0] REG1, REG2;
DA_CU DUT (
clk,
rst_n,
data_in,
data_out,
REG1,
REG2,
state,
start
);
always #10 clk = ~clk;
initial begin
#0 clk = 0;
r... | 6.55121 |
module DA_I (
clk,
out_data,
out_da_data,
out_da_clk,
out_da_wr
);
input clk;
input [9:0] out_data;
output [9:0] out_da_data;
output out_da_clk;
output out_da_wr;
reg [9:0] data_temp;
always @(posedge clk) begin
data_temp <= {~out_data[9], out_data[8 : 0]}; //λȡ;
end
assi... | 6.768924 |
module DA_multiper #(
parameter ASIZE = 8,
parameter BSIZE = 8, //BSIZE should be smaller than ASIZE
parameter PSIZE = 3 // it will raise error ,if 2^PSIZE !>= BSIZE
) (
input clock,
input rst_n,
input [ ASIZE-1:0] adata,
input [ BSIZE-1:0... | 6.824566 |
module DA_multiper_tb;
reg clock = 1'b0;
reg rst_n = 1'b0;
always #5 clock = ~clock;
initial begin
repeat (5) @(posedge clock);
rst_n = 1'b1;
end
DA_multiper #(
.ASIZE(8),
.BSIZE(8), //BSIZE should be smaller than ASIZE
.PSIZE(3) // it will raise error ,if 2^PSIZE !>= BSIZE
... | 7.32665 |
module DA_out (
input [13:0] digital_sig, //要输出的数字量
input sys_clk,
input rst_n,
output [13:0] DA9764_data, //伸缩为14bit
output DA9764_clk //DA的时钟12.5Mhz
);
/*
**25MHz计数,生成DA转换时钟(12.5MHz)
*/
reg cnt_25m;
parameter CNT_25M = 2; //2*0.02us = 0.04us(25M)
always @(posedge sys_clk) be... | 7.519401 |
module da_regfile #(
parameter DATA_WIDTH = 17
) (
input wire clk,
input wire rst_n,
input wire wen,
input wire ren,
input wire [ 2:0] waddr,
input wire [ 2:0] raddr,
input wire [DATA_WIDTH-1:0... | 8.29708 |
module da_test (
input clk, //fpga clock:50MHz
input rst_n, //reset
input rx, //uart rx
output daclk, //da clock
output [11:0] dadata, //da data 12bit
output reg pw = 0,
output [ 3:0] led
);
//变量定义
reg [ 9:0] r... | 7.030358 |
module da_testbench ();
localparam DATA_WIDTH = 17;
localparam RF_DEPTH = 8;
reg clk;
reg rst_n;
reg [ RF_DEPTH-1:0] wen_ctrl;
reg [ RF_DEPTH-1:0] ren_ctrl;
reg [ 2:0] waddr_ctrl;
reg [ 2:0] raddr_ctrl;
reg [DATA_WIDTH-1:0] din_real;
reg [DAT... | 7.117706 |
module DA_VINCI (
DATA,
ADDR,
READ,
WRITE,
CLK,
RST
);
// Parameter for the memory initialization file name
parameter mem_init_file = "mem_content_01.dat";
// output list
output [`ADDRESS_INDEX_LIMIT:0] ADDR;
output READ, WRITE;
// input list
input CLK, RST;
// inout list
inout... | 8.094999 |
module DA_VINCI_TB;
// output list
wire [`ADDRESS_INDEX_LIMIT:0] ADDR;
wire READ, WRITE, CLK;
// inout list
wire [`DATA_INDEX_LIMIT:0] DATA;
// reset
reg RST;
// Clock generator instance
CLK_GENERATOR clk_gen_inst (.CLK(CLK));
// DA_VINCI v1.0 instance
//defparam da_vinci_inst.mem_init_file = "... | 6.951278 |
module DB3 (
clk,
rst,
in,
out,
state
);
input clk, rst, in; // input controlling the operation
output reg out; // output of FSM
output reg [1:0] state; // state variable
parameter A = 2'b00, //defining state parameters
B = 2'b01, C = 2'b10, D = 2'b11;
always @(posedge clk or neged... | 6.807126 |
module DB3_test;
reg clk, rst, in;
wire out;
wire [1:0] state;
DB3 db3 (
clk,
rst,
in,
out,
state
); // module instantiated
initial begin
$dumpfile("DB3.vcd"); // output gets stored in this file
$dumpvars(0, DB3_test); // output parameters to be stored
clk = 1'... | 6.770176 |
module DBDR (
input [31:0] inputData,
input CLK,
output reg [31:0] outputData
);
always @(posedge CLK) begin
outputData <= inputData;
end
endmodule
| 8.074241 |
module dbg #(
parameter DFE_OUTPUT_BW = 8,
parameter ACO_OUTPUT_BW = 8 * 13
)(
// clock and reset
input clk_i,
input rst_n_i,
// logic analyzer signals
input [127:0] la_data_in_i,
output [127:0] la_data_out_o,
inpu... | 6.99095 |
module dbg_bridge_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
/... | 7.349399 |
module dbg_comm (
SYS_CLK,
SYS_RSTN,
P_TMS,
P_TCK,
P_TRST,
P_TDI,
P_TDO
);
parameter Tp = 20;
output SYS_CLK;
output SYS_RSTN;
output P_TMS;
output P_TCK;
output P_TRST;
output P_TDI;
input P_TDO;
// Signal for the whole system
reg SYS_CLK;
reg SYS_RSTN;
// For ha... | 7.687121 |
module for use with VPI / network communication.
//
// Revision 1.1 2002/03/28 19:59:54 lampret
// Added bench directory
//
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
// Revision 1.3 2001/09/24 14:06:13 mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revisio... | 6.836922 |
module dbg_cpu_registers (
data_i,
we_i,
tck_i,
bp_i,
rst_i,
cpu_clk_i,
ctrl_reg_o,
cpu_stall_o,
cpu_rst_o
);
input [`DBG_CPU_CTRL_LEN -1:0] data_i;
input we_i;
input tck_i;
input bp_i;
input rst_i;
input cpu_clk_i;
output [`DBG_CPU_CTRL_LEN -1:0] ctrl_reg_o;
outpu... | 7.344241 |
module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 1
//
// Info: janz@easics.be (Jan Zegers)
// http://www.easics.com ... | 7.897638 |
module containing a synthesizable CRC function
// * polynomial: (0 1 2 8)
// * data width: 1
//
// Info: jand@easics.be (Jan Decaluwe)
// http://www.easics.com
///////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`in... | 7.897638 |
module dbg_dmem #(
parameter W = `WORD_WIDTH,
parameter DMEM_SIZE = 4096,
parameter DATA_SEGMENT = `WORD_WIDTH'h10010000 // .data segment, "do the os job"
) (
input wire clk,
rst,
input wire read_en,
input wire [W-1:0] read_addr,
output reg [W-1:0] read_data,
input wire write_en,
... | 7.998286 |
module dbg_imem #(
parameter W = `WORD_WIDTH,
parameter IMEM_SIZE = 128
) (
input wire clk,
rst,
input wire [W-1:0] addr,
output reg [W-1:0] data
);
// Instruction memory can only be addressed by words
reg [W-1:0] mem[IMEM_SIZE-1:0];
initial begin
$readmemh(`IMEM_SIM_FILE, mem);
/... | 7.228886 |
module ||
// History: ||
// 2019/5/29 ||
// First version ||
//===============================================================
`include "core_defines.vh"
`include "dbg_defines.vh"
module dbg_mode_ctrl (
input cpu_clk,
input cpu_rstn,
input step,
in... | 6.979048 |
module dbg_register (
data_in,
data_out,
write,
clk,
reset
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input write;
input clk;
input reset;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
a... | 7.908704 |
module dbg_sync_clk1_clk2 (
clk1,
clk2,
reset1,
reset2,
set2,
sync_out
);
parameter Tp = 1;
input clk1;
input clk2;
input reset1;
input reset2;
input set2;
output sync_out;
reg set2_q;
reg set2_q2;
reg set1_q;
reg set1_q2;
reg clear2_q;
reg clear2_q2;
reg s... | 6.714004 |
module half_dup_dble_reg (
//outputs
sync_out_pulse,
//inputs
in_pulse,
dest_clk,
reset_n
);
output sync_out_pulse; //output synchronised to slow clock
input in_pulse; //input based on fast clock, pulse
input dest_clk; //slow clock
input reset_n;
reg s1_sync_out, d_sync_out, s2_sy... | 6.798279 |
modules. They "should" be
// identical.
//
// To prove:
//
// 1. That nothing changes as long as CE is low
//
// 2. That the outputs of the two LFSR's are identical, and hence the
// output, o_data, will be forever zero.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////... | 7.152209 |
module dbl_buf ( /*AUTOARG*/
// Outputs
dout,
vld,
full,
// Inputs
clk,
rst_l,
wr,
rd,
din
);
// synopsys template
parameter BUF_WIDTH = 64; // width of the buffer
// Globals
input clk;
input rst_l;
// Buffer Input
input wr;
input rd;
input [BUF_WIDTH-1:0]... | 7.209759 |
module dbl_tap_monitor (
input wire clk_1k, //1kHz clock required
input wire rstn,
input wire in_signal, //A pulse for each tap
input wire [15:0] delay_ms, //double tap delay
output wire out_signal //Pulse for every successful double tap
);
reg tap_pulse_r;
reg tap_sense;
wire tap_pul... | 8.300707 |
module dbpsk_modulator (
clock,
reset,
input_data,
trigger,
output_dbpsk
);
input clock, reset;
input trigger;
input input_data;
output reg output_dbpsk;
reg [15:0] counter;
always @(posedge clock or negedge reset) begin
if (!reset) begin
output_dbpsk <= 0;
counter <= 0... | 7.623492 |
module dbram ( /*AUTOARG*/
// Outputs
rd_data_out,
// Inputs
clk,
rst_n,
wr_data_in,
wr_addr,
wr_data_en,
rd_addr
);
parameter DATA_WIDTH = 8;
parameter DEPTH = 16;
parameter ADDR_WIDTH = 4;
input wire clk;
input wire rst_n;
input wire [DATA_WIDTH-1:0] wr_data_in;
i... | 7.914757 |
module dbram16 #(
parameter init_file = "none",
parameter adr_width = 11,
parameter data_width = 16
) (
input a_clk,
input a_rst,
input [data_width-1:0] a_do,
output reg [data_width-1:0] a_di,
input a_we,
input [adr_width-1:0] a_a,
input b_clk,
input b_rst,
input [data... | 9.087667 |
module dbram32 #(
parameter init_file = "none",
parameter adr_width = 11
) (
input a_clk,
input a_rst,
input [31:0] a_do,
output reg [31:0] a_di,
input a_we,
input [15:0] a_a,
input b_clk,
input b_rst,
input [31:0] b_do,
output reg [31:0] b_di,
input b_we,
input ... | 8.272982 |
module dbram8 #(
parameter init_file = "none",
parameter adr_width = 11
) (
input a_clk,
input a_rst,
input [7:0] a_do,
output reg [7:0] a_di,
input a_we,
input [7:0] a_a,
input b_clk,
input b_rst,
input [7:0] b_do,
output reg [7:0] b_di,
input b_we,
input [7:0] ... | 8.291265 |
module dbram_2048_40bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b,
reset
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 40;
input clk, reset;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
i... | 6.54167 |
module dpram_2048_40bit_db (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 40;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
i... | 7.111127 |
module dbram_2048_60bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b,
reset
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 60;
input clk, reset;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
i... | 6.528626 |
module dpram_2048_60bit_db (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 60;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
i... | 6.99541 |
module dbram_4096_40bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b,
reset
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 40;
input clk, reset;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
i... | 7.017127 |
module dpram_4096_40bit_db (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 40;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
i... | 7.233774 |
module dbram_4096_60bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b,
reset
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 60;
input clk, reset;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
i... | 7.004941 |
module dpram_4096_60bit_db (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 60;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
i... | 7.134998 |
module dbsao_controller (
clk,
rst_n,
start_i,
done_o,
cnt_o,
state_o
);
//***************************************************
//
// Input / Output Declaration
//
//****************************************************/
input clk, rst_n;
input start_i;
output reg done_o;... | 7.18897 |
module bsm (
input clk,
input reset,
input clear,
input write_done,
input read_done,
output readable,
output writeable
);
reg state;
localparam ST_WRITEABLE = 0;
localparam ST_READABLE = 1;
always @(posedge clk)
if (reset | clear) state <= ST_WRITEABLE;
else
case... | 7.115965 |
module dbsm (
input clk,
input reset,
input clear,
output reg read_sel,
output read_ready,
input read_done,
output reg write_sel,
output write_ready,
input write_done
);
localparam NUM_BUFS = 2;
wire [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf;
// Two o... | 8.004834 |
module DBU (
input clk,
input rst,
input succ,
input step,
input [2:0] sel,
input m_rf,
input inc,
input dec,
output reg [15:0] led, //ú8 LED ʾַ
output reg [7:0] CA,
output reg [7:0] AN
);
wire step_y, clkd;
wire [0:207] status;
wire [31:0] m_data, rf_data;
wire [2... | 6.518508 |
module dbuf (
input wire clk,
input wire [15:0] din, //input
input wire [5:0] didx, //address
input wire RW,
output reg [15:0] di
);
reg [15:0] mem[0:63];
// dbuf
always @(posedge clk) begin
if (RW) mem[didx] <= din;
di <= RW ? din : mem[didx];
end
endmodule
| 6.903553 |
module dbuf_ddr3_reader (
input wire [15:0] din,
output wire [15:0] dout,
input wire clk,
input wire reset,
input wire bclk,
input wire [1:0] cs,
input wire [18:16] hi_addr,
input wire lba,
input wire oe,
input wire rw,
output wire rb_wait,
);
reg bus_w... | 6.693585 |
module DBX (
input [255:0] diff_i,
output [255:0] bpx_o
);
genvar i, j, row_tr, col_tr, row_xor, col_xor;
wire [0:7] diff[0:31];
wire [0:31] bitplane[0:7];
wire [0:31] bitplaneXOR[0:7];
// renaming input in byte size
generate
for (i = 0; i < 32; i = i + 1) begin : input_rename
assign d... | 7.431102 |
module db_cbf_ram_sp_64x16 (
clk,
adr_i,
cen_i, // low active
wen_i, // low active
wr_dat_i,
rd_dat_o
);
//--- input/output declaration --------------------------
input clk;
input [6 -1 : 0] adr_i;
input cen_i;
input wen_i;
input [16 -1 : 0] wr_dat_i;
output [16 -... | 7.975183 |
module db_clip3_str (
o,
x,
y,
i
);
//---------------------------------------------------------------------------
//
// INPUT/OUTPUT DECLARATION
//
//----------------------------------------------------------------------------
input [7:0] x, y;
input [8:0] i;
outp... | 6.629442 |
module db_down (
input clk,
input raw_input,
output reg db
);
reg [31:0] counter = 0;
reg clk_en = 0;
always @(posedge clk) begin
if (counter == 100000) begin
counter <= 0;
clk_en <= 1;
end else begin
counter <= counter + 1;
clk_en <= 0;
end
end
always @(po... | 6.906684 |
module db_fsm (
input wire clk,
reset,
input wire sw,
output reg db
);
// symbolic state declaration
localparam [2:0]
zero = 3'b000,
wait1_1 = 3'b001,
wait1_2 = 3'b010,
wait1_3 = 3'b011,
one = 3'b100,
... | 7.97697 |
module db_lcu_ram (
clka,
cena_i,
rena_i,
wena_i,
addra_i,
dataa_o,
dataa_i,
clkb,
cenb_i,
renb_i,
wenb_i,
addrb_i,
datab_o,
datab_i
);
// ********************************************
//
// Parameter DECLAR... | 7.463649 |
module db_left_ram (
clka,
cena_i,
rena_i,
wena_i,
addra_i,
dataa_o,
dataa_i,
clkb,
cenb_i,
renb_i,
wenb_i,
addrb_i,
datab_o,
datab_i
);
// ********************************************
//
// Parameter DECLAR... | 7.943766 |
module db_module (
clk,
rst,
step,
controller,
delta,
deltab
);
input clk, rst;
input [3:0] step, controller;
input signed [15:0] delta;
output signed [15:0] deltab;
reg signed [31:0] temp;
always @(posedge clk) begin
if (rst) begin
temp <= 32'd0;
end else begin
... | 7.038521 |
module db_mpu_6050 #(
parameter FPGA_CLK = 50_000_000, // FPGA frequency 50 MHz
parameter I2C_CLK = 400_000
) // I2C bus frequency 400 KHz
(
CLK,
I_KEY,
I_SW,
O_LEDR,
IO_SCL,
IO_SDA
);
//--------------------------------------------------------------------------
localparam RX... | 6.527144 |
module db_mv_ram (
clka,
cena_i,
rena_i,
wena_i,
addra_i,
dataa_o,
dataa_i,
clkb,
cenb_i,
renb_i,
wenb_i,
addrb_i,
datab_o,
datab_i
);
// ********************************************
//
// Parameter DECLARA... | 7.530284 |
module db_mv_ram_sp_512x20 (
// global
clk,
// address
adr_i,
// write
wr_ena_i,
wr_dat_i,
// read
rd_ena_i,
rd_dat_o
);
//--- input/output declaration --------------------------
// global
input clk;
// address
input [9 -1 : 0] adr_i;
// write
input wr_ena_i;
inp... | 7.733989 |
module db_mv_ram_sp_64x20 (
clk,
adr_i,
cen_i, // low active
wen_i, // low active
wr_dat_i,
rd_dat_o
);
//--- input/output declaration --------------------------
input clk;
input [6 -1 : 0] adr_i;
input cen_i;
input wen_i;
input [20 -1 : 0] wr_dat_i;
output [20 -1... | 7.733989 |
module db_qp (
clk,
rst_n,
cbf_4x4_i,
cbf_u_4x4_i,
cbf_v_4x4_i,
qp_left_i,
qp_flag_o
);
// *************************************************************************************************
//
// INPUT / OUTPUT DECLARATION
... | 6.574085 |
module db_qp_ram (
clk,
cen_i,
oen_i,
wen_i,
addr_i,
data_i,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ***************... | 7.315851 |
module db_qp_ram_sp_64x20 (
clk,
adr_i,
cen_i, // low active
wen_i, // low active
wr_dat_i,
rd_dat_o
);
//--- input/output declaration --------------------------
input clk;
input [6 -1 : 0] adr_i;
input cen_i;
input wen_i;
input [20 -1 : 0] wr_dat_i;
output [20 -1... | 7.737488 |
module db_ram_1p (
clk,
cen_i,
oen_i,
wen_i,
addr_i,
data_i,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ***************... | 8.018449 |
module db_ram_1p_128x8 (
clk,
cen_i,
oen_i,
wen_i,
addr_i,
data_i,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// *********... | 8.106977 |
module db_ram_1p_28x480 (
clk,
cen_i,
oen_i,
wen_i,
addr_i,
data_i,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********... | 8.212212 |
module db_reset (
input clk,
input raw_input,
output reg db
);
reg [31:0] counter = 0;
reg clk_en = 0;
always @(posedge clk) begin
if (counter == 100000) begin
counter <= 0;
clk_en <= 1;
end else begin
counter <= counter + 1;
clk_en <= 0;
end
end
always @(p... | 7.20226 |
module db_sao_compare_cost (
b_cost_0_i,
b_cost_1_i,
b_cost_2_i,
b_cost_3_i,
b_cost_4_i,
b_cost_o,
b_band_o
);
//---------------------------------------------------------------------------
//
// ... | 7.093559 |
module db_spin (
input clk,
input raw_input,
output reg db
);
reg [31:0] counter = 0;
reg clk_en = 0;
always @(posedge clk) begin
if (counter == 100000) begin
counter <= 0;
clk_en <= 1;
end else begin
counter <= counter + 1;
clk_en <= 0;
end
end
always @(po... | 7.219358 |
module pb_debouncer (
input clk, // 100Mhz
input dirty, // "PB" is the glitchy, asynchronous to clk, active low push-button signal
input reset, // Debounced reset signal
// from which we make three outputs, all synchronous to the clock
output reg PB_state, // 1 as long as the push-button is a... | 7.43367 |
module db_top_ram (
clka,
cena_i,
rena_i,
wena_i,
addra_i,
dataa_o,
dataa_i,
clkb,
cenb_i,
renb_i,
wenb_i,
addrb_i,
datab_o,
datab_i
);
// ********************************************
//
// Parameter DECLARA... | 6.765655 |
module db_tupu_ram_sp_64x32 (
clk,
adr_i,
cen_i, // low active
wen_i, // low active
wr_dat_i,
rd_dat_o
);
//--- input/output declaration --------------------------
input clk;
input [6 -1 : 0] adr_i;
input cen_i;
input wen_i;
input [32 -1 : 0] wr_dat_i;
output [32 ... | 7.252945 |
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