code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module db_up (
input clk,
input raw_input,
output reg db
);
reg [31:0] counter = 0;
reg clk_en = 0;
always @(posedge clk) begin
if (counter == 100000) begin
counter <= 0;
clk_en <= 1;
end else begin
counter <= counter + 1;
clk_en <= 0;
end
end
always @(pose... | 6.689226 |
module dcache2_ram (
clk,
rst,
read_nClkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 8;
localparam DATA_WIDTH = `dcache2_data_width;
localparam ADDR_COUNT = 256;
input clk;
input rst;
input read_nClkEn;
input [ADDR_WIDTH-1:0] read_... | 8.095148 |
module dcache2_LRU_ram (
clk,
rst,
read_nClkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 8;
localparam DATA_WIDTH = 5;
localparam ADDR_COUNT = 256;
input clk;
input rst;
input read_nClkEn;
input [ADDR_WIDTH-1:0] read_addr;
output... | 7.857579 |
module dcache2_ram_box (
clk,
rst,
read_nClkEn,
read_addr,
read_data,
read_datax,
write_data,
write_wen,
write_ben
);
localparam ADDR_WIDTH = 8;
localparam DATA_WIDTH = `dcache2_data_width;
input clk;
input rst;
input read_nClkEn;
input [ADDR_WIDTH-1:0] read_addr;
outp... | 6.821517 |
module dcache2_xbit_ram (
clk,
rst,
read_nClkEn,
read0_addr,
read0_data,
read1_addr,
read1_data,
write0_addr,
write0_data,
write0_wen,
write1_addr,
write1_data,
write1_wen
);
localparam ADDR_WIDTH = 8 - 1;
localparam DATA_WIDTH = `dcache2_data_width;
localparam ... | 7.124866 |
module dcache2_xbit_ram_box (
clk,
rst,
read_nClkEn,
read0_addr,
read0_data,
read0_datax,
write0_data,
write0_wen,
write0_ben,
read1_addr,
write1_data,
write1_wen,
write1_ben
);
localparam ADDR_WIDTH = 8 - 1;
localparam DATA_WIDTH = `dcache2_data_width;
input c... | 7.124866 |
module dc0_cntrl_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 5;
localparam DATA_WIDTH = `mOpC_width + 2 + 16;
localparam ADDR_COUNT = 32;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_... | 8.305398 |
module dc0_cntrlD_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 5;
localparam DATA_WIDTH = 128 + 16;
localparam ADDR_COUNT = 32;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
out... | 8.005724 |
module dc0_cntrlC_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 3;
localparam DATA_WIDTH = 37 + 5;
localparam ADDR_COUNT = 8;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
output... | 8.068021 |
module dc0_cntrlC2w_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr0,
write_addr1,
write_data0,
write_wen0 write_data1,
write_wen1
);
localparam ADDR_WIDTH = 3;
localparam DATA_WIDTH = 37 + 5;
localparam ADDR_COUNT = 8;
input clk;
input rst;
input read_c... | 7.890662 |
module dc0_cntrlC1_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 5;
localparam DATA_WIDTH = 37 + 5 + 1 + 1 + 13;
localparam ADDR_COUNT = 32;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read... | 7.804922 |
module dc0_cntrlM_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 5;
localparam DATA_WIDTH = 37 + 5 + 1 + 1 + 13;
localparam ADDR_COUNT = 32;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_... | 7.952528 |
module dc0_cntrlM1_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 5;
localparam DATA_WIDTH = 37 + 1 + 1;
localparam ADDR_COUNT = 32;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
... | 7.880342 |
module dc0_cntrlMiC2_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 5;
localparam DATA_WIDTH = 37 + 5;
localparam ADDR_COUNT = 32;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
ou... | 7.781377 |
module dcache2_tag_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam ADDR_WIDTH = 8;
localparam DATA_WIDTH = `dc2Tag_width;
localparam ADDR_COUNT = 256;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr... | 7.62673 |
module dc2_thag_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write0_addr,
write0_data,
write0_wen,
write0_bitEn,
write1_addr,
write1_data,
write1_wen,
write1_bitEn,
write2_addr,
write2_data,
write2_wen,
write2_bitEn
);
localparam ADDR_WIDTH = 4;... | 7.84082 |
module DC2390_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
DC2390_pll_0002 dc2390_pll_inst (
.refclk (refclk), // refclk.clk
... | 7.685257 |
module dcache2_dirty_ram (
clk,
rst,
read_addr0,
read_clkEn0,
read_data0,
write_addr0,
write_wen0,
write_bitEn0,
write_data0,
write_addr1,
write_wen1,
write_bitEn1,
write_data1
);
localparam ADDR_WIDTH = 5;
localparam DATA_WIDTH = 8;
localparam ADDR_COUNT = 32;... | 6.638203 |
module dcache2_dirty (
clk,
rst,
read_addr0,
read_clkEn0,
read_dirty0,
write_addr0,
write_wen0,
write_addr1,
write_wen1,
insert,
insert_dirty,
init
);
localparam ADDR_WIDTH = 8;
localparam DATA_WIDTH = 8;
input clk;
input rst;
input [ADDR_WIDTH-1:0] read_addr0... | 6.638203 |
module DC8_reg (
/* A[3] must be zero to enable output of the decocder */
input wire [3:0] A,
input wire clk_in,
input wire res, // positive
output reg [7:0] Q,
output reg [7:0] Qn
);
reg [7:0] qi;
always @(A) begin
qi <= 8'b0000_0000;
case (A)
4'h0: qi[0] <= 1'b1;
4'h... | 7.171973 |
module dcache_axi_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
/... | 7.616121 |
module dcache_core_data_ram (
// Inputs
input clk0_i
, input rst0_i
, input [10:0] addr0_i
, input [31:0] data0_i
, input [ 3:0] wr0_i
, input clk1_i
, input rst1_i
, input [10:0] addr1_i
, input [31:0] data1_i
, input [ 3:0] wr1_i
// Output... | 7.319422 |
module dcache_data_sram (
clk_i,
addr_i,
data_i,
enable_i,
write_i,
data_o
);
// Interface
input clk_i;
input [4:0] addr_i;
input [255:0] data_i;
input enable_i;
input write_i;
output [255:0] data_o;
// Memory
reg [255:0] memory[0:31];
// Write Data
always @(pos... | 7.535032 |
module dcache_if_pmem_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//---------------------------------------------------------------... | 7.101415 |
module mux (
a,
sel,
b
);
parameter Value = 0;
parameter Width = 1;
input [Width-1:0] a;
input sel;
output [Width-1:0] b;
assign b = (sel) ? Value : a;
endmodule
| 8.268895 |
module fifo_buffer (
clk,
reset,
write_en,
data_in,
data_in_valid,
data_in_retry,
read_en,
data_out,
data_out_valid,
data_out_retry,
empty,
full
);
// Parameterize the module
parameter DATA_WIDTH = 8;
parameter ENTRIES = 8;
parameter ADDR_WIDTH = log2(ENTRIES)... | 8.171221 |
module dcache_ram (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input i_clk,
input i_rst,
input [5:0] i_addr,
input [81:0] i_data,
output reg [81:0] o_data,
input i_we
);
reg [81:0] mem[63:0];
always @(posedge ... | 7.822974 |
module dcache_ram (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input i_clk,
input i_rst,
input [5:0] i_addr,
input [81:0] i_data,
output reg [81:0] o_data,
input i_we
);
reg [81:0] mem[63:0];
always @(posedge ... | 7.822974 |
module dcache_sram
(
clk_i,
rst_i,
addr_i,
tag_i,
data_i,
enable_i,
write_i,
tag_o,
data_o,
hit_o
);
// I/O Interface from/to controller
input clk_i;
input rst_i;
input [3:0] addr_i;
input [24:0] tag_i;
input [255:0] data_i;
input ... | 6.604262 |
module dcache_tag (
input wire clk,
input wire rst,
input wire [`RegBus] mem_addr_i,
// дź
input wire wr,
input wire cache_ok,
output wire write_back,
output wire [31:0] last_addr,
output wire hit,
output reg [15:0] select_offset
);
wire [17:0] tag = mem_addr_i[31:14];
wir... | 8.099438 |
module dcache_tag_sram (
clk_i,
addr_i,
data_i,
enable_i,
write_i,
data_o
);
// Interface
input clk_i;
input [4:0] addr_i;
input [23:0] data_i;
input enable_i;
input write_i;
output [23:0] data_o;
// Memory
reg [23:0] memory[0:31];
// Write Data
always @(posedge... | 7.360381 |
module dcb ( /*AUTOARG*/
// Outputs
o0,
o1,
o2,
o3,
ia,
o4,
// Inputs
i0,
i1,
i2,
i3,
oa,
i4,
cfg
);
parameter NN = 2; // number of input ports
parameter MN = 3; // number of output ports
parameter DW = 8; // data-width of a port
parameter SCN = D... | 7.31201 |
modules. //
// RUT will use limited SystemVerilog features which will help to develop the//
// library greatly. //
// ... | 7.062491 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module DCD (
Clk4M,
RST_N,
ITone,
OSpk
);
input Clk4M, RST_N;
input [12:0] ITone;
output OSpk;
reg OSpk;
reg TSpk;
reg [12:0] TCo;
parameter PLC = 13'd8191;
always @(posedge Clk4M or negedge RST_N) begin
if (~RST_N) TCo <= ITone;
else if (TCo == PLC) TCo <= ITone;
else TCo <... | 7.479663 |
module dcd3x8 (
input [2:0] sel,
output reg [7:0] dcdout
);
always @(sel) begin
case (sel)
0: dcdout = 8'b00000001;
1: dcdout = 8'b00000010;
2: dcdout = 8'b00000100;
3: dcdout = 8'b00001000;
4: dcdout = 8'b00010000;
5: dcdout = 8'b00100000;
6: dcdout = 8'b0... | 7.497105 |
module dcdata #(
parameter EXPAND_TYPE = `INFERRED,
parameter LINES = 1024
) (
input clk,
input [9:0] rd_adr,
output [31:0] rd_dat,
input [3:0] wr_en,
input [9:0] wr_adr,
input [31:0] wr_dat
);
generate
case (EXPAND_TYPE)
`INFERRED: begin
reg [7:0] dir0[0:LINES-1];
... | 7.044436 |
module: DCDCController
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DCDCTest_tb;
// Inputs
reg clk;
reg [15:0] voltageSet;
reg [15:0] currentSet;
reg [23:0] DCDC_VSense;
re... | 6.893586 |
module that generates delta weight 2
module dcdw12_module (
clk, rst, step, controller, in_layer, delta2, deltaw2
);
input clk, rst;
input [3:0] step, controller;
input signed [15:0] in_layer, delta2;
output signed [15:0] deltaw2;
reg signed [31:0] temp;
always @(posedge clk ) begin
... | 6.649759 |
module that generates delta weight 3
module dcdw23_module (
clk, rst, step, controller, a2, delta3, deltaw3
);
input clk, rst;
input [3:0] step, controller;
input signed [15:0] a2, delta3;
output signed [15:0] deltaw3;
reg signed [31:0] temp;
always @(posedge clk ) begin
if (rst... | 6.649759 |
module dce2 (
input clk,
input a,
input b,
output reg d
);
reg [1:0] array1;
reg [1:0] array2;
reg c;
always @(*) begin
c = a ^ b;
end
always @(posedge clk) begin
array1[c] <= array1[c] ^ a;
array2[c] <= array2[c] ^ a;
d <= array1[~c];
end
endmodule
| 6.519815 |
module dcfifo_dffpipe (
d,
clock,
aclr,
q
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_delay = 1;
parameter lpm_width = 64;
// LOCAL PARAMETER DECLARATION
parameter delay = (lpm_delay < 2) ? 1 : lpm_delay - 1;
// INPUT PORT DECLARATION
input [lpm_width-1:0] d;
input clock;
input... | 8.172252 |
module dcfifo_fefifo (
usedw_in,
wreq,
rreq,
clock,
aclr,
empty,
full
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthad = 1;
parameter lpm_numwords = 1;
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_mode = "READ";
// INPUT PORT ... | 6.754214 |
module dcfifo ( data, rdclk, wrclk, aclr, rdreq, wrreq,
rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter delay_rdusedw = 1;
parameter delay_wrusedw = 1;
... | 7.370534 |
module DcFifo_32x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`if... | 7.404742 |
module DcFifo_32x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`if... | 7.404742 |
module dcfifo_512x24 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrusedw
);
input aclr;
input [23:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [23:0] q;
output [8:0] rdusedw;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// sy... | 7.509547 |
module dcfifo_512x24 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrusedw
);
input aclr;
input [23:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [23:0] q;
output [8:0] rdusedw;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// sy... | 7.509547 |
module DCFIFO_Controller (
input iclk_input, //50M
input iclk_output, //400M
input ireset,
input [127:0] idata,
output oread_request,
output [ 15:0] odata,
output [ 10:0] rdusedw,
output [ 7:0] wrusedw
);
wire write_request;
wire read_requ... | 6.719938 |
module dcfifo_dffpipe (
d,
clock,
aclr,
q
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_delay = 1;
parameter lpm_width = 64;
// LOCAL PARAMETER DECLARATION
parameter delay = (lpm_delay < 2) ? 1 : lpm_delay - 1;
// INPUT PORT DECLARATION
input [lpm_width-1:0] d;
input clock;
input... | 8.172252 |
module dcfifo_fefifo (
usedw_in,
wreq,
rreq,
clock,
aclr,
empty,
full
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthad = 1;
parameter lpm_numwords = 1;
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_mode = "READ";
// INPUT PORT ... | 6.754214 |
module
// Based on Altera megafunction dcfifo
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dcfifo_generic
#(
parameter WIDTH = 16,
parameter NUM_WORDS = 1024,
parameter ADDR_WIDTH = 10, //log2(NUM_WORDS)
parameter SHOW_AHEAD = "OFF"
)
(
input aclr,
input [WIDTH-1:0] ... | 7.83644 |
module dcfilter (
multout,
clk,
addin
);
input [15:0] multout;
input clk;
output [15:0] addin;
reg [15:0] addin;
always @(negedge clk) begin
if (multout === 16'bXXXXXXXXXXXXXXXX) addin = 16'b0000000000000000;
else addin = multout;
end
endmodule
| 7.108071 |
module DCIRESET (
LOCKED,
RST
);
output LOCKED;
input RST;
time sample_rising, sample_falling;
always @(RST) begin
if (RST) sample_rising = $time;
else if (!RST) sample_falling = $time;
if (sample_falling - sample_rising < 100000)
$display(
"Timing Violation Error : The... | 7.810634 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module dclkfifo (
rclk,
wclk,
reset,
full,
empty,
item_in,
item_out,
write,
read
);
parameter routerid = -1;
parameter DCLK_FIFO_DSIZE = 4;
input rclk, wclk, reset, write, read;
output full, empty;
reg [DCLK_FIFO_DSIZE -1:0] mem[`DCLK_FIFO_DEPTH-1:0];
reg [`DCLK_FIFO... | 6.615442 |
module top ();
wire rclk;
wire wclk;
wire reset;
wire full;
wire empty;
wire write;
wire read;
wire [3:0] item_in;
wire [3:0] item_out;
// Connect the DUT
generator #(2, 4) g0 (
rclk,
wclk,
reset,
item_in,
write,
rea... | 7.326089 |
module generator (
rclk,
wclk,
reset,
item_in,
write,
read
);
output rclk, wclk, reset, write, read;
output [3:0] item_in;
reg rclk, wclk, reset, write, read;
reg [3:0] item_in;
initial begin
rclk = 0;
wclk = 1;
item_in = 0;
write = 0;
read = 0;
#0 reset... | 7.128432 |
module top ();
wire rclk;
wire wclk;
wire reset;
wire serial_out;
wire channel_busy;
wire valid;
wire ... | 7.018989 |
module generator (
rclk,
wclk,
reset,
item_in,
req,
item_read
);
parameter RCLOCK_PERIOD = 10;
parameter WCLOCK_PERIOD = 12;
parameter WCLOCK_PHASE = 2;
output rclk, wclk, reset, req, item_read;
output [`PAYLOAD_SIZE+`ADDR_SZ-1:0] item_in;
reg rclk, wclk, reset, req, item_read;... | 7.128432 |
module generic_fifo_dc(rd_clk, wr_clk, rst, clr, din, we, dout, re,
full, empty, full_n, empty_n, level );
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
input rd_clk, wr_clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input re;
output full;
output empty... | 6.701278 |
module dclk_rx (
rclk,
wclk,
reset,
valid,
channel_busy,
item_read,
serial_in,
parallel_out
);
`include "constants.v"
// parameter routerid=-1;
parameter port = "unknown";
input rclk, wclk, reset, item_read, serial_in;
output valid, channel_busy;
reg channel_busy;
outp... | 7.154294 |
module dclk_rx (
rclk,
wclk,
reset,
valid,
channel_busy,
item_read,
serial_in,
parallel_out
);
`include "constants.v"
// parameter routerid=-1;
parameter port = "unknown";
input rclk, wclk, reset, item_read, serial_in;
output valid, channel_busy;
reg channel_busy;
outp... | 7.154294 |
module dclk_rx (
rclk,
wclk,
reset,
valid,
channel_busy,
item_read,
serial_in,
parallel_out
);
`include "constants.v"
// parameter routerid=-1;
parameter port = "unknown";
`define STATE_IDLE 0
`define STATE_WRTNG 1
`define STATE_VALID 2
`define STATE_READ 3
`define MOD_... | 7.154294 |
module dclk_rx (
rclk,
wclk,
reset,
valid,
channel_busy,
item_read,
serial_in,
parallel_out
);
// `include "constants.v"
// parameter routerid=-1;
parameter port = "unknown";
// states format: <generating clock domain>-STATE-<status>
`define WR_STATE_IDLE 0
`define WR_STAT... | 7.154294 |
module dclk_rx (
rclk,
wclk,
reset,
valid,
channel_busy,
item_read,
serial_in,
parallel_out
);
`include "constants.v"
// parameter routerid=-1;
parameter port = "unknown";
// states format: <generating clock domain>-STATE-<status>
`define STATE_IDLE 0
`define STATE_WRTNG 1... | 7.154294 |
module dclk_rx (
rclk,
wclk,
reset,
valid,
channel_busy,
item_read,
serial_in,
parallel_out
);
`include "constants.v"
// parameter routerid=-1;
parameter port = "unknown";
// states format: <generating clock domain>-STATE-<status>
`define STATE_IDLE 0
`define STATE_WRTNG 1... | 7.154294 |
module dclk_rx_bram (
en,
rd_clk,
wr_clk,
reset,
valid,
channel_busy,
fifo_read,
fifo_count,
serial_in,
item_out
);
`define STATE_IDLE 0
`define STATE_SHFT 1
`define STATE_FNSH 2
parameter routerid = -1;
parameter port = "unknown";
input wr_clk, rd_clk, en, reset, f... | 6.955945 |
module Top (
input clk,
input rst_n,
input wave,
input switch,
output reg [3:0] seg = 0,
output reg [7:0] codeout = 0,
output reg led
);
wire fout;
reg [13:0] num = 0;
reg [3:0] d1, d2, d3, d4;
reg [13:0] T = 0;
reg [13:0] duty_cyc... | 6.64497 |
module dcm ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
output CLK_OUT5
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocki... | 6.632448 |
module dcm12_100 (
// Inputs
input clkref_i
// Outputs
, output clkout0_o
);
wire clkref_buffered_w;
wire clkfb;
wire clk0;
wire clkfx;
// Clocking primitive
DCM_SP #(
.CLKDV_DIVIDE(2.000),
.CLKFX_DIVIDE(3),
.CLKFX_MULTIPLY(25),
.CLKIN_PERIOD(83.3333333333),
... | 7.216727 |
module dcm1_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input ... | 7.667508 |
module dcm1_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 31.250 ... | 7.87438 |
module dcm32to50 ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
output CLK_OUT5,
output CLK_OUT6
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(... | 6.588876 |
module dcm32to50_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [6:1] CLK_OUT,
// High bits of counters driven by clocks
output [6:1] COUNT
);
// Parameters for the counters
/... | 7.317205 |
module dcm32to50_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 31... | 7.206584 |
module dcm90 ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
// Clocking primitive
//-----------------------------... | 6.655975 |
module dcm90_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input... | 7.59563 |
module dcm90_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0 *... | 7.772587 |
module dcmem #(
parameter MEM_ADDR_WIDTH = 5, //地址宽度5位，一共32个数据
parameter MEM_DATA_WIDTH = 16,
parameter MEM_NUMBER = 32
) (
input [MEM_ADDR_WIDTH-1:0] addr, //写入和读出用同一个地址线
input [MEM_DATA_WIDTH-1:0] data_w,
input MemWEn,
input clk,
output [MEM_DATA_WIDTH-1:0] data_r
);
reg [MEM_DATA_... | 9.2137 |
module dcmi_irq (
// sys
input rstn,
input clk,
// pulse
input line_irq_pulse,
input vsync_irq_pulse,
input err_irq_pulse,
input ovfl_irq_pulse,
input frame_end_irq_pulse,
// reg
output reg [4:0] dcm... | 7.151028 |
module dcmi_pingpang (
input rstn,
input clk,
input block_en,
// wr
output wr_rdy,
input wr_req,
input [31:0] wr_data,
// rd
output rd_rdy,
input rd_req,
output [31:0] rd_data
);
//---------------------------------------------------------------------------
// SIGNAL
//... | 7.866651 |
module dcmi_psync (
input srstn,
sclk,
sin,
input drstn,
dclk,
output dout
);
// source toggle
reg stoggle;
always @(posedge sclk or negedge srstn)
if (~srstn) stoggle <= 0;
else if (sin) stoggle <= ~stoggle;
// cross clock domain
reg [2:0] stoggle_dly;
always @(posedge dcl... | 6.899399 |
module dcmspi (
input RST, //Synchronous Reset
input PROGCLK, //SPI clock
input PROGDONE, //DCM is ready to take next command
input DFSLCKD,
input [7:0] M, //DCM M value
input [7:0] D, //DCM D value
input ... | 7.508842 |
module dcm_165MHz ( // Clock in ports
input clk,
// Clock out ports
output clk_sdram,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = clk;
// Clocking primitive
//-------------------------------... | 7.180314 |
module dcm_24MHz ( // Clock in ports
input clk,
// Clock out ports
output cmos_xclk,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = clk;
// Clocking primitive
//--------------------------------... | 6.775404 |
module dcm_25m_clk_wiz ( // Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg (
.O(clk_in1_dcm_25m),
.I(clk_in1)
);
// Clocking PRIMIT... | 7.819003 |
module main_pll ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//------------------------------------
/... | 6.951372 |
module dcm_adv_clock_divide_by_2 (
clock,
clock_type,
clock_out,
rst
);
input clock;
input clock_type;
input rst;
output clock_out;
reg clock_out;
reg clock_div2;
reg [2:0] rst_reg;
wire clk_src;
initial begin
clock_out = 1'b0;
clock_div2 = 1'b0;
end
always @(posedge cl... | 6.657983 |
module dcm_adv_maximum_period_check (
clock,
rst
);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge = 0;
clock_period = 0;
end
always @(posedge clock) begin
clock_edge <= $time;
... | 7.695623 |
module dcm_adv_clock_lost (
clock,
enable,
lost,
rst
);
input clock;
input enable;
input rst;
output lost;
reg lost_r, lost_f, lost;
time clock_edge;
reg [63:0] period;
reg clock_low, clock_high;
reg clock_posedge, clock_negedge;
reg clock_second_pos, clock_second_neg;
initial b... | 6.657983 |
module DCM_BASE (
CLK0,
CLK180,
CLK270,
CLK2X,
CLK2X180,
CLK90,
CLKDV,
CLKFX,
CLKFX180,
LOCKED,
CLKFB,
CLKIN,
RST
);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter real CLKIN_PERIOD = 10.0;
param... | 8.048063 |
module DCM_BUFG (
input I,
input RST_N,
output O
);
wire RST_P;
assign RST_P = !RST_N;
BUFG CLK0_BUFG_INST (
.I(I),
.O(O)
);
endmodule
| 7.090548 |
module DCM_CMOS ( // Clock in ports
input clk_in1,
// Clock out ports
output clk_out1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(clk_in1)
);
// Clocking primitive
//------------------------------------
// Instantiation of th... | 7.092463 |
module DCM_CMOS_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output COUNT
);
// Parameters for the counters
//-------------------------------
// Counter... | 6.891571 |
module DCM_CMOS_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.... | 7.702635 |
module dcm_delay ( // Clock in ports
input clk133,
input CLKFB_IN,
// Clock out ports
output clk133out,
output clk133_p90,
output clk133_p180,
output clk133_p270,
output CLKFB_OUT,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//-----... | 6.547936 |
module dcm_delay_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT,
// Status and control signals
i... | 7.269551 |
module dcm_dsp ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inpu... | 6.854039 |
module dcm_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT
);
// Parameters for the counters
//-----... | 7.531459 |
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