code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dcm_freq_counter #(
parameter integer REF_FREQ = 100000000, // Reference frequency (100MHz default)
parameter integer LF_MODE_MIN = 10000000, // Minimum frequency for "low frequency" mode
parameter integer LF_MODE_MAX = 150050000, // Maximum frequency for "low frequency" mode
parameter intege... | 7.98547 |
module DCM_PS (
CLK0,
CLK180,
CLK270,
CLK2X,
CLK2X180,
CLK90,
CLKDV,
CLKFX,
CLKFX180,
DO,
LOCKED,
PSDONE,
CLKFB,
CLKIN,
PSCLK,
PSEN,
PSINCDEC,
RST
);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
par... | 6.94484 |
module dcm_sp_maximum_period_check (
clock,
rst
);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge = 0;
clock_period = 0;
end
always @(posedge clock) begin
clock_edge <= $time;
//... | 7.484979 |
module dcm_sys(CLKIN_IN,
RST_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND1;
assig... | 6.919949 |
module dcm_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0 * O... | 7.983179 |
module DCOff_DSP (
input clk,
input rst,
input [7:0] din,
output [7:0] dc
);
wire signed [15:0] PRODUCT;
wire signed [ 7:0] K;
//wire signed [31:0] ACOUT;
assign K = 16'h0085;
ADDMACC_MACRO #(
.DEVICE("7SERIES"), // Target Device: "VIRTEX6", "SPARTAN6", "7SERIES"
.LATENCY(4),... | 7.840935 |
module dcol_reader (
full,
empty,
addrin,
clk,
readin,
addrout,
reset,
resetpe,
write_q,
sel
);
input full;
input empty;
input [14:0] addrin;
input clk;
input reset;
input sel;
output readin;
output [18:0] addrout;
output resetpe;
output write_q;
wire ... | 8.729011 |
module tb_top_dcol;
reg clk;
reg full;
reg empty;
reg [14:0] addrin;
reg reset;
reg sel;
wire [18:0] addrout;
wire readin;
wire resetpe;
wire write_q;
dcol_reader dc (
full,
empty,
addrin,
clk,
readin,
addrout,
reset,
resetpe,
write_q,
... | 7.691225 |
module DCombinMemPort(
input clock,
input reset,
input [31:0] io_pipeline_address,
input io_pipeline_valid,
output io_pipeline_good,
input [31:0] io_pipeline_writedata,
input io_pipeline_memread,
input io_pipeline_memwrite,
input [1:0] io_pipeline_mas... | 6.870769 |
module dcontrol (
input clk,
input rst_n,
input [15:0] addr,
input [7:0] data,
output reg [7:0] data_out,
input rd,
input wr,
input fifo_rden,
output fifo_empty,
output [7:0] fifo_data
);
reg [15:0] src_addr;
reg arm;
localparam ENDADDR = 16'h3FFF;
reg fifo_wren;
reg ... | 7.181277 |
module dcounter (
d_out,
clock,
rst,
d_en
);
input clock;
input rst;
input d_en;
output [15:0] d_out;
reg [15:0] counter;
always @(posedge clock)
if (rst) begin
counter <= 16'b0;
end else if (d_en) begin
counter <= counter - 1'b1;
end else begin
counter <= co... | 7.611291 |
module dcounter_tb ();
reg clock, rst;
reg d_en;
wire rdy;
wire [15:0] d_out;
initial begin
$display($time, " << Starting the Simulation >>");
d_en = 1'b0;
wait (rdy == 1'b1) begin
d_en = 1'b0;
end
#10 d_en = 1'b1;
#1311220 $display($time, " << Simulation Complete >>");
... | 7.63259 |
module dcounter_tb ();
reg clock, rst;
reg d_en;
wire [15:0] d_out;
initial begin
$display($time, " << Starting the Simulation >>");
d_en = 1'b0;
#50 rst = 1'b0;
d_en = 1'b1;
#1311220 $display($time, " << Simulation Complete >>");
$stop;
end
initial begin
$monitor($time, ",... | 7.63259 |
module dcpirq_tb (
output reg clk,
output reg rst_n,
output reg enable,
output reg [3:0] irq_trigger
);
initial begin
irq_trigger <= 4'b0000;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
irq_pulse(4'b1000);
@(posedge clk);
end
initial begin
cl... | 6.700035 |
module dcpirq_test;
wire clk;
wire rst_n;
wire enable;
wire [3:0] irq_trigger;
wire int_output;
wire [1:0] irq_address;
dcpirq i_dcpirq (
.clk(clk),
.rst_n(rst_n),
.enable(enable),
.irq_trigger(irq_trigger),
.int_output(int_output),
.irq_address(irq_address)
);
d... | 6.640117 |
module DCPU16 (
rst_n, // Active low reset
clk, // Clock
// RAM interface
ram_addr, // Address to RAM
ram_dout // Data from RAM
);
// Inputs
input rst_n; // Active low reset
input clk; // Clock
// RAM interface
output [15:0] ram_addr; // Address to RAM
input [15:0] ram_dout; //... | 7.727863 |
module dcpu16_cpu ( /*AUTOARG*/
// Outputs
g_wre,
g_stb,
g_dto,
g_adr,
f_wre,
f_stb,
f_dto,
f_adr,
// Inputs
rst,
g_dti,
g_ack,
f_dti,
f_ack,
clk
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [15:0] f_adr... | 6.835773 |
module dcpu16_regs ( /*AUTOARG*/
// Outputs
rrd,
// Inputs
rwd,
rra,
rwa,
rwe,
rst,
ena,
clk
);
output [15:0] rrd; // read data
input [15:0] rwd; // write data
input [2:0] rra, // read address
rwa; // write address
input rwe; // write-enable
input rst, ena,... | 7.190733 |
module dcpu16sim ( /*AUTOARG*/);
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] f_adr; // From ut0 of dcpu16_cpu.v
wire [15:0] f_dti; // From ur0 of fasm_dpsram_wbr.v
wire [15:0] f_dto; // From ut0 of dcpu16_cpu.v
w... | 6.647495 |
module dcpu_alu (
// Inputs
opcode,
a,
b,
// Outputs
result,
overflow
);
// Inputs
input [3:0] opcode;
input [15:0] a; // First decoded operand
input [15:0] b; // Second decoded operand
// Outputs
output reg [15:0] result;
output reg [15:0] overflow;
// Compute result
... | 7.159613 |
modules.v //
// Author.......Ran Minerbi //
// //
// Unit Description : //
// dcp unit ... | 6.855611 |
module dram (
adr,
do,
di,
we,
pwrdown,
clk
);
input [`dc_msb:2] adr ;
input [31:0] di ;
input [3:0] we ;
input clk ;
input pwrdown;
output[31:0] do;
// synopsys translate_off
// ram instantiated
reg [7:0] dc_ra... | 7.202239 |
module dcram_misc (
addr,
bank_sel,
bypass,
we,
data_in,
sin,
so,
sm,
clk
);
input clk;
input [`dc_msb:0] addr;
input [1:0] bank_sel;
input bypass;
input [3:0] we;
input [63:0] data_in;
input sm;
input sin;
output so;
reg [`dc_msb:0] addr_l;
mj_s_ff_s_d ff... | 6.60162 |
module dcache_ram0_LocalBist (
BIST_ADR,
BIST_WE,
func_do,
BIST_ON,
ERRN_ON,
INVERSE,
NO_COMP,
END_SEQ,
dcache_ram0_ENABLE,
BACKGROUND,
BIST_PATTERN,
we,
dcache_ram0_ERROR
);
input [31:0] func_do;
output [31:0] BIST_PATTERN;
input [`dc_msb-2:0] BIST_ADR;
inpu... | 6.61256 |
module dcache_ram1_LocalBist (
BIST_ADR,
BIST_WE,
func_do,
BIST_ON,
ERRN_ON,
INVERSE,
NO_COMP,
END_SEQ,
dcache_ram1_ENABLE,
BACKGROUND,
BIST_PATTERN,
we,
dcache_ram1_ERROR
);
input [31:0] func_do;
output [31:0] BIST_PATTERN;
input [`dc_msb-2:0] BIST_ADR;
inpu... | 6.665854 |
module dcache1_ram (
clk,
rst,
read_nClkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen,
write_ben
);
`ifdef DCACHE_256K
localparam ADDR_WIDTH = 7;
localparam ADDR_COUNT = 128;
`else
localparam ADDR_WIDTH = 6;
localparam ADDR_COUNT = 64;
`endif
localparam DATA_W... | 7.976492 |
module dc1_strip_ECC (
dataIn,
dataOut
);
input [39:1] dataIn;
output [31:0] dataOut;
assign dataOut = {dataIn[38:33], dataIn[31:17], dataIn[15:9], dataIn[7:5], dataIn[3]};
endmodule
| 6.715536 |
module dcache_dirty_ram (
clk,
rst,
read_addr0,
read_clkEn0,
read_data0,
write_addr0,
write_wen0,
write_bitEn0,
write_data0,
write_addr1,
write_wen1,
write_bitEn1,
write_data1
);
localparam ADDR_WIDTH = 3;
localparam DATA_WIDTH = 8;
localparam ADDR_COUNT = 8;
... | 7.2884 |
module dcache_dirty (
clk,
rst,
read_addr0,
read_clkEn0,
read_dirty0,
write_addr0,
write_wen0,
write_addr1,
write_wen1,
insert,
insert_dirty,
init
);
localparam ADDR_WIDTH = 6;
localparam DATA_WIDTH = 8;
input clk;
input rst;
input [ADDR_WIDTH-1:0] read_addr0;... | 6.949226 |
module dc1_xbit_ram (
clk,
rst,
readA_clkEn,
readA_addr,
readA_data,
readB_clkEn,
readB_addr,
readB_data,
writeA_clkEn,
writeA_addr,
writeA_data,
writeB_clkEn,
writeB_addr,
writeB_data
);
`ifdef DCACHE_256K
localparam ADDR_WIDTH = 6;
localparam ADDR_COUNT = 64... | 8.02574 |
module dcache1_tag_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
`ifdef DCACHE_256K
localparam ADDR_WIDTH = `dcache1_addr_width;
localparam ADDR_COUNT = `dcache1_addr_count;
`else
localparam ADDR_WIDTH = `dcache1_addr_width - 1;
localparam... | 7.156177 |
module dcache1_tagV_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write0_addr,
write0_data,
write0_wen,
write1_addr,
write1_data,
write1_wen,
write2_addr,
write2_data,
write2_wen,
write3_addr,
write3_data,
write3_wen,
write4_addr,
write4_da... | 7.19984 |
module dcs_client_fifo_wr_fsm (
//DCS rx_fifo read interface
input dcs_rd_clk, //40MHz
output dcs_rd_sof_n,
output [7:0] dcs_rd_data_out,
output dcs_rd_eof_n,
output dcs_rd_src_rdy_n,
input dcs_rd_dst_rdy_n,
input [5:0] dcs_rd_addr,
output [3... | 7.46473 |
module DCS_Encoder (
input resetn,
input clk,
input data_en, //Initiates an 8-bit data transfer
input escape_en, //Initiates a LP11,LP10,LP00,LP01,LP00 transmission
input stop_en, //Returns LP output ports to LP11 idle state
input [7:0] data,
output ready , //Tells stat... | 6.787348 |
module srudcsreplyack (
input reset,
input dcsclk,
input rcmd_reply_dv,
input [31:0] udp_cmd_addr,
input [31:0] rcmd_reply_data,
output reg dcs_cmd_update = 1'b0,
output reg [63:0] dcs_cmd_reply = 64'h0
);
parameter st0 = 0;
parameter st1 = 1;
parameter st2 = 2;
paramete... | 6.609502 |
module MUX (
input control,
d,
crc,
output out
);
assign out = (control && crc) || (~control && d);
endmodule
| 7.716553 |
module dct1d_tb ();
wire [ 5:0] addr; // RAM address bus
wire wren; // RAM write enable
wire [15:0] data; // RAM write data bus
wire ready; // Ready signal
reg clk, reset_n, en; // Enable signal
reg [15:0] q; // RAM read data bus
reg [15:0] testRAM [63:0];
reg [15:0] ... | 6.829193 |
module dct2d_tb ();
reg clk, reset_n, en;
wire rdy, wwren;
wire [5:0] iaddr, maddr, waddr;
reg [15:0] iq;
reg [15:0] mq;
wire [15:0] wdata;
reg [ 7:0] inRAM [63:0];
reg [15:0] matrix [63:0];
reg [15:0] testRAM[63:0];
reg [15:0] solnRAM[63:0];
reg [ 6:0] i;
task assertmem;
begin
... | 7.133965 |
module dctu (
clk,
ena,
ddgo,
x,
y,
ddin,
dout
);
parameter coef_width = 16;
parameter di_width = 8;
parameter [2:0] v = 0;
parameter [2:0] u = 0;
//
// inputs & outputs
//
input clk;
input ena;
input ddgo; // double delayed go signal
input [2:0] x, y;
input [di_... | 6.523909 |
module dct_8puntos_test;
localparam WIDTH_X = 9;
localparam WIDTH_Y = 19;
// test vector input registers
reg clk;
reg load;
reg rst;
reg [WIDTH_X-1:0] x0;
reg [WIDTH_X-1:0] x1;
reg [WIDTH_X-1:0] x2;
reg [WIDTH_X-1:0] x3;
reg [WIDTH_X-1:0] x4;
reg [WIDTH_X-1:0] x5;
reg [WIDTH_X-1:0] x6;
reg... | 6.623995 |
module dct_buffer (
clock,
dct_ram_we,
dct_ram_waddr,
dct_ram_wdata,
dct_ram_raddr,
dct_ram_rdata
);
parameter D_WIDTH = 13;
/* interface declaration */
input clock;
input dct_ram_we; /* synthesis syn_keep=1 */ /* synthesis syn_preserve=1 */
input [D_WIDTH-1:0] dct_ram_wdata; /* ... | 7.094625 |
module dct_ctrl (
clk,
rst,
i_valid,
i_transize,
i_valid_4,
i_transize_1,
i_transize_2,
i_transize_3,
i_transize_4
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 7.007319 |
module dct_idct (
CLK,
RST,
xin,
idct_2d
);
output [7:0] idct_2d;
input CLK, RST;
input [7:0] xin;
wire [7:0] idct_2d;
wire [8:0] dct_2d;
wire rdy_sig;
dct dct_1 (
.CLK(CLK),
.RST(RST),
.xin(xin),
.dct_2d(dct_2d),
.rdy_out(rdy_sig)
);
idct idct_2 (
... | 6.595427 |
module dct_modules_vdd2 #(
parameter SIZE = 10,
APPROX_BITS = 8,
SIZE_OUT = SIZE + 2
) (
input rst,
clk,
//input [7:0] wr_en,
input [7:0] wr_en_entry[7:0],
input approx_en, // stage 2 approx_en
input stage2_en, // enable computation
input signed [SIZE-1:0] data_in[7:0],
ou... | 8.199067 |
module dct_stage1_col_ctrl (
input clk,
rst,
start,
wr_en_col,
output logic col_done,
output logic [7:0] wr_en_entry
);
logic signed [3:0] cnt, n_cnt;
assign col_done = (cnt == 4'b0111);
always_comb begin
n_cnt = cnt;
if (start || cnt == 4'b0111) n_cnt = 0;
else n_cnt = cnt ... | 6.633912 |
module dct_stage1_dff #(
parameter SIZE = 10
) (
input clk,
rst,
//input [7:0] wr_en,
input [7:0] wr_en_entry[7:0],
input signed [SIZE-1:0] data_in[7:0],
output logic signed [SIZE-1:0] data_out[7:0][7:0]
);
dct_stage1_dff_col #(
.SIZE(SIZE)
) dff_col0 (
.clk (clk),
... | 8.129668 |
module dct_stage1_dff_col #(
parameter SIZE = 10
) (
input clk,
rst,
input [7:0] wr_en_entry,
input signed [SIZE-1:0] data_in[7:0],
output logic signed [SIZE-1:0] data_out[7:0]
);
dff #(
.SIZE(SIZE)
) dff0 (
.clk(clk),
.rst(rst),
.wr_en(wr_en_entry[0]),
.d(data... | 8.129668 |
module dct_stage1_dff #(
parameter SIZE = 10
) (
input clk,
rst,
input [7:0] wr_en,
input signed [SIZE-1:0] data_in[7:0],
output logic signed [SIZE-1:0] data_out[7:0][7:0]
);
dct_stage1_dff_col #(
.SIZE(SIZE)
) dff_col0 (
.clk (clk),
.rst (rst),
.wr_en (w... | 8.129668 |
module dct_stage1 #(
parameter SIZE = 8,
APPROX_BITS = 0,
SIZE_MULT = SIZE + 6,
SIZE_OUT = SIZE + 2
) (
input signed [SIZE-1:0] data_in[7:0],
input signed dct_en, //dct_start signal
input approx_en,
clk,
rst,
output logic signed [SIZE_OUT-1:0] data_out[7:0][7:0],
output logi... | 7.543381 |
module dct_stage1 #(
parameter SIZE = 8,
APPROX_BITS = 0,
SIZE_MULT = SIZE + 6,
SIZE_OUT = SIZE + 2
) (
input signed [SIZE-1:0] data_in[7:0],
input signed dct_en, //dct_start signal
input approx_en,
clk,
rst,
output logic signed [SIZE_OUT-1:0] data_out[7:0][7:0],
output logi... | 7.543381 |
module dut;
parameter SIZE = 8, APPROX_BITS = 0, SIZE_MULT = SIZE + 6, SIZE_OUT = SIZE + 3, DIM = 8;
logic signed [SIZE-1:0] data_in[7:0];
logic dct_en, clk, rst; //dct_start signal
logic approx_en;
logic signed [SIZE_OUT-1:0] data_out[7:0][7:0];
logic dct_stage_done;
logic [3:0] cnt;
logic dct_en_i... | 7.252897 |
module dct_stage2 #(
parameter SIZE = 10,
APPROX_BITS = 8,
SIZE_MULT = SIZE + 6,
SIZE_OUT = SIZE + 2
) (
input signed [SIZE-1:0] data_in[7:0][7:0],
input signed dct_en, //dct_start signal
input approx_en,
clk,
rst,
output logic signed [SIZE_OUT-1:0] data_out[7:0][7:0],
outpu... | 7.812349 |
module dct_stage2_comb #(
parameter SIZE = 10,
APPROX_BITS = 0,
SIZE_MULT = SIZE + 6,
SIZE_OUT = SIZE + 2
) (
input signed [SIZE-1:0] data_in[7:0][7:0],
input approx_en,
output logic signed [SIZE_OUT-1:0] data_out[7:0][7:0]
);
dct_col_comb #(
.SIZE(SIZE),
.APPROX_BITS(APPROX_... | 7.49811 |
module dct_stage2_dff #(parameter SIZE = 2) (
input clk,rst,
input:0] wr_en,
input signed [SIZE-1:0] data_in[7:0][7:0],
output logic signed [SIZE-1:0] data_out[7:0][7:0]
);
dct_stage2_dff_col #(.SIZE(SIZE)) dff0 (.clk(clk),.rst(rst),.wr_en(wr_en[0]),.data_in(data_in[0]),.data_out(data_out[0]));
dct_stage2_df... | 7.626202 |
module dct_stage2_dff_col #(
parameter SIZE = 2
) (
input clk,
rst,
input wr_en,
input signed [SIZE-1:0] data_in[7:0],
output logic signed [SIZE-1:0] data_out[7:0]
);
dff_level_convert #(
.SIZE(SIZE)
) dff0 (
.clk(clk),
.rst(rst),
.wr_en(wr_en),
.d(data_in[0]),
... | 7.626202 |
module dct_syn (
clk,
ena,
rst,
dstrb,
din,
dout,
den
);
input clk;
input ena;
input rst;
input dstrb;
input [7:0] din;
output [11:0] dout;
output den;
//
// DCT unit
//
// As little as 11bits coefficients can be used while
// all errors remain in the decimal bit... | 7.139802 |
module dut;
parameter SIZE = 8, APPROX_BITS_ST1= 4, APPROX_BITS_ST2 = 8, SIZE_MULT = SIZE+6,SIZE_OUT = SIZE+2, SIZE_FINAL = SIZE+4;
logic [SIZE-1:0] data_in[8-1:0];
logic clk, rst, dct_en;
logic [1:0] approx_en;
logic signed [SIZE_FINAL-2:0] data_out[8-1:0][8-1:0];
logic dct_done;
logic dct_en_internal... | 7.185605 |
module dct_top #(
parameter M = 32
) (
input [M*16-1:0] data,
input [3:0] number,
input clk,
input start,
input rst_n,
output ready,
output [M*16-1:0] out
);
reg [M*16-1:0] temp_in;
wire [ M*8-1:0] temp_out8;
wire [M*16-1:0] temp_out16;
reg [M*16-1:0] final_out;
reg go8, go16... | 6.841664 |
module dct_8 #(
parameter M = 8
) (
input [M*8-1:0] data,
input enable,
input clk,
input rst_n,
output ready,
output [M*8-1:0] out
);
reg signed [M-1:0] temp[7:0];
reg rdy = 1'b0;
reg [1:0] stat = 2'b00;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
stat <= ... | 7.786146 |
module dct_transpose_32x16 (
clk,
cen_i,
oen_i,
wen_i,
addr_i,
data_i,
data_o
);
// ********************************************
//
// Input/Output DECLARATION
//
// *... | 7.455039 |
module aligner (
dcram_dout,
sign_sel,
algn_sel_7_0,
algn_sel_15_8,
algn_sel_23_16,
algn_sel_31_24,
algn_size_sel,
align_data
);
input [31:0] dcram_dout;
input [4:0] sign_sel;
input [3:0] algn_sel_7_0; //sel the correct 7:0 bits (rotation)
input [3:0] algn_sel_15_8; // sel th... | 7.112493 |
module swapper (
din,
sel_7_0,
sel_15_8,
sel_23_16,
sel_31_24,
dout
);
input [31:0] din;
input [2:0] sel_7_0;
input [2:0] sel_15_8;
input [2:0] sel_23_16;
input [2:0] sel_31_24;
output [31:0] dout;
mux3_8 swap_data_31_24_mux (
.out(dout[31:24]),
.in2(din[31:24]),
... | 6.726818 |
module buffer (
din,
dout,
buf_sel,
buf_ce,
clk,
so,
sin,
sm
);
input [63:0] din;
output [31:0] dout;
input [3:0] buf_sel;
input [1:0] buf_ce;
input clk;
input sin;
output so;
input sm;
wire [31:0] buf_data0, buf_data1, buf_data2, buf_data3;
ff_se_32 buf0 (
.... | 6.861394 |
module dcu_mon (
clk,
clk_count,
dc_inst_c,
iu_inst_c,
smu_inst_c,
dcu_addr_c,
dcu_data_c,
dcu_data,
iu_data_vld,
smu_data_vld
);
input clk;
input [63:0] clk_count;
input dc_inst_c;
input [7:0] iu_inst_c;
input [3:0] smu_inst_c;
input [31:0] dcu_addr_c;
input [31... | 6.623293 |
module DC_1_databank #(parameter Width = 36, Size =512, Forward=0)
( //I adress 22 bits
//36=>4 bit valid bits+ 4 byte/32 bit data=36 bit in total per entry 1 databank
input clk
,input reset
,input bank_sel
,input req_valid
,outp... | 7.362365 |
module DC_CR_ROM (
input wire CLK,
input wire RST,
input wire [ 3:0] VLI_size,
output reg [ 3:0] VLC_DC_size,
output reg [10:0] VLC_DC
);
//-----------------------------------------------------------------
// DC-ROM
//------------------------------------------------------... | 7.931905 |
module dc_data_buffer (
clk,
rstn,
write_pointer,
write_data,
read_pointer,
read_data
);
parameter DATA_WIDTH = 32;
parameter BUFFER_DEPTH = 8;
// `ifndef PULP_FPGA_EMUL
// function integer log2(input integer value);
// begin
// value = value - 1;
// ... | 6.676114 |
module dc_data_fifo #(
parameter ADDR_W = 10
) (
input wire rdclk,
input wire wrclk,
input wire rst_n,
input wire rdreq,
input wire wrreq,
input wire [ 7:0] data_in,
output wire [ ... | 7.281894 |
module dc_pulse #(
parameter
//
// Monovibrator pulse width in clock periods
//
DC_PULSE_WIDTH_CLK = 100
) (
input clk, // input clock
input reset_n, // negative reset
input a_n, // negative start
input b, // positive start
output q // output
);
l... | 6.85283 |
module dc_fifo (
aclr,
wr_clk,
wr,
wr_data,
wr_full,
wr_words_avail,
rd_clk,
rd,
rd_data,
rd_words_avail,
rd_empty
);
parameter data_bits = 16;
parameter addr_bits = 7;
input aclr;
input wr_clk;
input wr;
input [data_bits-1:0] wr_data;
output reg wr_full;
i... | 8.357248 |
module dc_fifo (
aclr,
wr_clk,
wr,
wr_data,
wr_full,
rd_clk,
rd,
rd_data,
rd_words_avail,
rd_empty
);
parameter addr_bits = 7;
parameter data_bits = 16;
input aclr;
input wr_clk;
input wr;
input [71:0] wr_data;
output wr_full;
input rd_clk;
input rd;
output... | 8.357248 |
module dc_fifo_async_read (
aclr,
wr_clk,
wr,
data_in,
afull,
rd_clk,
rd,
data_out,
nword,
valid
);
parameter addr_bits = 7;
parameter data_bits = 16;
input aclr;
input wr_clk;
input wr;
input [data_bits-1:0] data_in;
output afull;
input rd_clk;
input rd;
o... | 8.070186 |
module dc_full_detector (
clk,
rstn,
read_pointer,
write_pointer,
valid,
full
);
parameter BUFFER_DEPTH = 8;
input clk;
input rstn;
input [BUFFER_DEPTH - 1 : 0] read_pointer;
input [BUFFER_DEPTH - 1 : 0] write_pointer;
input valid;
output full;
wire fifo_full;
wire fifo_1_fr... | 6.822006 |
module DC_OFFSET (
IN_adc,
IN_offset,
OUT
);
parameter BW = 6;
input signed [BW-1:0] IN_adc;
input signed [BW-4:0] IN_offset;
output signed [BW-1:0] OUT;
assign OUT = IN_adc + IN_offset;
endmodule
| 7.38278 |
module dc_offset_correct_new (
input clk,
input clken,
input signed [23:0] data_in,
output signed [23:0] data_out
);
// test 11.24
//wire signed [23:0] dc_level = accumulator[39:16];
wire signed [23:0] dc_level = accumulator[34:11];
wire signed [23:0] corrected = data_in[23:0] - dc_level[23:0... | 6.530204 |
module dc_pla #(
parameter
//______________________________________________________________________________
//
// DC303_PLA defines PLA content of the DC303 module
// - DC303_PLA = 0, 23-001C7-AA - 1811VU1
// - DC303_PLA = 1, 23-002C7-AA - 1811VU3
// - DC303_PLA = 2, 23-203C7-AA - 1811VU2... | 7.276977 |
module dc_ram (
input wire clk_a,
input wire [addr_bits - 1:0] addr_a,
input wire [data_bits - 1:0] din_a,
output reg [data_bits - 1:0] dout_a,
input wire wr_en_a,
input wire clk_b,
input wire [addr_bits - 1:0] addr_b,
input wire [data_bits - 1:0] din_b,
output reg [data_bits - 1:0] ... | 7.463749 |
module dc_rep_upload ( //input
clk,
rst,
dc_flits_rep,
v_dc_flits_rep,
flits_max,
en_flits_max,
rep_fifo_rdy,
//output
dc_flit_out,
v_dc_flit_out,
dc_ctrl_out,
dc_rep_upload_state
);
//input
input clk;
input rst;
input [175:0] dc_flits_rep;
input v_dc_flits_rep... | 7.201492 |
module dc_req_upload ( //input
clk,
rst,
dc_flits_req,
v_dc_flits_req,
req_fifo_rdy,
//output
dc_flit_out,
v_dc_flit_out,
dc_ctrl_out,
dc_req_upload_state
);
//input
input clk;
input rst;
input [47:0] dc_flits_req;
input v_dc_flits_req;
input req_fifo_rdy;
//output... | 7.094279 |
module dc_rm #(
parameter DATA_WIDTH = 16
) (
input wire clk,
input wire rstn,
input wire signed [(DATA_WIDTH-1):0] ddc_i,
input wire signed [(DATA_WIDTH-1):0] ddc_q,
input wire ddc_iq_valid,
output wire signed [(DATA_WIDTH-1):0] i_dc_rm,
output wire signed [(DATA_WIDTH-1):0] q_dc_rm,
... | 8.177602 |
module, (128 + 10) lines x 4 pages x 25-bit words
// 25-bit word provides 9-bit next address in the upper bits,
// the rest is 16-bit microcode opcode
//
module dc_rom
#(parameter
//______________________________________________________________________________
//
// DC303_CS defines ROM content of the DC303 ROM module
... | 8.104789 |
module dc_synchronizer (
clk,
rstn,
d_in,
d_out
);
parameter WIDTH = 1;
parameter RESET_VALUE = 'h0;
input clk;
input rstn;
input [WIDTH - 1 : 0] d_in;
output [WIDTH - 1 : 0] d_out;
reg [WIDTH - 1 : 0] d_middle;
reg [WIDTH - 1 : 0] d_out;
always @(posedge clk or negedge rstn) begin... | 7.331681 |
module DC_tb;
reg clk, reset, x;
wire [3:0] out, z;
DC u_DC (
.clk(clk),
.reset(reset),
.x(x),
.out(out),
.z(z)
);
initial clk = 1'b0;
initial reset = 1'b1;
initial x = 1'b0;
always clk = #20 ~clk;
always @(reset) begin
reset = #50 ~reset;
end
always @(x) be... | 6.623964 |
module dc_token_ring (
clk,
rstn,
enable,
state
);
parameter BUFFER_DEPTH = 8;
parameter RESET_VALUE = 'h3;
input clk;
input rstn;
input enable;
output [BUFFER_DEPTH - 1 : 0] state;
reg [BUFFER_DEPTH - 1 : 0] state;
reg [BUFFER_DEPTH - 1 : 0] next_state;
always @(posedge clk or neg... | 7.250515 |
module dc_token_ring_fifo_din (
clk,
rstn,
data,
valid,
ready,
write_token,
read_pointer,
data_async
);
parameter DATA_WIDTH = 10;
parameter BUFFER_DEPTH = 8;
input clk;
input rstn;
input [DATA_WIDTH - 1 : 0] data;
input valid;
output ready;
output [BUFFER_DEPTH - 1 : ... | 7.250515 |
module dc_token_ring_fifo_dout (
clk,
rstn,
data_async,
write_token,
read_pointer,
data,
valid,
ready
);
parameter DATA_WIDTH = 10;
parameter BUFFER_DEPTH = 8;
input [DATA_WIDTH - 1 : 0] data_async;
input clk;
input rstn;
output [DATA_WIDTH - 1 : 0] data;
output valid;
... | 7.250515 |
module DD (
rst,
clk,
yi,
yq,
pd
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟：8MHz
input signed [25:0] yi; //输入同相支路数据：8MHz
input signed [25:0] yq; //输入正交支路数据：8MHz
output signed [25:0] pd; //鉴相器输出数据
//实例化均值计算模块，获取门限值mean
wire signed [25:0] mean;
mgate u0 (
.rst (rst),... | 7.543428 |
module dda_fsm #(
parameter buffer_bits = 2,
parameter buffer_size = 1,
parameter move_duration_bits = 32
) (
input clk,
input resetn,
input dda_tick,
input [move_duration_bits-1:0] move_duration,
output loading_move,
output executing_move,
output reg move_done,
output reg fi... | 8.036582 |
module dda_revC_model (
inout SENSE,
inout SDA,
inout SCL,
inout [9:0] RD,
input [5:0] SMP,
input [2:0] CH,
output [11:0] DAT,
input TSA,
output TSAOUT,
output TSTOUT
);
// DDA has a pulldown on SENSE.
buf (pull1, pull0) pd (SENSE, 0);
wire ON = SENSE;
wire ALERT;
re... | 7.100668 |
module dda_revD_model (
inout SENSE,
inout SDA,
inout SCL,
input [9:0] RD,
input SMPALL,
input [5:0] SMP,
input [2:0] CH,
output [11:0] DAT,
input TSA,
output TSAOUT,
output TSTOUT
);
// DDA has a pulldown on SENSE.
buf (pull1, pull0) pd (SENSE, 0);
wire ON;
wire AL... | 7.489034 |
module dda_timer #(
parameter dda_bits = 64,
parameter phase_angle_bits = 10,
parameter step_encoder_bits = 24
) (
input resetn,
input signed [dda_bits-1:0] increment,
input signed [dda_bits-1:0] incrementincrement,
input loading_move,
input executing_move,
output signed [phase_angle... | 8.355609 |
module ddc (
input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_cordic_out... | 7.490856 |
module ddc65(
// rst_n ,
// clk ,
// data_in ,
// data_out ,
// data_done
// );
//
// input rst_n;
// input clk;
// input [15:0]data_in;
// output[20:0]data_out;
// output data_done;
//
// /*32阶*/
// /*前级积分器*/
// /**中间变量字长 WI = Wi + N*log2(MD) Wi 为输入位宽 N为CIC阶数 M为抽取因子 **/
// reg signed[175:0]I_data_in;
// alway... | 7.551602 |
module ddc65 (
rst_n,
clk,
data_in,
data_out,
data_done
);
input rst_n;
input clk;
input [15:0] data_in;
output [20:0] data_out;
output data_done;
/*32阶*/
/*前级积分器*/
/**中间变量字长 WI = Wi + N*log2(MD) Wi 为输入位宽 N为CIC阶数 M为抽取因子 **/
reg signed [175:0] I_data_in;
always @(posedge clk or ... | 7.242987 |
module DDC_1 (
input wire IN,
output reg [15:0] OUT
);
always @(IN) begin
if (IN == 1'b1) OUT <= 16'b0111111111111111;
else OUT <= 16'b1000000000000000;
end
endmodule
| 6.89196 |
module ddc_chain_tb ();
initial $dumpfile("waves.vcd");
initial $dumpvars(2, ddc_chain_tb.dut_i0);
// Need these declarations to use the task libarary.
`ifndef CHDR_IN_NUMBER
`define CHDR_IN_NUMBER 1
`endif
`ifndef CHDR_OUT_NUMBER
`define CHDR_OUT_NUMBER 1
`endif
reg [63:0] data_in [ `CHDR_IN_NUMBER-1... | 7.027538 |
module ddc_chain_x300_tb ();
`ifdef ISIM
`else //iverilog implied.
// xlnx_glbl glbl (.GSR(),.GTS());
`endif
localparam SR_TX_DSP = 8;
reg clk = 0;
reg reset = 1;
always #10 clk = ~clk;
initial $dumpfile("ddc_chain_x300_tb.vcd");
initial $dumpvars(0, ddc_chain_x300_tb);
reg run = 0;
wire stro... | 6.670006 |
module ddc_iq (
input clk_200m,
input cfg_rst,
input [15:0] data,
input [27:0] fcw_data,
input dac_txenable,
input rx_dds_en,
input [31:0] loop_data,
output [15:0] data_out_i,
output [15:0] data_out_q,
output [255:0] ddc_iq_debug
);
assign data_out_i = dd... | 6.525183 |
module ddc_NCO_Addr_Gen_10bit (
resetn,
Clk_20P48,
NCO_Addr
);
input resetn;
input Clk_20P48;
output [11:0] NCO_Addr;
reg [11:0] NCO_Addr;
parameter NCO_Addr_Fixed = 12'd992; //12M
reg [11:0] Sum_Reg;
always @(posedge Clk_20P48) begin
if (!resetn) begin
Sum_Reg <= 24'd0;
N... | 6.673407 |
module ddc_subch #(
parameter DATAIN_WIDTH = 16,
parameter DATAOUT_WIDTH = DATAIN_WIDTH,
parameter NCO_PHASE_WIDTH = 12,
parameter NCO_WIDTH = 25,
parameter NCO_LUT_FILE = "",
parameter CIC_M = 2,
parameter CIC_N = 5,
parameter CIC_MAXRATE = 64,
... | 6.879386 |
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