code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module ddfs (
clk,
fcontrol,
outp
);
input clk;
input [22:0] fcontrol;
output [7:0] outp;
reg [7:0] outp;
reg [22:0] accum;
reg [8:0] accum_old;
reg sign;
reg [7:0] rom_data[2**9-1:0];
initial begin
$readmemb("rom.dat", rom_data, 0, 2 ** 9 - 1);
accum = 0;
sign = 0;
e... | 6.873945 |
module ddfs_test;
// Inputs
reg clk;
reg [22:0] fcontrol;
// Outputs
wire [7:0] outp;
// Instantiate the Unit Under Test (UUT)
ddfs uut (
.clk(clk),
.fcontrol(fcontrol),
.outp(outp)
);
// 1MHz
always #50 clk = ~clk;
initial begin
clk = 0;
fcontrol = 23'b000001100000... | 6.8879 |
module lab5 (
in,
out
); //模組 lab5(對應的輸入埠與輸出埠)
//宣告區段
input [2:0] in; //宣告輸入埠 in ,其形態為 3bit wire
output [3:0] out; //宣告輸出埠 out ,其形態為 4bit wire
//邏輯區段
assign out[3] = (!in[2] & !in[1] & in[0]) | (in[2] & in[1] & in[0]),
out[2] = (!in[2] & in[1]),
out[1] = (!in[2] & in[1]) | (in[2] & !i... | 6.684648 |
module lab5 (
in,
out
); //模組 lab6(對應的輸入埠與輸出埠)
//宣告區段
input [2:0] in; //宣告輸入埠 in ,其形態為 3bit wire
output [3:0] out; //宣告輸出埠 out ,其形態為 4bit wire
wire nin2, nin1, nin0; //宣告線
wire w0, w1, w2, w3, w4, w5, w6;
//邏輯區段
//使用 not 將 in[2] 的補數訂為線 nin2
not n2 (nin2, in[2]), n1 (nin1, in[1]), n0 (nin... | 6.684648 |
module ddmux ( /*AUTOARG*/
// Outputs
d_in_a,
d_out,
// Inputs
d_in,
d_sel,
d_out_a
);
parameter VCN = 2; // number of output VCs
parameter DW = 32; // data width of the input
input [DW-1:0] d_in;
input [VCN-1:0] d_sel;
output d_in_a;
output [VCN-1:0][DW-1:0] d_out;
input ... | 7.904311 |
module Clock_Divider #(
parameter n = 50000000
) (
input clk,
input reset,
output reg clk_out
);
reg [31:0] counter;
always @(posedge (clk), posedge (reset)) begin
if (reset == 1) begin
counter <= 32'd0;
end else begin
if (counter == n - 1) begin
counter <= 32'd0;
... | 7.076409 |
module debouncer (
clockIn,
reset,
out,
in
);
input in, clockIn, reset;
output out;
reg ff1, ff2, ff3;
always @(posedge clockIn or posedge reset) begin
if (reset == 1'b1) begin
ff1 <= 1'b0;
ff2 <= 1'b0;
ff3 <= 1'b0;
end else begin
ff1 <= in;
ff2 <= ff1;
... | 6.564102 |
module ddp_bram #(
parameter DWIDTH = 0,
parameter LEN = 0,
parameter LOG_LEN = 0
) (
clk,
ena,
enb,
wea,
web,
addra,
addrb,
dla,
dlb,
doa,
dob
); //!!!!!!!a: inpout, b: output!!!!
input clk;
input ena;
input enb;
input wea;
input web;
input [LOG_LEN-... | 7.019368 |
module Ddr2SdramIf_ex_lfsr8 (
clk,
reset_n,
enable,
pause,
load,
data,
ldata
);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output [8 - 1:0] data;
wire [8 - 1:0] data;
input [8 - 1:0] ldata;
reg [8 - 1:0] lfsr_data;
assign da... | 7.864858 |
module Ddr2SdramIf_full_mem_model_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [15:0] q;
input [15:0] data;
input [25:0] rdaddress;
input rdclken;
input [25:0] wraddress;
input wrclock;
input wren;
reg [15:0] ... | 7.254431 |
module ddr2um_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw
);
input aclr;
input [127:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [127:0] q;
output rdempty;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys... | 6.509708 |
module ddr2_12 (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_clk_... | 7.318978 |
module ddr2_12_ex_lfsr8 (
clk,
reset_n,
enable,
pause,
load,
data,
ldata
);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output [8 - 1:0] data;
wire [8 - 1:0] data;
input [8 - 1:0] ldata;
reg [8 - 1:0] lfsr_data;
assign data =... | 7.826848 |
module ddr2_12_full_mem_model_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [31:0] q;
input [31:0] data;
input [23:0] rdaddress;
input rdclken;
input [23:0] wraddress;
input wrclock;
input wren;
reg [31:0] mem_... | 6.919502 |
module ddr2 (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_clk_n,
... | 6.582555 |
module accepts 72-bit input and provides 64-bit output
//
///////////////////////////////////////////////////////////////////////////////
module ddr2_blk_rdwr_fifo_72b_2_64b
(
//----------------------
// wr intfc
//input:
input [71:0] wr_data,
input wr_en,
//output:
output full,
//---------... | 7.85762 |
module vio_sync_out32 (
control,
clk,
sync_out
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input clk;
output [31:0] sync_out;
endmodule
| 6.859998 |
module ddr2_convert (
input CLK,
input RST,
// * control
input req,
output ack,
input [30:0] addr,
input read,
// * write
input [255:0] data_i,
input [ 31:0] mask,
// * read
output valid,
output [127:0] data_o,
// DDR2 IF
in... | 7.086527 |
module vio_sync_out32 (
output [31:0] SYNC_OUT,
input CLK,
inout [35:0] CONTROL
) /* synthesis syn_black_box syn_noprune = 1 */;
endmodule
| 6.859998 |
module instantiates DDR IOB output flip-flops, an
// output buffer with registered tri-state, and an input buffer
// for a single strobe/dqs bit. The DDR IOB output flip-flops
// are used to forward strobe to memory during a write. During
// a ... | 7.670485 |
module ddr2_dram_access_reg #(
parameter DRAM_ADDR_WIDTH = 24, // 2 - BA + 22 - Addr
parameter DRAM_DATA_WIDTH = 64
) (
// Register interface
input reg_req,
input reg_rd_wr_L,
input [DRAM_ADDR_WIDTH - 1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH -1:0] reg_wr_data,
output reg [`CPCI_NF2_... | 8.673244 |
module ddr2_ex_lfsr8 (
clk,
reset_n,
enable,
pause,
load,
data,
ldata
);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output [8 - 1:0] data;
wire [8 - 1:0] data;
input [8 - 1:0] ldata;
reg [8 - 1:0] lfsr_data;
assign data = lf... | 7.922015 |
module instantiates the IDELAYCTRL primitive of the Virtex-5 device
// which continuously calibrates the IDELAY elements in the region in case of
// varying operating conditions. It takes a 200MHz clock as an input
//Reference:
//Revision History:
// Rev 1.1 - Parameter IODELAY_GRP added and constraint IODELAY_GR... | 7.670485 |
module instantiates the IDELAYCTRL primitive of the Virtex-5 device
// which continuously calibrates the IDELAY elements in the region in case of
// varying operating conditions. It takes a 200MHz clock as an input
//Reference:
//Revision History:
// Rev 1.1 - Parameter IODELAY_GRP added and constraint IODELAY_GR... | 7.670485 |
module ddr2_idelay_ctrl_mod (
input clk_100MHz,
input rst
);
parameter IODELAY_GRP = "IODELAY_GRP";
parameter RST_SYNC_NUM = 25;
reg [RST_SYNC_NUM-1:0] rst200_sync_r;
wire clk200, rst200;
wire clk200_ready, idelay_ctrl_rdy;
// Generate 200MHz clock
x2_dcm x2_dcm (
//Outputs
.x2_clk(... | 7.090811 |
module ddr2_mcp (
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_rdqs,
ba,
addr,
dq,
dqs,
dqs_n,
rdqs_n,
odt
);
`include "ddr2_parameters.vh"
// Declare Ports
input ck;
input ck_n;
input [CS_BITS-1:0] cke;
input [CS_BITS-1:0] cs_n;
input ras_n;
... | 6.633438 |
module ddr2_mem_test (
hw_ram_rasn,
hw_ram_casn,
hw_ram_wen,
hw_ram_ba,
hw_ram_udqs_p,
hw_ram_udqs_n,
hw_ram_ldqs_p,
hw_ram_ldqs_n,
hw_ram_udm,
hw_ram_ldm,
hw_ram_ck,
hw_ram_ckn,
hw_ram_cke,
hw_ram_odt,
hw_ram_ad,
hw_ram_dq,
hw_rzq_pin,
hw_zio_pin,... | 7.321502 |
module ddr2_read_control (
input clk_in,
input _rst,
input ena,
input [26:0] addr_read,
//mig
input [127:0] app_rd_data,
input app_rdy,
input app_rd_data_end,
input app_rd_data_valid,
output reg app_en,
output reg [2:0] app_cmd,
output reg [26:0] app_addr
);
//��... | 7.332932 |
module ddr2_sys_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "ddr2_sys_onchip_memory2_0.hex";
output [31:0] readdata;
input [16:0] address;
input [3... | 6.865632 |
module instantiates the addr_gen and the data_gen modules. It takes
// the user data stored in internal FIFOs and gives the data that is to be
// compared with the read data
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module d... | 7.670485 |
module
//****************************************************************
module ddr2_test (
input clk,
input rst_n,
output reg wr_en, //SDRAM 写使能
output reg [31:0] wr_data, //SDRAM 写入的数据
output reg rd_en, //SDRAM 读使能
input [31:0] rd_data, ... | 8.366981 |
module ddr2_traffic_gen (
clk,
reset_n,
pass,
fail,
test_complete,
avl_ready,
avl_addr,
avl_size,
avl_wdata,
avl_rdata,
avl_write_req,
avl_read_req,
avl_rdata_valid,
avl_be,
avl_burstbegin,
pnf_per_bit,
pnf_per_bit_persist
);
input clk;
input rese... | 7.146396 |
module instantiates the block RAM based FIFO to store the user
// address and the command information. Also calculates potential bank/row
// conflicts by comparing the new address with last address issued.
//Reference:
//Revision History:
//***************************************************************************... | 7.670485 |
module ddr2_v10_1_0002_aiigx_hr_write_io (
pll_afi_clk,
pll_write_clk,
wdata_0,
wdata_1,
wdata_2,
wdata_3,
wdata_mask_0,
wdata_mask_1,
wdata_mask_2,
wdata_mask_3,
wdata_en,
wdata_out,
dq_oe,
wdata_mask_out
);
parameter MEM_DQ_WIDTH = "";
parameter MEM_DM_WIDT... | 6.600648 |
module ddr2_v10_1_0002_altera_avalon_st_bytes_to_packets (
input clk,
input reset_n,
input out_ready,
output reg out_valid,
output reg [7:0] out_data,
output reg [7:0] out_channel,
output reg out_startofpacket,
output reg out_endofpacke... | 6.600648 |
module ddr2_v10_1_0002_altera_avalon_st_clock_crosser (
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWAR... | 6.600648 |
module ddr2_v10_1_0002_altera_avalon_st_idle_inserter (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [7:0] in_data,
input out_ready,
output reg out_valid,
output reg [7:0] out_data
);
reg received_... | 6.600648 |
module ddr2_v10_1_0002_altera_avalon_st_idle_remover (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [7:0] in_data,
input out_ready,
output reg out_valid,
output reg [7:0] out_data
);
reg received_e... | 6.600648 |
module ddr2_v10_1_0002_altera_avalon_st_jtag_interface (
clk,
reset_n,
source_ready,
source_data,
source_valid,
sink_data,
sink_valid,
sink_ready,
resetrequest
);
input clk;
input reset_n;
output [7:0] source_data;
input source_ready;
output source_valid;
input [7:0] sink... | 6.600648 |
module ddr2_v10_1_0002_altera_avalon_st_packets_to_bytes (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [7:0] in_data,
input [7:0] in_channel,
input in_startofpacket,
input in_endofpacket,
... | 6.600648 |
module ddr2_v10_1_0002_altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYM... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_bytes_to_packets (
input wire clk, // clk.clk
input wire reset_n, // clk_reset.reset_n
input wire out_ready, // out_packets_stream.ready
output wire out_valid, ... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_channel_adapter_0 (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [7:0] in_data,
input [7:0] in_channel,
input in_startofpacket,
input in_endofp... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_channel_adapter_1 (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [7:0] in_data,
input in_startofpacket,
input in_endofpacket,
input out_r... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_packets_to_bytes (
input wire clk, // clk.clk
input wire reset_n, // clk_reset.reset_n
output wire in_ready, // in_packets_stream.ready
input wire in_valid, // ... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_packets_to_transactions_converter (
input wire clk, // clk.clk
input wire reset_n, // clk_reset.reset_n
input wire out_ready, // out_stream.ready
output wire ... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_sc_fifo (
input wire clk, // clk.clk
input wire reset, // clk_reset.reset
input wire [7:0] in_data, // in.data
input wire in_valid, // .valid
output wire in_ready, // .ready... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_bytes_to_packets_in_bytes_stream_arbitrator (
altera_jtag_avalon_master_bytes_to_packets_in_bytes_stream_ready,
altera_jtag_avalon_master_sc_fifo_out_data,
altera_jtag_avalon_master_sc_fifo_out_valid,
clk,
reset_n,
altera_jtag_avalon_master_bytes... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_bytes_to_packets_out_packets_stream_arbitrator (
altera_jtag_avalon_master_bytes_to_packets_out_packets_stream_channel,
altera_jtag_avalon_master_bytes_to_packets_out_packets_stream_data,
altera_jtag_avalon_master_bytes_to_packets_out_packets_stream_endofpack... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_channel_adapter_0_out_arbitrator (
altera_jtag_avalon_master_channel_adapter_0_out_data,
altera_jtag_avalon_master_channel_adapter_0_out_endofpacket,
altera_jtag_avalon_master_channel_adapter_0_out_startofpacket,
altera_jtag_avalon_master_channel_adapter_... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_channel_adapter_1_out_arbitrator (
altera_jtag_avalon_master_channel_adapter_1_out_channel,
altera_jtag_avalon_master_channel_adapter_1_out_data,
altera_jtag_avalon_master_channel_adapter_1_out_endofpacket,
altera_jtag_avalon_master_channel_adapter_1_out_... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_sc_fifo_out_arbitrator (
altera_jtag_avalon_master_bytes_to_packets_in_bytes_stream_ready_from_sa,
altera_jtag_avalon_master_sc_fifo_out_data,
altera_jtag_avalon_master_sc_fifo_out_valid,
clk,
reset_n,
altera_jtag_avalon_master_sc_fifo_out_ready
... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_packets_to_transactions_converter_out_stream_arbitrator (
altera_jtag_avalon_master_channel_adapter_1_in_ready_from_sa,
altera_jtag_avalon_master_packets_to_transactions_converter_out_stream_data,
altera_jtag_avalon_master_packets_to_transactions_converter_ou... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_jtag_interface_pli_off (
input wire clk, // clock.clk
input wire reset_n, // clock_reset.reset_n
output wire [7:0] source_data, // src.data
output wire source_valid, // .valid
input ... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_jtag_interface_pli_off_src_arbitrator (
altera_jtag_avalon_master_jtag_interface_pli_off_src_data,
altera_jtag_avalon_master_jtag_interface_pli_off_src_valid,
altera_jtag_avalon_master_sc_fifo_in_ready_from_sa,
clk,
reset_n,
altera_jtag_avalon_ma... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_jtag_interface_pli_off_sink_arbitrator (
altera_jtag_avalon_master_jtag_interface_pli_off_sink_ready,
altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_data,
altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_valid,
clk,
reset_n,
... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_arbitrator_pli_off (
altera_jtag_avalon_master_jtag_interface_pli_off_sink_ready_from_sa,
altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_data,
altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_valid,
... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_sc_fifo_in_arbitrator_pli_off (
altera_jtag_avalon_master_jtag_interface_pli_off_src_data,
altera_jtag_avalon_master_jtag_interface_pli_off_src_valid,
altera_jtag_avalon_master_sc_fifo_in_ready,
clk,
reset_n,
altera_jtag_avalon_master_sc_fifo_in_... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_pli_off_reset_clk_domain_synch_module (
clk,
data_in,
reset_n,
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SU... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_jtag_interface_pli_on (
input wire clk, // clock.clk
input wire reset_n, // clock_reset.reset_n
output wire [7:0] source_data, // src.data
output wire source_valid, // .valid
input w... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_jtag_interface_pli_on_sink_arbitrator (
altera_jtag_avalon_master_jtag_interface_pli_on_sink_ready,
altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_data,
altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_valid,
clk,
reset_n,
... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_jtag_interface_pli_on_src_arbitrator (
altera_jtag_avalon_master_jtag_interface_pli_on_src_data,
altera_jtag_avalon_master_jtag_interface_pli_on_src_valid,
altera_jtag_avalon_master_sc_fifo_in_ready_from_sa,
clk,
reset_n,
altera_jtag_avalon_maste... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_arbitrator_pli_on (
altera_jtag_avalon_master_jtag_interface_pli_on_sink_ready_from_sa,
altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_data,
altera_jtag_avalon_master_packets_to_bytes_out_bytes_stream_valid,
... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_sc_fifo_in_arbitrator_pli_on (
altera_jtag_avalon_master_jtag_interface_pli_on_src_data,
altera_jtag_avalon_master_jtag_interface_pli_on_src_valid,
altera_jtag_avalon_master_sc_fifo_in_ready,
clk,
reset_n,
altera_jtag_avalon_master_sc_fifo_in_dat... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_avalon_master_pli_on_reset_clk_domain_synch_module (
clk,
data_in,
reset_n,
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUP... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_control_signal_crosser (
clk,
reset_n,
async_control_signal,
sense_pos_edge,
sync_control_signal
);
input clk;
input reset_n;
input async_control_signal;
input sense_pos_edge;
output sync_control_signal;
parameter SYNC_DEPTH = 3; // number of synchron... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input sink_clk;
input sink_reset_n;
... | 6.600648 |
module ddr2_v10_1_0002_altera_jtag_dc_streaming (
clk,
reset_n,
source_data,
source_valid,
sink_data,
sink_valid,
sink_ready,
resetrequest
);
input clk;
input reset_n;
output [7:0] source_data;
output source_valid;
input [7:0] sink_data;
input sink_valid;
output sink_ready;... | 6.600648 |
module ddr2_v10_1_0002_altera_pli_streaming (
clk,
reset_n,
source_valid,
source_data,
source_ready,
sink_valid,
sink_data,
sink_ready,
resetrequest
);
parameter PLI_PORT = 50000;
parameter PURPOSE = 0;
input clk;
input reset_n;
output reg source_valid;
output reg [... | 6.600648 |
module ddr2_v10_1_0002_alt_ddrx_clock_and_reset #(
parameter CTL_RESET_SYNC_STAGES = 4,
CTL_NUM_RESET_OUTPUT = 1,
CTL_HALF_RESET_SYNC_STAGES = 4,
CTL_HALF_NUM_RESET_OUTPUT = 1
) (
ctl_clk,
ctl_reset_n,
ctl_half_clk,
ctl_half_clk_reset_n,
res... | 6.600648 |
module ddr2_v10_1_0002_alt_ddrx_reset_sync #(
parameter RESET_SYNC_STAGES = 4,
NUM_RESET_OUTPUT = 1
) (
reset_n,
clk,
reset_n_sync
);
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -nam... | 6.600648 |
module ddr2_v10_1_0002_alt_ddrx_ddr3_odt_gen #(
parameter DWIDTH_RATIO = 2,
TCL_BUS_WIDTH = 4,
CAS_WR_LAT_BUS_WIDTH = 4
) (
ctl_clk,
ctl_reset_n,
mem_tcl,
mem_cas_wr_lat,
do_write,
do_read,
int_odt_l,
int_odt_h
);
input ctl_clk;
input c... | 6.600648 |
module ddr2_v10_1_0002_alt_ddrx_decoder #(
parameter INPUT_DATA_WIDTH = 72,
OUTPUT_DATA_WIDTH = 64
) (
ctl_clk,
input_data,
err_corrected,
err_detected,
err_fatal,
output_data
);
input ctl_clk;
input [INPUT_DATA_WIDTH - 1 : 0] input_data;
output [OUTPUT_DATA_WIDTH - 1 : 0] output... | 6.600648 |
module ddr2_v10_1_0002_alt_ddrx_decoder_40 (
clock,
data,
err_corrected,
err_detected,
err_fatal,
q
);
input clock;
input [38:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output [31:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] s... | 6.600648 |
module ddr2_v10_1_0002_alt_ddrx_decoder_72 (
clock,
data,
err_corrected,
err_detected,
err_fatal,
q
);
input clock;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output [63:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [63:0] s... | 6.600648 |
module ddr2_v10_1_0002_alt_ddrx_encoder #(
parameter INPUT_DATA_WIDTH = 64,
OUTPUT_DATA_WIDTH = 72
) (
ctl_clk,
input_data,
output_data
);
input ctl_clk;
input [INPUT_DATA_WIDTH - 1 : 0] input_data;
output [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
wire [OUTPUT_DATA_WIDTH - 1 : 0] output_da... | 6.600648 |
module ddr2_v10_1_0002_alt_ddrx_encoder_40 (
clock,
data,
q
);
input clock;
input [31:0] data;
output [38:0] q;
wire [38:0] sub_wire0;
wire [38:0] q = sub_wire0[38:0];
ddr2_v10_1_0002_alt_ddrx_encoder_40_altecc_encoder_plb ddr2_v10_1_0002_alt_ddrx_encoder_40_altecc_encoder_plb_component (
... | 6.600648 |
module ddr2_v10_1_0002_alt_ddrx_encoder_72 (
clock,
data,
q
);
input clock;
input [63:0] data;
output [71:0] q;
wire [71:0] sub_wire0;
wire [71:0] q = sub_wire0[71:0];
ddr2_v10_1_0002_alt_ddrx_encoder_72_altecc_encoder_rlb ddr2_v10_1_0002_alt_ddrx_encoder_72_altecc_encoder_rlb_component (
... | 6.600648 |
module ddr2_v10_1_0002_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_... | 6.600648 |
module ddr2_v10_1_0002_clock_pair_generator_config (
datain,
dataio,
dataio_b,
dataout,
dynamicterminationcontrol,
dynamicterminationcontrol_b,
oe,
oe_b,
parallelterminationcontrol,
parallelterminationcontrol_b,
seriesterminationcontrol,
seriesterminationcontrol_b
) /* s... | 6.600648 |
module ddr2_v10_1_0002_dll_memphy_altdll_us51 (
dll_clk,
dll_delayctrlout
);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] wire_dll_wys_m_delayctrlout;
stratixiv_dll dll_wys_m (
.clk(dll_clk),
.delayctrlout(wire_dll_wys_m_delayctrlout),
.dqsupdate(),
.offsetdel... | 6.600648 |
module ddr2_v10_1_0002_dll_memphy (
dll_clk,
dll_delayctrlout
);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] sub_wire0;
wire [5:0] dll_delayctrlout = sub_wire0[5:0];
ddr2_v10_1_0002_dll_memphy_altdll_us51 ddr2_v10_1_0002_dll_memphy_altdll_us51_component (
.dll_clk(dll_clk),... | 6.600648 |
module ddr2_v10_1_0002_flop_mem (
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = ""... | 6.600648 |
module ddr2_v10_1_0002_hr_to_fr (
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1_neg;
always @(posedge clk) begin
q_h0 <=... | 6.600648 |
module ddr2_v10_1_0002_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source(),
.clrn(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag... | 6.600648 |
module ddr2_v10_1_0002_iss_source (
source
);
parameter WIDTH = 1;
parameter ID_NAME = "SRCE";
output [WIDTH-1:0] source;
altsource_probe iss_source_inst (
.probe(),
.source(source),
.clrn(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag_state_cir(),... | 6.600648 |
module ddr2_v10_1_0002_memphy_jtag_master (
input wire clk, // clk.clk
input wire reset_n, // clk_reset.reset_n
output wire [31:0] address_from_the_altera_jtag_avalon_master_packets_to_transactions_converter, // master.address
output wire [3:0] byteenable_from_the_altera_jtag_av... | 6.600648 |
module ddr2_v10_1_0002_mem_cq_buf (
datain,
dataout
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
wire [0:0] wire_ibufa_o;
stratixiv_io_ibuf ibufa_0 (
.i(datain),
.o(wire_ibufa_o[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,... | 6.600648 |
module ddr2_v10_1_0002_mem_qk_buf (
datain,
datain_b,
dataout
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
input [0:0] datain_b;
output [0:0] dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] datain_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys transla... | 6.600648 |
module ddr2_v10_1_0002_oct_control (
parallelterminationcontrol,
rdn,
rup,
seriesterminationcontrol
) /* synthesis synthesis_clearbox=1 */;
output [13:0] parallelterminationcontrol;
input [0:0] rdn;
input [0:0] rup;
output [13:0] seriesterminationcontrol;
`ifndef ALTERA_RESERVED_QIS
// synops... | 6.600648 |
module ddr2_v10_1_0002_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] la... | 6.600648 |
module ddr2_v10_1_0002_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
... | 6.600648 |
module ddr2_v10_1_0002_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since ... | 6.600648 |
module ddr2_v10_1_0002_rom_bridge (
write_clock,
rom_address,
rom_data,
rom_rden,
init,
rom_data_ready,
init_busy,
avlm_address,
avlm_writedata,
avlm_wren,
avlm_waitrequest
);
parameter AVL_DATA_WIDTH = 32;
parameter AVL_ADDR_WIDTH = 12;
input write_clock;
output... | 6.600648 |
module ddr2_v10_1_0002_rom_bridge_0 (
input wire write_clock, // write_clock.clk
output wire [13:0] rom_address, // export_interface.export
input wire [31:0] rom_data, // .export
output wire rom_rden, // .export
input wi... | 6.600648 |
module ddr2_v10_1_0002_sequencer_bridge (
// Avalon Interface
avlf_clk,
avlf_reset_n,
avlf_address,
avlf_write,
avlf_writedata,
avlf_read,
avlf_readdata,
avlf_waitrequest,
// PHY control
avlt_clk,
avlt_reset_n,
avlt_address,
avlt_write,
avlt_writedata,
... | 6.600648 |
module ddr2_v10_1_0002_sequencer_bridge_0 (
input wire avlf_clk, // clock_sink.clk
input wire avlf_reset_n, // .reset_n
input wire [15:0] avlf_address, // avalon_slave.address
input wire avlf_write, // .write
input wire [3... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_rf_module (
// inputs:
address_a,
address_b,
clock0,
clock1,
clocken0,
... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
... | 6.600648 |
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