code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ddr2_v10_1_0002_sequencer_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [18:... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_co... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or ... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_c... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_traceram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
... | 6.600648 |
module ddr2_v10_1_0002_sequencer_cpu_nios2_performance_monitors;
endmodule
| 6.600648 |
module ddr2_v10_1_0002_sequencer_ctrl_reset_clk_0_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_RE... | 6.600648 |
module ddr2_v10_1_0002_sequencer_ctrl_reset_rom_write_clock_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; P... | 6.600648 |
module ddr2_v10_1_0002_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [9:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input write;
i... | 6.600648 |
module ddr2_v10_1_0002_sequencer_raminit (
clock,
datain,
init,
rom_data_ready,
dataout,
init_busy,
ram_address,
ram_wren,
rom_address,
rom_rden
);
input clock;
input [31:0] datain;
input init;
input rom_data_ready;
output [31:0] dataout;
output init_busy;
output [... | 6.600648 |
module ddr2_v10_1_0002_sequencer_rom (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
... | 6.600648 |
module ddr2_v10_1_0002_write_datapath (
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask
);
parameter MEM... | 6.600648 |
module ddr2_v10_1_0002_write_mask_iobuf (
datain,
dataout,
parallelterminationcontrol,
seriesterminationcontrol
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
input [13:0] parallelterminationcontrol;
input [13:0] seriesterminationcontrol;
`ifndef ALTERA_RESERV... | 6.600648 |
module ddr2_v10_1_aiigx_hr_write_io (
pll_afi_clk,
pll_write_clk,
wdata_0,
wdata_1,
wdata_2,
wdata_3,
wdata_mask_0,
wdata_mask_1,
wdata_mask_2,
wdata_mask_3,
wdata_en,
wdata_out,
dq_oe,
wdata_mask_out
);
parameter MEM_DQ_WIDTH = "";
parameter MEM_DM_WIDTH = "... | 6.588842 |
module ddr2_v10_1_flop_mem (
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = "";
p... | 7.530528 |
module ddr2_v10_1_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source(),
.clrn(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag_stat... | 6.855453 |
module ddr2_v10_1_iss_source (
source
);
parameter WIDTH = 1;
parameter ID_NAME = "SRCE";
output [WIDTH-1:0] source;
altsource_probe iss_source_inst (
.probe(),
.source(source),
.clrn(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag_state_cir(),
... | 6.855453 |
module ddr2_v10_1_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency... | 7.145599 |
module ddr2_v10_1_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
re... | 7.145599 |
module ddr2_v10_1_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these... | 7.145599 |
module ddr2_v10_1_rom_bridge (
write_clock,
rom_address,
rom_data,
rom_rden,
init,
rom_data_ready,
init_busy,
avlm_address,
avlm_writedata,
avlm_wren,
avlm_waitrequest
);
parameter AVL_DATA_WIDTH = 32;
parameter AVL_ADDR_WIDTH = 12;
input write_clock;
output [AVL... | 7.584321 |
module ddr2_v10_1_rom_bridge_0 (
input wire write_clock, // write_clock.clk
output wire [13:0] rom_address, // export_interface.export
input wire [31:0] rom_data, // .export
output wire rom_rden, // .export
input wire ... | 7.584321 |
module ddr2_v10_1_sequencer_bridge (
// Avalon Interface
avlf_clk,
avlf_reset_n,
avlf_address,
avlf_write,
avlf_writedata,
avlf_read,
avlf_readdata,
avlf_waitrequest,
// PHY control
avlt_clk,
avlt_reset_n,
avlt_address,
avlt_write,
avlt_writedata,
avlt_... | 7.047126 |
module ddr2_v10_1_sequencer_bridge_0 (
input wire avlf_clk, // clock_sink.clk
input wire avlf_reset_n, // .reset_n
input wire [15:0] avlf_address, // avalon_slave.address
input wire avlf_write, // .write
input wire [31:0] ... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_rf_module (
// inputs:
address_a,
address_b,
clock0,
clock1,
clocken0,
... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocir... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [18:0] cp... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assi... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count =... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_re... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_traceram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
tr... | 7.047126 |
module ddr2_v10_1_sequencer_cpu_nios2_performance_monitors;
endmodule
| 7.047126 |
module ddr2_v10_1_sequencer_ctrl_reset_clk_0_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTE... | 7.047126 |
module ddr2_v10_1_sequencer_ctrl_reset_rom_write_clock_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESER... | 7.047126 |
module ddr2_v10_1_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [9:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input write;
input ... | 7.047126 |
module ddr2_v10_1_sequencer_raminit (
clock,
datain,
init,
rom_data_ready,
dataout,
init_busy,
ram_address,
ram_wren,
rom_address,
rom_rden
);
input clock;
input [31:0] datain;
input init;
input rom_data_ready;
output [31:0] dataout;
output init_busy;
output [11:0]... | 7.047126 |
module ddr2_v10_1_sequencer_rom (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
... | 7.047126 |
module ddr2_v10_1_write_datapath (
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask
);
parameter MEM_ADDR... | 6.636772 |
module ddr2_v10_1_write_mask_iobuf (
datain,
dataout,
parallelterminationcontrol,
seriesterminationcontrol
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
input [13:0] parallelterminationcontrol;
input [13:0] seriesterminationcontrol;
`ifndef ALTERA_RESERVED_QI... | 6.636772 |
module ddr2_v12_1_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";... | 7.543121 |
module ddr2_v12_1_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_ob... | 7.543121 |
module ddr2_v12_1_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_A... | 7.543121 |
module ddr2_v12_1_p0_fr_cycle_extender (
clk,
reset_n,
extend_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their ... | 7.543121 |
module ddr2_v12_1_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their va... | 7.543121 |
module ddr2_v12_1_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_out(),
... | 7.543121 |
module ddr2_v12_1_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] late... | 7.543121 |
module ddr2_v12_1_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
reset_n_afi_clk,
re... | 7.543121 |
module ddr2_v12_1_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since th... | 7.543121 |
module ddr2_write_control (
clk_in,
_rst,
I_ADDR,
I_DATA,
I_STB,
O_ACK,
en_read,
//mig
app_en,
app_wdf_wren,
app_wdf_end,
app_cmd,
app_addr,
app_wdf_data,
app_rdy,
app_wdf_rdy
);
parameter DQ_WIDTH = 16;
parameter ECC_TEST = "OFF";
parameter ADDR_WI... | 6.972716 |
module ddr2_wr_sim ();
reg clk;
reg rst;
reg [127:0] data;
reg [26:0] addr;
reg stb;
wire ack;
//DDR2参数
//ddr2 parameter
wire [15:0] ddr2_dq;
wire [1:0] ddr2_dqs_n;
wire [1:0] ddr2_dqs_p;
wire [12:0] ddr2_addr;
wire [2:0] ddr2_ba;
wire ddr2_ras_n;
wire ddr2_cas_n;
wire ddr2_we_n;
wir... | 7.125743 |
module row_addr_tab (
WrAddress,
RdAddress,
Data,
WrClock,
WrClockEn,
WE,
Q
);
input [5:0] WrAddress;
input [5:0] RdAddress;
input [`ROW_WIDTH-1:0] Data;
input WrClock;
input WrClockEn;
input WE;
output [`ROW_WIDTH-1:0] Q;
defparam pmi_distributed_dpram.pmi_addr_depth = 64;... | 6.541172 |
module ddr3_afifo #(
parameter ADDR_WIDTH = 30,
parameter DATA_WIDTH = 32
) (
input i_sys_clk,
input i_ddr_clk,
// Write-Side Ports
input i_cmd_en, // Command Enable
input [ 2:0] i_cmd_instr, // write = 000, read = 001
input [ADDR_WIDTH-1:0] i_... | 8.048518 |
module ddr3_altera_avalon_onchip_memory2_181_fwqs2dy (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "seq_cal_soft_m20k.hex";
output [31:0] rea... | 7.509588 |
module ddr3_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Por... | 7.732727 |
module ddr3_axi_pmem_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//---------------------------------------------------------------... | 7.687225 |
modules
//-----------------------------------------------------------------
module ddr3_axi_retime_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter... | 7.831093 |
module ddr3_clkgen ( // Clock in ports
input clk50in,
// Clock out ports
output clk50,
output clk400,
output clk100,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
BUFG clkin1_buf (
.O(clkin1),
.... | 7.216545 |
module ddr3_clkgen_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
... | 7.694799 |
module ddr3_dev (
input clk,
input clk_ddr,
input clk_ref,
input rst,
input [ 31:0] addr_i,
input [255:0] data_i,
output [255:0] data_o,
input we_i,
input rd_i,
output ack_o,
inout [31:0] ddr3_dq,
inout [ 3:0] ddr3_dqs_n,
inout [ 3:0] ... | 7.074859 |
module ddr3_dfi_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 144,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------
... | 7.433513 |
module ddr3_dma_mux (
clk,
rst,
write_req,
write_app_cmd,
write_app_addr,
write_app_en,
read_req,
read_app_cmd,
read_app_addr,
read_app_en,
app_cmd,
app_addr,
app_en
);
input clk;
input rst;
input write_req;
input [2:0] write_app_cmd;
input [29:0] write... | 7.657345 |
module ddr3_dma_write (
clk,
ddr_clk,
rst,
//ddr3 Interface
init_calib_complete,
app_addr,
app_cmd,
app_rdy,
app_en,
app_wdf_data,
app_wdf_rdy,
app_wdf_wren,
app_wdf_end,
//dma Interface
write_req,
write_start_addr,
write_length,
write_done,
... | 6.898513 |
module ddr3_init_sm (
rst,
clk,
init_done,
init_start
);
input wire rst;
input wire clk;
input wire init_done;
output reg init_start;
reg [7:0] init_dly_cnt;
parameter IDLE = 3'b000,
START_CNT = 3'b001,
WAITFOR_CNT = 3'b010,
INIT_DDR = 3'b011,
INIT_DONE = 3'b100;
reg [2:0] ... | 7.324937 |
module ddr3_interface_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "fal... | 7.71922 |
module ddr3_interface_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wir... | 7.71922 |
module ddr3_interface_p0_generic_ddio (
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0]... | 7.71922 |
module ddr3_interface_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
.ir_out(),
... | 7.71922 |
module ddr3_interface_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,... | 7.71922 |
module ddr3_interface_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Sinc... | 7.71922 |
module ddr3_mcp (
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
`include "1024Mb_ddr3_parameters.vh"
// Declare Ports
input rst_n;
input ck;
input ck_n;
input [CS_BITS-1:0] cke;
input [CS_... | 7.361916 |
module ddr3_mem_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADD... | 7.742112 |
module ddr3_mem_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their valu... | 7.742112 |
module ddr3_mem_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
.ir_out(),
.j... | 6.82917 |
module ddr3_mem_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latenc... | 7.973427 |
module ddr3_mem_p0_reset_m10 (
pll_afi_clk,
pll_write_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_resync_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input pll_afi_clk;
input pll_writ... | 7.973427 |
module ddr3_mem_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since thes... | 7.973427 |
module ddr3_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WI... | 8.357243 |
module ddr3_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values p... | 7.587312 |
module ddr3_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_... | 6.756284 |
module ddr3_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_sh... | 7.047169 |
module ddr3_p0_reset_m10 (
pll_afi_clk,
pll_write_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_resync_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input pll_afi_clk;
input pll_write_cl... | 7.559002 |
module ddr3_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these re... | 7.559002 |
module ddr3_pll (CLK, RESET, DPHASE0, DPHASE1, DPHASE2, DPHASE3, CLKOP,
CLKOS, CLKOK, LOCK)/* synthesis syn_noprune=1 */;//pragma attribute ddr3_pll dont_touch true
input wire CLK;
input wire RESET;
input wire DPHASE0;
input wire DPHASE1;
input wire DPHASE2;
input wire DPHASE3;
output ... | 7.225397 |
module ddr3_ring_buffer8 (
dout,
listen,
strobe,
readPtr,
din,
reset
);
input listen; // A cycle long pulse after which ring buffer would start paying attention towards the incoming strobe
input strobe; // After listen the ring buffer would capture 4 data at every edges of strobe
input r... | 6.642275 |
module ddr3_s4_uniphy_example_if0_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_dll_memphy_altdll_5s51 (
dll_clk,
dll_delayctrlout
);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] wire_dll_wys_m_delayctrlout;
stratixiv_dll dll_wys_m (
.clk(dll_clk),
.delayctrlout(wire_dll_wys_m_delayctrlout),
.dqsupdate(),
... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_dll_memphy (
dll_clk,
dll_delayctrlout
);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] sub_wire0;
wire [5:0] dll_delayctrlout = sub_wire0[5:0];
ddr3_s4_uniphy_example_if0_p0_dll_memphy_altdll_5s51 ddr3_s4_uniphy_example_if0_p0_dll_memphy_altdll... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_flop_mem (
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_A... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" wi... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_hr_to_fr (
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1_neg;
always @(posedge clk) beg... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_oct_control (
parallelterminationcontrol,
rdn,
rup,
seriesterminationcontrol
) /* synthesis synthesis_clearbox=1 */;
output [13:0] parallelterminationcontrol;
input [0:0] rdn;
input [0:0] rup;
output [13:0] seriesterminationcontrol;
`ifndef ALTERA_RESERVED_Q... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wr... | 6.60431 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.