code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SLT8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_inst0_O;
wire LUT3_inst0_O;
Sub8_cin1 Sub8_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub8_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub8_cin1_inst0_O[7]),
.I1(... | 7.008963 |
module Add2_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input CIN
);
assign O = 2'((2'(({1'b0, CIN}) + I0)) + I1);
endmodule
| 7.779783 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add2_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input CIN
);
wire bit_const_0_None_out;
wire [1:0] coreir_add2_inst0_out;
wire [1:0] coreir_add2_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(2)
) coreir_ad... | 7.779783 |
module Add2_cout_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT,
input CIN
);
wire [2:0] coreir_add3_inst0_out;
assign coreir_add3_inst0_out = 3'((3'(({1'b0, 1'b0, CIN}) + ({1'b0, I0}))) + ({1'b0, I1}));
assign O = coreir_add3_inst0_out[1:0];
assign COUT = coreir_add3_inst... | 8.275035 |
module Sub2_cout_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT,
input CIN
);
wire [1:0] Invert2_inst0_out;
wire not_inst0_out;
Add2_cout_cin Add2_cout_cin_inst0 (
.I0(I0),
.I1(Invert2_inst0_out),
.O(O),
.COUT(COUT),
.CIN(not_inst0_out)
);
a... | 7.568739 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add2_cout_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT,
input CIN
);
wire bit_const_0_None_out;
wire [2:0] coreir_add3_inst0_out;
wire [2:0] coreir_add3_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [2:0] coreir_add... | 8.275035 |
module Sub2_cout_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT,
input CIN
);
wire [1:0] Add2_cout_cin_inst0_O;
wire Add2_cout_cin_inst0_COUT;
wire [1:0] Invert2_inst0_out;
wire not_inst0_out;
Add2_cout_cin Add2_cout_cin_inst0 (
.I0(I0),
.I1(Invert2_inst0_out... | 7.568739 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN_COUT (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(F... | 7.152261 |
module Sub2_cin_cout (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT1_inst0_O;
LUT2 #(
.INIT(4'h9)
) LUT2_inst0 (
.... | 6.568817 |
module Sub2_cin_cout (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT1_inst0_O... | 6.568817 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(FullAdder_inst0_O),
... | 6.821676 |
module Sub2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire [1:0] Invert2_inst0_O;
wire [1:0] Add2_CIN_inst0_O;
wire SB_LUT4_inst0_O;
Invert2 Invert2_inst0 (
.I(I1),
.O(Invert2_inst0_O)
);
Add2_CIN Add2_CIN_inst0 (
.I0 (I0),
.I1 (Invert2_inst0_... | 6.641859 |
module Add2_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input CIN
);
assign O = 2'((2'(({1'b0, CIN}) + I0)) + I1);
endmodule
| 7.779783 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add2_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input CIN
);
wire bit_const_0_None_out;
wire [1:0] coreir_add2_inst0_out;
wire [1:0] coreir_add2_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(2)
) coreir_ad... | 7.779783 |
module Add2_cout_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT,
input CIN
);
wire [2:0] coreir_add3_inst0_out;
assign coreir_add3_inst0_out = 3'((3'(({1'b0, 1'b0, CIN}) + ({1'b0, I0}))) + ({1'b0, I1}));
assign O = coreir_add3_inst0_out[1:0];
assign COUT = coreir_add3_inst... | 8.275035 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add2_cout_cin (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT,
input CIN
);
wire bit_const_0_None_out;
wire [2:0] coreir_add3_inst0_out;
wire [2:0] coreir_add3_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [2:0] coreir_add... | 8.275035 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN_COUT (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(F... | 7.152261 |
module Sub2_COUT (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire [1:0] Invert2_inst0_O;
wire [1:0] Add2_CIN_COUT_inst0_O;
wire Add2_CIN_COUT_inst0_COUT;
Invert2 Invert2_inst0 (
.I(I1),
.O(Invert2_inst0_O)
);
Add2_CIN_COUT Add2_CIN_COUT_inst0 (
.I0(I0),... | 7.093823 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(FullAdder_inst0_O),
... | 6.821676 |
module Add4_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
input CIN
);
assign O = 4'((4'(({1'b0, 1'b0, 1'b0, CIN}) + I0)) + I1);
endmodule
| 7.761374 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add4_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
input CIN
);
wire bit_const_0_None_out;
wire [3:0] coreir_add4_inst0_out;
wire [3:0] coreir_add4_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(4)
) coreir_ad... | 7.761374 |
module Add4_cout_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT,
input CIN
);
wire [4:0] coreir_add5_inst0_out;
assign coreir_add5_inst0_out = 5'((5'(({1'b0,1'b0,1'b0,1'b0,CIN}) + ({1'b0,I0}))) + ({1'b0,I1}));
assign O = coreir_add5_inst0_out[3:0];
assign COUT = coreir_add... | 8.467947 |
module Sub4_cout_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT,
input CIN
);
wire [3:0] Invert4_inst0_out;
wire not_inst0_out;
Add4_cout_cin Add4_cout_cin_inst0 (
.I0(I0),
.I1(Invert4_inst0_out),
.O(O),
.COUT(COUT),
.CIN(not_inst0_out)
);
a... | 7.750468 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add4_cout_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT,
input CIN
);
wire bit_const_0_None_out;
wire [4:0] coreir_add5_inst0_out;
wire [4:0] coreir_add5_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [4:0] coreir_add... | 8.467947 |
module Sub4_cout_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT,
input CIN
);
wire [3:0] Add4_cout_cin_inst0_O;
wire Add4_cout_cin_inst0_COUT;
wire [3:0] Invert4_inst0_out;
wire not_inst0_out;
Add4_cout_cin Add4_cout_cin_inst0 (
.I0(I0),
.I1(Invert4_inst0_out... | 7.750468 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN_COUT (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.712749 |
module Sub4_CIN_COUT (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire [3:0] Invert4_inst0_O;
wire [3:0] Add4_CIN_COUT_inst0_O;
wire Add4_CIN_COUT_inst0_COUT;
wire SB_LUT4_inst0_O;
Invert4 Invert4_inst0 (
.I(I1),
.O(Invert4_inst0_O)
);
Add4_CI... | 6.63285 |
module Sub4_cin_cout (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire L... | 6.887831 |
module Sub4_cin_cout (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2... | 6.887831 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
Ful... | 7.507677 |
module Sub4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire [3:0] Invert4_inst0_O;
wire [3:0] Add4_CIN_inst0_O;
wire SB_LUT4_inst0_O;
Invert4 Invert4_inst0 (
.I(I1),
.O(Invert4_inst0_O)
);
Add4_CIN Add4_CIN_inst0 (
.I0 (I0),
.I1 (Invert4_inst0_... | 6.709145 |
module Add4_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
input CIN
);
assign O = 4'((4'(({1'b0, 1'b0, 1'b0, CIN}) + I0)) + I1);
endmodule
| 7.761374 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add4_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
input CIN
);
wire bit_const_0_None_out;
wire [3:0] coreir_add4_inst0_out;
wire [3:0] coreir_add4_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(4)
) coreir_ad... | 7.761374 |
module Add4_cout_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT,
input CIN
);
wire [4:0] coreir_add5_inst0_out;
assign coreir_add5_inst0_out = 5'((5'(({1'b0,1'b0,1'b0,1'b0,CIN}) + ({1'b0,I0}))) + ({1'b0,I1}));
assign O = coreir_add5_inst0_out[3:0];
assign COUT = coreir_add... | 8.467947 |
module Sub4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire [3:0] Invert4_inst0_out;
Add4_cout_cin Add4_cout_cin_inst0 (
.I0(I0),
.I1(Invert4_inst0_out),
.O(O),
.COUT(COUT),
.CIN(1'b1)
);
assign Invert4_inst0_out = ~I1;
endmodule
| 6.96229 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add4_cout_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT,
input CIN
);
wire bit_const_0_None_out;
wire [4:0] coreir_add5_inst0_out;
wire [4:0] coreir_add5_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [4:0] coreir_add... | 8.467947 |
module Sub4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire [3:0] Add4_cout_cin_inst0_O;
wire Add4_cout_cin_inst0_COUT;
wire [3:0] Invert4_inst0_out;
wire bit_const_1_None_out;
Add4_cout_cin Add4_cout_cin_inst0 (
.I0(I0),
.I1(Invert4_inst0_out),
.O(... | 6.96229 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN_COUT (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.712749 |
module Sub4_COUT (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire [3:0] Invert4_inst0_O;
wire [3:0] Add4_CIN_COUT_inst0_O;
wire Add4_CIN_COUT_inst0_COUT;
Invert4 Invert4_inst0 (
.I(I1),
.O(Invert4_inst0_O)
);
Add4_CIN_COUT Add4_CIN_COUT_inst0 (
.I0(I0),... | 7.489469 |
module Sub4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire... | 6.96229 |
module Sub4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_... | 6.96229 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
Ful... | 7.507677 |
module Add8_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
input CIN
);
assign O = 8'((8'(({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, CIN}) + I0)) + I1);
endmodule
| 8.416699 |
module Sub8_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
input CIN
);
wire [7:0] Invert8_inst0_out;
wire not_inst0_out;
Add8_cin Add8_cin_inst0 (
.I0 (I0),
.I1 (Invert8_inst0_out),
.O (O),
.CIN(not_inst0_out)
);
assign Invert8_inst0_out = ~I1;
assign not_ins... | 6.745054 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add8_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
input CIN
);
wire bit_const_0_None_out;
wire [7:0] coreir_add8_inst0_out;
wire [7:0] coreir_add8_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(8)
) coreir_ad... | 8.416699 |
module Sub8_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
input CIN
);
wire [7:0] Add8_cin_inst0_O;
wire [7:0] Invert8_inst0_out;
wire not_inst0_out;
Add8_cin Add8_cin_inst0 (
.I0 (I0),
.I1 (Invert8_inst0_out),
.O (Add8_cin_inst0_O),
.CIN(not_inst0_out)
);
co... | 6.745054 |
module Add8_cout_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT,
input CIN
);
wire [8:0] coreir_add9_inst0_out;
assign coreir_add9_inst0_out = 9'((9'(({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CIN}) + ({1'b0,I0}))) + ({1'b0,I1}));
assign O = coreir_add9_inst0_out[7:0];
assi... | 8.324529 |
module Sub8_cout_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT,
input CIN
);
wire [7:0] Invert8_inst0_out;
wire not_inst0_out;
Add8_cout_cin Add8_cout_cin_inst0 (
.I0(I0),
.I1(Invert8_inst0_out),
.O(O),
.COUT(COUT),
.CIN(not_inst0_out)
);
a... | 7.823153 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add8_cout_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT,
input CIN
);
wire bit_const_0_None_out;
wire [8:0] coreir_add9_inst0_out;
wire [8:0] coreir_add9_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [8:0] coreir_add... | 8.324529 |
module Sub8_cout_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT,
input CIN
);
wire [7:0] Add8_cout_cin_inst0_O;
wire Add8_cout_cin_inst0_COUT;
wire [7:0] Invert8_inst0_out;
wire not_inst0_out;
Add8_cout_cin Add8_cout_cin_inst0 (
.I0(I0),
.I1(Invert8_inst0_out... | 7.823153 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN_COUT (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.252533 |
module Sub8_CIN_COUT (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire [7:0] Invert8_inst0_O;
wire [7:0] Add8_CIN_COUT_inst0_O;
wire Add8_CIN_COUT_inst0_COUT;
wire SB_LUT4_inst0_O;
Invert8 Invert8_inst0 (
.I(I1),
.O(Invert8_inst0_O)
);
Add8_CI... | 7.015307 |
module Sub8_cin_cout (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire L... | 7.026868 |
module Sub8_cin_cout (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2... | 7.026868 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.