code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module design_1_xup_nand2_0_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_nand2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_nand2_0_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h7)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_nor2_0_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_nor2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_nor2_0_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h1)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_xor2_0_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_xor2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_xor2_0_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h6)
) y_INST_0 (
.I0(b),
.I1(a),
.O (y)
);
endmodule
| 6.893999 |
module design_2_design_1_wrapper_0_0 (
A1,
A2,
D0,
D1,
D2,
D3,
EN
);
input A1;
input A2;
output D0;
output D1;
output D2;
output D3;
input EN;
wire A1;
wire A2;
wire D0;
wire D1;
wire D2;
wire D3;
wire EN;
design_2_design_1_wrapper_0_0_design_1_wrapper U0 (
... | 6.828867 |
module design_2_design_1_wrapper_0_0_design_1 (
D0,
D1,
D2,
D3,
EN,
A2,
A1
);
output D0;
output D1;
output D2;
output D3;
input EN;
input A2;
input A1;
wire A1;
wire A2;
wire D0;
wire D1;
wire D2;
wire D3;
wire EN;
wire xup_and2_4_y;
wire xup_and2_5_y;
wire... | 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_wrapper (
D0,
D1,
D2,
D3,
EN,
A2,
A1
);
output D0;
output D1;
output D2;
output D3;
input EN;
input A2;
input A1;
wire A1;
wire A2;
wire D0;
wire D1;
wire D2;
wire D3;
wire EN;
design_2_design_1_wrapper_0_0_design_... | 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_and2_0_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_and2_0_1 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_and2_0_2 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_and2_0_3 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_and2_0_4 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_and2_0_5 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_and2_0_6 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_and2_0_7 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_inv_0_0 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_0_design_1_xup_inv_0_1 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1 (
D0,
D1,
D2,
D3,
EN,
A2,
A1
);
output D0;
output D1;
output D2;
output D3;
input EN;
input A2;
input A1;
wire A1;
wire A2;
wire D0;
wire D1;
wire D2;
wire D3;
wire EN;
wire xup_and2_4_y;
wire xup_and2_5_y;
wire... | 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_wrapper (
D0,
D1,
D2,
D3,
EN,
A2,
A1
);
output D0;
output D1;
output D2;
output D3;
input EN;
input A2;
input A1;
wire A1;
wire A2;
wire D0;
wire D1;
wire D2;
wire D3;
wire EN;
design_2_design_1_wrapper_0_1_design_... | 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_and2_0_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_and2_0_1 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_and2_0_2 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_and2_0_3 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_and2_0_4 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_and2_0_5 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_and2_0_6 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_and2_0_7 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_inv_0_0 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1_design_1_xup_inv_0_1 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 6.828867 |
module design_2_design_1_wrapper_0_1 (
A1,
A2,
D0,
D1,
D2,
D3,
EN
);
input A1;
input A2;
output D0;
output D1;
output D2;
output D3;
input EN;
wire A1;
wire A2;
wire D0;
wire D1;
wire D2;
wire D3;
wire EN;
design_2_design_1_wrapper_0_1_design_1_wrapper U0 (
... | 6.828867 |
module design_2_xup_inv_0_0 (
a,
y
);
input wire a;
output wire y;
xup_inv #(
.DELAY(3)
) inst (
.a(a),
.y(y)
);
endmodule
| 6.881122 |
module design_2_xup_inv_0_0 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 6.881122 |
module design_6_1_xup_and2_0_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 7.289269 |
module design_6_1_xup_inv_0_0 (
a,
y
);
input wire a;
output wire y;
xup_inv #(
.DELAY(3)
) inst (
.a(a),
.y(y)
);
endmodule
| 7.289269 |
module design_6_1_xup_or2_0_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_or2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 7.289269 |
module design_6_1_xup_or2_0_1 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_or2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 7.289269 |
module design_6_1_xup_or4_0_0 (
a,
b,
c,
d,
y
);
input wire a;
input wire b;
input wire c;
input wire d;
output wire y;
xup_or4 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.c(c),
.d(d),
.y(y)
);
endmodule
| 7.289269 |
module AMBA_APB (
P_clk,
P_rst,
P_addr,
P_selx,
P_enable,
P_write,
P_wdata,
P_ready,
P_slverr,
P_rdata
);
//input configration
input P_clk;
input P_rst;
input [31:0] P_addr;
input P_selx;
input P_enable;
input P_write;
input [31:0] P_wdata;
//output configrat... | 8.037126 |
module design_clocks (
// differential clock inputs
input clk_in_p, //200 MHz
input clk_in_n,
// asynchronous control/resets
input glbl_rst,
output dcm_locked,
// clock outputs
output gtx_clk_bufg, //125 MHz
output refclk_bufg, //200 MHz
output s_axi_aclk, //100 MHz
... | 7.540241 |
module float32_point_adder (
A,
B,
C
);
input [0:31] A, B;
output [0:31] C;
wire exc;
wire op_sub_add;
wire c_enable;
wire output_sign;
wire [0:31] op_a, op_b, temp_c;
wire [0:23] significand_a, significand_b;
wire [0:7] exponent_diff;
wire [0:23] significand_b_add_sub;
wire [0:7] ... | 7.459953 |
module design_lab_8_xup_and2_0_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_0_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_0_1 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_0_1 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_1_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_1_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_3_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_3_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_4_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_4_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_5_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and2_5_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and4_0_0 (
a,
b,
c,
d,
y
);
input wire a;
input wire b;
input wire c;
input wire d;
output wire y;
xup_and4 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.c(c),
.d(d),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and4_0_0 (
a,
b,
c,
d,
y
);
input a;
input b;
input c;
input d;
output y;
wire a;
wire b;
wire c;
wire d;
wire y;
design_lab_8_xup_and4_0_0_xup_and4 inst (
.a(a),
.b(b),
.c(c),
.d(d),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_and4_0_0_xup_and4 (
y,
d,
a,
b,
c
);
output y;
input d;
input a;
input b;
input c;
wire a;
wire b;
wire c;
wire d;
wire y;
LUT4 #(
.INIT(16'h8000)
) y__0 (
.I0(d),
.I1(a),
.I2(b),
.I3(c),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_dff_en_reset_0_0 (
d,
clk,
en,
reset,
q
);
input wire d;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
i... | 7.197647 |
module design_lab_8_xup_dff_en_reset_0_0 (
d,
clk,
en,
reset,
q
);
input d;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input clk;
in... | 7.197647 |
module design_lab_8_xup_dff_en_reset_0_0_xup_dff_en_reset (
q,
clk,
en,
d,
reset
);
output q;
input clk;
input en;
input d;
input reset;
wire clk;
wire d;
wire en;
wire q;
wire q_i_1_n_0;
wire reset;
LUT4 #(
.INIT(16'h00E2)
) q_i_1 (
.I0(q),
.I1(en),
... | 7.197647 |
module design_lab_8_xup_dff_en_reset_0_1 (
d,
clk,
en,
reset,
q
);
input wire d;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
i... | 7.197647 |
module design_lab_8_xup_dff_en_reset_0_1 (
d,
clk,
en,
reset,
q
);
input d;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input clk;
in... | 7.197647 |
module design_lab_8_xup_dff_en_reset_0_1_xup_dff_en_reset (
q,
clk,
en,
d,
reset
);
output q;
input clk;
input en;
input d;
input reset;
wire clk;
wire d;
wire en;
wire q;
wire q_i_1_n_0;
wire reset;
LUT4 #(
.INIT(16'h00E2)
) q_i_1 (
.I0(q),
.I1(en),
... | 7.197647 |
module design_lab_8_xup_dff_en_reset_0_2 (
d,
clk,
en,
reset,
q
);
input wire d;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
i... | 7.197647 |
module design_lab_8_xup_dff_en_reset_0_2 (
d,
clk,
en,
reset,
q
);
input d;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input clk;
in... | 7.197647 |
module design_lab_8_xup_dff_en_reset_0_2_xup_dff_en_reset (
q,
clk,
en,
d,
reset
);
output q;
input clk;
input en;
input d;
input reset;
wire clk;
wire d;
wire en;
wire q;
wire q_i_1_n_0;
wire reset;
LUT4 #(
.INIT(16'h00E2)
) q_i_1 (
.I0(q),
.I1(en),
... | 7.197647 |
module design_lab_8_xup_inv_0_0 (
a,
y
);
input wire a;
output wire y;
xup_inv #(
.DELAY(3)
) inst (
.a(a),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_inv_0_0 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_inv_0_1 (
a,
y
);
input wire a;
output wire y;
xup_inv #(
.DELAY(3)
) inst (
.a(a),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_inv_0_1 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_inv_0_2 (
a,
y
);
input wire a;
output wire y;
xup_inv #(
.DELAY(3)
) inst (
.a(a),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_inv_0_2 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_inv_0_3 (
a,
y
);
input wire a;
output wire y;
xup_inv #(
.DELAY(3)
) inst (
.a(a),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_inv_0_3 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_or3_0_0 (
a,
b,
c,
y
);
input wire a;
input wire b;
input wire c;
output wire y;
xup_or3 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.c(c),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_or3_0_0 (
a,
b,
c,
y
);
input a;
input b;
input c;
output y;
wire a;
wire b;
wire c;
wire y;
design_lab_8_xup_or3_0_0_xup_or3 inst (
.a(a),
.b(b),
.c(c),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_or3_0_0_xup_or3 (
y,
a,
b,
c
);
output y;
input a;
input b;
input c;
wire a;
wire b;
wire c;
wire y;
LUT3 #(
.INIT(8'hFE)
) y__0 (
.I0(a),
.I1(b),
.I2(c),
.O (y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_or4_0_0 (
a,
b,
c,
d,
y
);
input wire a;
input wire b;
input wire c;
input wire d;
output wire y;
xup_or4 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.c(c),
.d(d),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_or4_0_0 (
a,
b,
c,
d,
y
);
input a;
input b;
input c;
input d;
output y;
wire a;
wire b;
wire c;
wire d;
wire y;
design_lab_8_xup_or4_0_0_xup_or4 inst (
.a(a),
.b(b),
.c(c),
.d(d),
.y(y)
);
endmodule
| 7.197647 |
module design_lab_8_xup_or4_0_0_xup_or4 (
y,
d,
a,
b,
c
);
output y;
input d;
input a;
input b;
input c;
wire a;
wire b;
wire c;
wire d;
wire y;
LUT4 #(
.INIT(16'hFFFE)
) y__0 (
.I0(d),
.I1(a),
.I2(b),
.I3(c),
.O (y)
);
endmodule
| 7.197647 |
module design_lecture5_2 (
A,
B,
S,
Y
);
input wire [1:0] A;
input wire [1:0] B;
input wire [0:0] S;
output wire [1:0] Y;
wire wireS;
wire wire1;
wire wire2;
wire wire3;
wire wire4;
assign #3 wire1 = A[0] & ~S;
assign #3 wire2 = B[0] & S;
assign #3 wire3 = A[1] & ~S;
assign ... | 7.274745 |
module_ref:clock_gen:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_main_clock_gen_0_0 (
clk
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_mai... | 7.311128 |
module_ref:counter_reg:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_main_counter_reg_0_0 (
clk,
a
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN d... | 7.39927 |
module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
parameter LEFT = 0, RIGHT = 1;
reg state, next_state;
always @(*) begin
case (state)
LEFT: next_state = (bump_left) ? RIGHT : LEFT;
RIGHT: ... | 7.203305 |
module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter LEFT = 0, RIGHT = 1, FALLING_LEFT = 2, FALLING_RIGHT = 3;
reg [1:0] state, next_state;
always @(*) begin
c... | 7.203305 |
module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT=0,RIGHT=1,FALLING_LEFT=2,FALLING_RIGHT=3,DIGGING_LEFT=4,DIGGING_RIGHT=5;
... | 7.203305 |
module counter (
input clk,
input reset,
input areset,
output signal
);
reg [5:0] count;
always @(posedge clk) begin
if (areset || (reset && count < 6'd19)) begin
count = 6'd0;
signal = 0;
end else if (~reset && count < 6'd19) begin
count++;
signal = 0... | 6.813256 |
module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT=0,RIGHT=1,FALLING_LEFT=2,FALLING_RIGHT=3,DIGGING_LEFT=4,DIGGING_RIGHT=5,SPLAT... | 7.203305 |
module design_tb(
);
reg [7:0] kaiguan; //k1-k8
reg rst,clk;//λаť
wire [6:0]seven_LED; //λ
wire [7:0]LED;
desgin1 test(kaiguan,rst,clk,seven_LED,LED);
always#20clk = ~clk;
initial
begin
clk = 0;rst = 0;
kaiguan = 8'b10101010;
end
endmodule
| 6.711856 |
module design_wrapper (
// Input to the design
input wire clock,
input wire reset
);
`TOP_MODULE core (
.clock(clock),
.reset(reset)
);
endmodule
| 8.184695 |
module deskew_state (
current_state,
next_state,
got_align,
disp_err,
aligned
);
input [2:0] current_state;
output [2:0] next_state;
input got_align;
input disp_err;
output aligned;
function [2:0] nstate;
input [2:0] cstate;
input got_align;
input align_error;
begin
... | 7.05356 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
// q <= d; qnot <= ~q;
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
// q <= d; qnot <= ~q;
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
// q <= d; qnot <= ~q;
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module deslocamentoEsq;
reg clk, d;
wire [3:0] q;
wire qnot;
dff DFF1 (
q[0],
qnot,
d,
clk
);
dff DFF2 (
q[1],
qnot,
q[0],
clk
);
dff DFF3 (
q[2],
qnot,
q[1],
clk
);
dff DFF4 (
q[3],
qnot,
q[2],
clk
);... | 6.534589 |
module deslocamento_2 (
entrada,
saida
);
// input
input [31:0] entrada;
// output
output [31:0] saida;
assign saida = entrada << 2;
endmodule
| 8.457406 |
module Desplazamiento_Derecha #(
parameter N = 8
) (
input [N-1:0] A,
output [N-1:0] Y
);
assign Y = A >> 1;
endmodule
| 8.730437 |
module Desplazamiento_Izquierda #(
parameter N = 8
) (
input [N-1:0] A,
output [N-1:0] Y
);
assign Y = A << 1;
endmodule
| 8.730437 |
module destination#(
parameter WIDTH = 8 ,
parameter DEPTH = 256
)
(
clk,
s_rst,
vaild,
data_in,
ready
);
localparam wt = $clog2(DEPTH);
input clk ;
input s_rst ;
input vaild ;
input [WIDTH-1:0] data_in ;
output reg ready ;
reg [WIDTH-1:0] mem [DEPTH-1:0] ;
reg [wt... | 7.868396 |
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