code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module to select the destination register to write into based on the type of instructions.
module destination_reg_selector(
input logic[4:0] read_reg_b, // register rt, instruction[20:16]
input logic[4:0] rtype_rd, // register rd, instruction[15:11]
input logic[1:0] rd_select, ... | 7.964075 |
module destination_v1#(
parameter WIDTH = 8 ,
parameter DEPTH = 256
)
(
clk,
s_rst,
idle,//contrl ready
vaild,
data_in,
ready
);
localparam wt = $clog2(DEPTH);
input clk ;
input s_rst ;
input vaild ;
input [WIDTH-1:0] data_in ;
output reg ready ;
input idle ;... | 7.852309 |
module destination_v3#(
parameter WIDTH = 8 ,
parameter DEPTH = 256
)
(
clk,
s_rst,
ready_in,//contrl ready
vaild,
data_in,
ready
);
localparam wt = $clog2(DEPTH);
input clk ;
input s_rst ;
input vaild ;
input [WIDTH-1:0] data_in ;
output ready ;
input ready_i... | 7.852309 |
module destroyAnimation (
input [9:0] HCounter,
input [9:0] VCounter,
input destroy,
input [32:0] dH,
input [32:0] dV,
input clk,
output reg dRed,
output reg dGreen
);
reg [32:0] hMax = 33'd40;
reg [32:0] vMax = 33'd40;
reg [32:0] one = 33'd8;
reg [32:0] two = 33'd16;
reg [32... | 6.629461 |
module dest_data_decode (instr, next_pc, alu_out, mem_out, rdata);
// Inputs
input [15:0] instr;
input [15:0] next_pc;
input [15:0] alu_out;
input [15:0] mem_out;
// Outputs
output reg [15:0] rdata;
// Wires
wire [6:0] op;
// assigns
assign op = {instr[15:11], instr[1:0]}... | 7.355887 |
module dest_domain #(
parameter DATAWIDTH = 8
) (
input CLK,
input RSTn,
input [DATAWIDTH - 1 : 0] src2dest_data,
input src2dest_load,
output reg dest_data_valid,
output reg [DATAWIDTH - 1 : 0... | 9.398259 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module dest_shift_reg (
alu_vgpr_dest_data,
alu_sgpr_dest_data,
alu_dest_vcc_value,
alu_dest_exec_value,
dest_buffer_wr_en,
dest_buffer_shift_en,
vgpr_dest_data,
sgpr_dest_data,
exec_wr_vcc_value,
vgpr_wr_mask,
clk,
rst
);
input [511:0] alu_vgpr_dest_data;
input [15:... | 8.401116 |
module p_sbox (
input [1:32] msg,
output [1:32] p_msg
);
assign p_msg[1] = msg[16];
assign p_msg[2] = msg[7];
assign p_msg[3] = msg[20];
assign p_msg[4] = msg[21];
assign p_msg[5] = msg[29];
assign p_msg[6] = msg[12];
assign p_msg[7] = msg[28];
assign p_msg[8] = msg[17];
assign p_msg[... | 6.76519 |
module f (
input [1:32] msg_r,
input [1:48] key,
output [1:32] f_out
);
wire [1:48] temp, emsg_r;
wire [1:32] temp_s_box;
wire [4:1] s_box1, s_box2, s_box3, s_box4, s_box5, s_box6, s_box7, s_box8;
wire [5:0] B1, B2, B3, B4, B5, B6, B7, B8;
e inst (
msg_r,
emsg_r
);
assign temp ... | 6.572024 |
module des_core (
input i_clk,
input i_rst,
input i_flag, //1-encrypt,0-decrypt
input [63:0] i_key,
input i_key_en, //1-key init start
output o_key_ok, //1-key init done
input [63:0] i_din,
input i_din_en,
output [63:0] o_dout,
... | 7.174898 |
module DES_CORE_DEC_VIP (
input [64:1] data,
key,
input clk,
output [64:1] enc_data
);
wire [32:1] data_l, data_r, data17_l, data17_r;
wire [56:1] key_wop;
stage1 ip_perm (
data,
key,
clk,
data_l,
data_r,
key_wop
);
stage2_dec proc (
data_l,
da... | 7.007269 |
module DES_CORE_ENC_IP (
input [64:1] data,
key,
input clk,
output [64:1] enc_data
);
wire [32:1] data_l, data_r, data17_l, data17_r;
wire [56:1] key_wop;
stage1 ip_perm (
data,
key,
clk,
data_l,
data_r,
key_wop
);
stage2_enc proc (
data_l,
dat... | 6.596745 |
module des_crypt_salt_test;
// Inputs
reg [63:0] Din;
reg [63:0] K;
reg [11:0] salt;
reg CLK;
// Outputs
wire [67:0] Kout;
wire [31:0] L_out;
wire [31:0] R_out;
// Instantiate the Unit Under Test (UUT)
descrypt_salt uut (
.Din(Din),
.K(K),
.salt(salt),
.Kout(Kout),
... | 6.521998 |
module performs the DES function.
module DES_Function(
input [31:0] i_data,
input [47:0] i_key,
output [31:0] o_data
);
wire [47:0] w_expanded_data;
wire [47:0] w_xored_data;
wire [31:0] w_sboxes_reduced_data;
Expansion_D_Box Expansion_D_Box_inst
(
.i_data(i_data) , // input [31:0] i_data_sig
... | 7.634754 |
module des_loop (
input [63:0] Ti_in,
input [47:0] Ki,
input [`SALT_MSB:0] salt_in,
output [63:0] Ti_out
);
wire [31:0] Li = Ti_in[63:32];
wire [31:0] Ri = Ti_in[31:0];
// E,xor,S,P
wire [47:0] E_result;
Eblock Eblock_instance (
salt_in,
Ri,
E_result
);
wire [47:0] xor... | 8.375453 |
module des_round (
input [1:32] Rin, // 32-bit right-half input
input [1:32] Lin, // 32-bit left-half input
input [1:48] K, // 48-bit round key
output [1:32] Rout, // 32-bit right-half output
output [1:32] Lout // 32-bit left-half output
);
wire [1:32] P; // 32-bit output of round function
... | 8.667226 |
module is designed to perform the round function for DES. The
* indexing has been adjusted to match the values in the respective
* tables (https://en.wikipedia.org/wiki/DES_supplementary_material).
*/
module des_round_function
(
input [1:32] R, // 32-bit right-half input
input [1:48] K, /... | 7.739429 |
module des_s_box (
input wire [1:6] address,
output wire [1:4] sout
);
parameter width = 4;
parameter widthad = 6;
parameter datafile = "none";
reg [width-1:0] mem[(2**widthad)-1:0];
reg [6:0] n;
/*
CAUTION $readmemh 部分综合工具可能无法综合!
*/
initial begin
$readmemh(datafile, mem);
$display("... | 7.451955 |
module: Des_Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DES_test1;
// Inputs
reg CLK;
reg RST;
reg CHIP_SELECT_BAR;
reg [64:1] PLAIN_TEXT;
reg [64:1] KEY;
// Outputs... | 7.414341 |
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
wire [7:0] pre;
always @(posedge clk) begin
pedge <= (~pre & in);
pre <= in;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
wire [7:0] pre;
always @(posedge clk) begin
anyedge <= pre ^ in;
pre <= in;
end
endmodule
| 7.203305 |
module Detect111_tb ();
reg X, clk, rst;
wire out;
wire [11 : 0] in;
integer i;
assign in = 12'b1001_0111_0110;
always #5 clk = ~clk;
initial begin
clk = 0;
rst = 1;
@(posedge clk);
rst = 0;
for (i = 0; i < 12; i = i + 1) begin
@(posedge clk);
... | 6.578479 |
module DetectHign2Low (
input clk,
input reset,
input signal,
output high2LowSignal
);
reg high2LowReg_1 = 1'b0;
reg high2LowReg_2 = 1'b0;
always @(posedge clk or negedge reset)
if (!reset) begin
high2LowReg_1 <= 1'b0;
high2LowReg_2 <= 1'b0;
end else begin
high2LowReg... | 7.246776 |
module DetectHign2Low_tb;
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg reset;
initial begin
reset = 1'b1;
#100 reset = 1'b0;
#180 reset = 1'b1;
// #20 $finish;
end
reg signal;
initial begin
signal = 1'b0;
#1000 signal = 1'b1;
#180 signal = 1'b0;
#100 signal ... | 7.246776 |
module detection_17x17 (
//Input
input iClk,
input iReset_n,
input iReady_HFG,
input iRun_HFG,
input iRun_ANN,
input [12:0] iAddr_OM,
input [83:0] i4Rec0,
input [83:0] i4Rec1,
input [83:0] i4Rec2,
input [83:0] i4Rec3,
input [8... | 7.299862 |
module detection_19x19 (
//Input
input iClk,
input iReset_n,
input iReady_HFG,
input iRun_HFG,
input iRun_ANN,
input [12:0] iAddr_OM,
input [83:0] i4Rec0,
input [83:0] i4Rec1,
input [83:0] i4Rec2,
input [83:0] i4Rec3,
input [8... | 7.014745 |
module detection_23x23 (
//Input
input iClk,
input iReset_n,
input iReady_HFG,
input iRun_HFG,
input iRun_ANN,
input [12:0] iAddr_OM,
input [83:0] i4Rec0,
input [83:0] i4Rec1,
input [83:0] i4Rec2,
input [83:0] i4Rec3,
input [8... | 7.065988 |
module Det_Des #(
parameter DATA_WIDTH = 8,
parameter COL = 640,
parameter ROW = 480,
parameter DATA_WIDTH_4WORDS = 32
) (
input wire [DATA_WIDTH - 1:0] din,
input wire din_valid,
input wire clk,
input wire rst,
input wire [DATA_WIDTH_4WORDS - 1:0] constant,
output wire dout_v... | 6.882503 |
module DetectLow2High (
input clk,
input reset,
input signal,
output low2HighSignal
);
reg low2HighReg_1 = 1'b1;
reg low2HighReg_2 = 1'b1;
always @(posedge clk or negedge reset)
if (!reset) begin
low2HighReg_1 <= 1'b1;
low2HighReg_2 <= 1'b1;
end else begin
low2HighReg... | 6.531231 |
module DetectLow2High_tb;
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg reset;
initial begin
reset = 1'b1;
#100 reset = 1'b0;
#180 reset = 1'b1;
// #20 $finish;
end
reg signal;
initial begin
signal = 1'b1;
#1000 signal = 1'b0;
#180 signal = 1'b1;
#100 signal ... | 6.531231 |
module detector10010_PRE (
input clk,
rst,
J,
output w
);
reg [2:0] ns, ps;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100, F = 3'b101;
always @(ps, J) begin
ns = A;
case (ps)
A: ns = J ? B : A;
B: ns = J ? B : C;
C: ns = J ? B : D;
D: n... | 7.365801 |
module detector10010mealy_PRE (
input clk,
rst,
J,
output w
);
reg [2:0] ns, ps;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b100, E = 3'b011;
always @(ps, J) begin
ns = A;
case (ps)
A: ns = J ? B : A;
B: ns = J ? B : C;
C: ns = J ? B : D;
D: ns = J ?... | 7.365801 |
module detector_delay (
clk,
rst_n,
datain,
dataout
);
parameter DATA_WIDTH = 16;
parameter DELAY_CYCLE = 2;
input clk, rst_n;
input [DATA_WIDTH-1:0] datain;
output [DATA_WIDTH-1:0] dataout;
reg [DATA_WIDTH-1:0] data_reg[DELAY_CYCLE-1:0];
assign dataout = data_reg[DELAY_CYCLE-1];
al... | 7.091047 |
module DETECTOR_RIESGOS ( //INPUTS
input i_reset,
input [4:0] i_rs,
input [4:0] i_rt,
input [4:0] i_id_ex_rt,
input [2:0] i_id_ex_mem,
//OUTPUTS
output o_pc_write,
output o_if_id_write,
output o_mux_zero
);
reg pc_write;
reg if_id_write;
reg mux_z... | 6.561784 |
module detector_secuencia (
input clk,
input reset,
input in,
input tick,
output [2:0] current_state,
output reg out
);
/* Estados del detector */
localparam S0 = 'b000;
localparam S1 = 'b001;
localparam S2 = 'b010;
localparam S3 = 'b011;
localparam S4 = 'b100;
reg [2:0] state, s... | 6.6587 |
module detector_sim ();
reg clk_sim;
reg rst_sim;
reg b_sim;
wire w_sim;
detector a1 (
clk_sim,
rst_sim,
b_sim,
w_sim
);
always begin
clk_sim <= 0;
#10;
clk_sim <= 1;
#10;
end
initial begin
// Reset at first
rst_sim <= 1;
b_sim <= 0;
/... | 6.937132 |
module detector (
clk,
rst,
b,
w
);
input clk;
input rst;
input b;
output w;
wire \FSM_sequential_state[0]_i_1_n_0 ;
wire \FSM_sequential_state[1]_i_1_n_0 ;
wire b;
wire b_IBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire rst;
wire rst_IBUF;
(* RTL_KEEP = "yes" *) wire... | 6.593279 |
module detector_tb ();
reg clk;
reg w;
wire z;
wire [2:0] stage_no;
detector ollo_detector (
w,
clk,
z,
stage_no
);
always begin
clk = 0;
#2.5
clk = 1;
#2.5
clk = 0;
#2.5
clk = 1;
#2.5
clk = 0;
forever #50 clk = ~clk;
end
initial begin
... | 6.526219 |
module detects whether the given number in ieee format is
* a zero
*
*/
module detector_zero(m, e, z);
parameter WIDTH_M = 23;
parameter WIDTH_E = 8;
input [WIDTH_M-1:0] m;
input [WIDTH_E-1:0] e;
output z;
// If m=0 and e=0 then the value is zero
assign z = (m == 0 && e == ... | 8.320447 |
module detectPatternOut (
SW,
KEY,
LEDR
);
input [9:0] SW;
input [3:0] KEY;
output [9:0] LEDR;
wire w, clock, reset_b;
reg [3:0] y_Q, Y_D; // y_Q represents current state, Y_D represents next state
wire out_light;
parameter A = 4'b0000, B = 4'b0001, C = 4'b0010, D = 4'b0011, E = 4'b0100, F = ... | 7.821973 |
module DetectWinner (
input [8:0] ain,
bin,
output [7:0] win_line
);
// CPEN 211 LAB 3, PART 1: your implementation goes here
wire [7:0] winner_a; //a will be the winner, and 7 means 3 rows + 3 columns + 2 diagonal
wire [7:0] winner_b; //b will be the winner, and 7 means 3 rows + 3 columns + 2 diag... | 6.840294 |
module detectwin_tb;
reg [8:0] ain, bin;
wire [7:0] win_line;
DetectWinner DUT (
ain,
bin,
win_line
);
initial begin
ain = 9'b000_000_000;
bin = 9'b000_000_000; //initialized
//a wins
ain = 9'b111_000_000; //test when the first row are all occupied by a
bin = 9'b000_... | 6.970118 |
module detect_3inarow (
input [1:0] pos0,
pos1,
pos2,
output wire winner,
output wire [1:0] who_win
);
wire [1:0] temp1, temp2, temp3;
wire temp4;
assign temp1[1] = !(pos0[1] ^ pos1[1]);
assign temp1[0] = !(pos0[0] ^ pos1[0]);
assign temp2[1] = !(pos2[1] ^ pos1[1]);
assign temp2[0] = !... | 6.750409 |
module detect_CMD_V4 (
cs,
byteFromEth,
data,
dNumber
);
input cs;
input [15:0] byteFromEth;
output reg [15:0] data;
output reg [7:0] dNumber = 0; // number of incoming byte
reg [7:0] f_CM = 0;
always @(posedge cs) begin // at the end of transmition o? SPI data begin:
if (byteFromE... | 6.872394 |
module is detecting collison ship with enemy missile and turn him off
`timescale 1 ns / 1 ps
module detect_collision (
input wire pclk, // Peripheral Clock
input wire rst, // Synchrous reset
input wire [10:0] ship_X,
input wire [10:0] enBulle... | 7.261362 |
module detect_falling_edge (
input wire clk,
input wire rst_n,
input wire signal,
output reg out
);
reg signal_delayed;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
signal_delayed <= 0;
out <= 0;
end else begin
signal_delayed <= signal;
out <= ~signa... | 8.186932 |
module detect_errors2 #(
parameter whereis_aux = 0
) (
input wire clk,
input wire rst,
input wire [15:0] segment_number_max,
(* mark_debug = "true" *) input wire [15:0] seg,
(* mark_debug = "true" *) input wire rx_en,
(* mark_debug = "true" *) input wire [7:0] rx_data,
(* mark_debug = "t... | 7.29241 |
module DETECT_LOWEST_HIGH (
// INPUTS
Din, // 128bits
// OUTPUTS
Dout // 8 bits, MSB = 1 =>none of 1
);
input [127:0] Din;
output [7:0] Dout;
reg [7:0] Dout;
integer i;
always @(*) begin
Dout = 8'b1000_0000;
for (i = 127; i >= 0; i = i - 1)
if (Din[i] == 1'b1) Dout = i;... | 6.556392 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module detect_module(
CLK,
RST_n,
Rx_Pin_In,
... | 7.088073 |
module DETECT_tb;
// INPUTS
reg [127:0] Din; // posedge active
// OUTPUTS
wire [ 7:0] Dout; // 8 bits
DETECT_LOWEST_HIGH DETECT_LOWEST_HIGH_inst (
.Din (Din),
.Dout(Dout)
);
initial begin
#(`Clock * 1);
Din = 128'd1213213; // 100101000001100011101 Dout = 0
#(`Cl... | 6.535544 |
module detect_win (
input [1:0] pos1,
pos2,
pos3,
pos4,
pos5,
pos6,
pos7,
pos8,
pos9,
output wire winner,
output wire [1:0] who_win
);
wire win1, win2, win3, win4, win5, win6, win7, win8;
wire [1:0] who1, who2, who3, who4, who5, who6, who7, who8;
detect_3inarow w1 (
... | 6.783706 |
module is detecting colision enemy with ship missile and turns off enemy
// drawing when he die
module detec_col
#( parameter
N = 1 // number of enemy
)(
input wire pclk,
input wire rst,
input wire [10:0] xpos_missile_1,
input wire [10:0] ypos_missile_1,
input wire [10:0] xpos_mi... | 7.261362 |
module determinador_vuelto (
input [13:0] monto_ingresado,
input [13:0] costo,
output reg [13:0] vuelto
);
always @(*) begin
if (costo > monto_ingresado) vuelto = 0;
else vuelto = monto_ingresado - costo;
end
endmodule
| 7.110989 |
module DetermineSuccessiveClapsAmount #(
parameter integer SUC_CLAPS_WIDTH = 16,
parameter integer N_D = 16,
parameter integer N_CLAP = 16
) (
input wire clock,
input wire nreset,
input wire clap_valid,
output reg clap_ready = 0,
input wire energy_valid,
input wire energy_ready,
... | 7.580162 |
module Detetor (
din,
clk,
dout
);
input din, clk;
output wire dout;
reg [3:0] qtemp;
always @(posedge clk) begin
qtemp <= {din, qtemp[3:1]};
//if (qtemp == 4'b1101) dout=1;
//else dout=0;
end
assign dout = (qtemp == 4'b1101) ? 1 : 0;
endmodule
| 6.625734 |
module DEtoALU_REG (
input clk,
input rstn,
// PC及指令
input [31:0] i_DecodePC_32,
input [31:0] i_Inst_32,
input [31:0] i_PCPlus4_32,
output [31:0] o_ALUPC_32,
output [31:0] o_PCPlus4_32,
output [31:0] o_Inst_32,
// ALU使用
input [11:0] i_ALUControl_12,
input [31:0] i_AL... | 8.038954 |
module: seq_detector
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module det_tb;
// Inputs
reg sequence;
reg clk;
reg resetn;
// Outputs
wire out;
// Instantiate the Unit Under... | 7.831128 |
module switch (
inp,
out
);
supply0 gnd;
supply1 vdd;
input inp;
output out;
wire con;
// Not-gate.
pmos (con, vdd, inp);
nmos (con, gnd, inp);
// Not-gate.
pmos (out, vdd, con);
nmos (out, gnd, con);
endmodule
| 6.864438 |
module led_interface (
input clk,
rst,
wr,
rd,
input [7:0] din,
output reg [7:0] dout,
output [7:0] led
);
reg [7:0] led_data;
assign led = led_data;
always @(posedge clk)
if (rst) led_data = 0;
else if (wr) led_data = din;
always @(posedge clk)
if (rd) dout = led_data;... | 6.680295 |
module key_interface (
input clk,
rst,
rd,
input [3:0] key,
output reg [7:0] dout
);
reg [3:0] key_r;
always @(posedge clk) key_r = key;
wire [3:0] w_key;
always @(posedge clk) begin
dout[7:4] = 0;
if (rd) dout[3:0] = w_key;
else dout[3:0] = 0;
end
`define KEY_FSM
`ifdef KE... | 6.977585 |
module second_gen (
input clk,
rst,
input rd,
input [7:0] din,
input wr,
output reg [7:0] dout
);
reg [31:0] cntr;
wire time_out = cntr == (`CLK_HZ - 1);
wire clr = wr & (din[0] == 0);
always @(posedge clk)
if (rst) cntr = 0;
else if (time_out) cntr = 0;
else cntr = cntr + ... | 6.729728 |
module key_fsm (
input clk,
rst,
input key_i,
output reg key_o,
input rd
);
reg [3:0] curr_state, next_state;
reg [31:0] cntr;
always @(posedge clk)
if (rst) cntr = 0;
else if (curr_state == 1) cntr = cntr + 1;
else cntr = 0;
always @(posedge clk)
if (rst) curr_state = 0;
... | 8.00823 |
module in order to set the
* number of items in the ROM
* defparam DRT_NUM_OF_DEVICES = 2;
*/
`include "project_defines.v"
//`define DRT_NUM_OF_DEVICES 1
`define DRT_SIZE_OF_HEADER 8
`define DRT_SIZE_OF_DEV 8
module device_rom_table (
clk,
rst,
wbs_we_i,
wbs_cyc_i,
wbs_sel_i,
wbs_dat_i,
wbs_stb_i,
wbs... | 6.823916 |
module device_sim ( /*AUTOARG*/
// Outputs
TXN_OUT0,
TXP_OUT0,
// Inputs
RXN_IN0,
RXP_IN0
);
localparam real SATA_DEVICE_PER = 1000.0 / 300; // 300Mhz
localparam real GTP_CLK_REF = 1000.0 / 150; // 150Mhz
output TXN_OUT0;
output TXP_OUT0;
input RXN_IN0;
input RXP_IN0;
reg sa... | 6.741852 |
module Device (
force_req,
req,
gnt,
selDev,
addr_data,
AddressToContact,
cmd,
test_cmd,
Frame,
TRDY,
IRDY,
clk,
slotSel,
dataToWrite
);
//========================= pins declaration=========================
/*
//Test Pins---------------------------------------... | 7.433782 |
module devider (
input clk,
input rst,
input [31:0] dev,
output reg out
);
reg [31:0] count = 0;
always @(posedge clk, posedge rst)
// при загрузке отнимать 1
if (rst)
count <= dev - 1;
else begin
count <= count - 1;
if (count == 0) begin
count <= dev - 1;
... | 6.810843 |
module dev_clk_counter (
output [31:0] dev_out,
input [31:0] dev_in,
input [7:0] dev_addr,
input we,
clk,
rst
);
reg [31:0] counter0;
reg [31:0] counter1;
always @(posedge clk or posedge rst)
if (rst) begin
counter0 <= 32'b0;
counter1 <= 32'b0;
end else begin
cou... | 6.922851 |
module dev_debug_input (
output [31:0] dev_out,
input [31:0] dev_in,
input [7:0] dev_addr,
input we,
clk,
rst
);
reg [31:0] val; // will be accessed by testbench
always @(posedge rst) if (rst) val <= 32'b0;
assign dev_out = dev_addr == 8'h00 ? val : 32'h_dead_beef;
endmodule
| 7.956416 |
module dev_gpio8 (
input wire clk,
input wire reset,
// External IO
input wire [NUM_IO-1:0] io_in,
output wire [NUM_IO-1:0] io_out,
output wire [NUM_IO-1:0] io_oeb,
// Filtered signals
output wire [NUM_IO-1:0] io_in_sync,
output wire [NUM_IO-1:0] io_in_rise,
output wire [NUM_I... | 7.201303 |
module DEV_I2C_CONFIG (
input iCLK,
input iRST_N,
output I2C_SCLK,
inout I2C_SDAT,
output reg I2C_DONE
);
// LUT for Configuration Data Number
parameter LUT_SIZE = 10;
// Clock Setting
parameter CLK_Freq = 50_000000; //50 MHz
parameter I2C_Freq = 10_000; //10 KHz
reg [1... | 8.550843 |
module dev_printReg (
output [31:0] dev_out,
input [31:0] dev_in,
input [7:0] dev_addr,
input we,
clk,
rst
);
always @(posedge clk)
if (we)
$display("[%0t] [dev_printReg] addr 0x%2X recv value: 0x%8X", $time, dev_addr, dev_in);
endmodule
| 6.724772 |
module dev_uart (
input wire clk,
input wire reset,
// Serial wires
input wire rx,
output wire tx,
// Memory bus
input wire stb,
output wire ack,
input wire we,
input wire [1:0] addr,
input wire [31:0] dtw,
output reg [31:0] dtr,
// Interrupts
output wire irq
... | 7.444902 |
module DEXT (
input [31:0] instr,
input [1:0] offset,
input [31:0] DMD,
output reg [31:0] newDMD
);
always @(*) begin : DEXT_CL
if (`isLw) newDMD = DMD;
else if (`isLh) begin
if (offset[1]) newDMD = {{16{DMD[31]}}, DMD[31:16]};
else newDMD = {{16{DMD[15]}}, DMD[15:0]};
end els... | 7.465303 |
module: de_acelp_pipe
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module de_acelp_tb;
`include "paramList.v"
// Inputs
reg clk;
reg start;
reg reset;
reg mem_Mux1Sel;
reg mem_M... | 6.554249 |
module de_audio_codec (
clk,
reset_n,
sample_end,
audio_output,
audio_input,
channel_sel,
AUD_ADCLRCK,
AUD_ADCDAT,
AUD_DACLRCK,
AUD_DACDAT,
AUD_BCLK
);
input clk;
input reset_n;
output [1:0] sample_end;
input [15:0] audio_output;
output reg [15:0] audio_input;
/... | 7.822431 |
module de_canonicalize(
//# {{data|Instruction Data}}
input[63:0] instIn,
output[63:0] instOut
);
`include "de_isa_def.vh"
reg[63:0] instOut_pre;
assign instOut = instOut_pre;
//Expands input instruction into full 64-bit format
always @(*)
begin
instOut_pre = 64'h0;
... | 7.456827 |
module DE_flipflop (
input wire clk,
input wire [31:0] RD1,
input wire [31:0] RD2,
input wire [31:0] SignImmD,
input wire [ 4:0] RsD,
input wire [ 4:0] RtD,
input wire [ 4:0] RdD,
input wire RegWriteD,
input wire MemtoRegD,
input wire MemWriteD,
in... | 6.742188 |
module de_i2c_controller (
CLOCK,
I2C_SCLK, // I2C CLOCK
I2C_SDAT, // I2C DATA
I2C_DATA, // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
GO, // GO transfor
END, // END transfor
W_R, // W_R
ACK, // ACK
RESET,
// TEST
SD_COUNTER,
SDO
);
input CLOCK;
input [23:0] I2C_DATA;
... | 6.503336 |
module de_nrzi (
clk,
rst,
DP_in,
DM_in,
data_out
);
input clk, rst, DP_in, DM_in;
output data_out;
reg de_dp, de_dm /*, data_out*/, out;
//wire dm, dp;
wire data_out;
//wire a, b, c;
/*
assign data_out = (!rst) ? 1'bz : (de_dp | de_dm);
assign dp = ~(de_dp ^ DP_in);
assign dm = ~(de... | 7.325508 |
module DE_with_display (
input wire [5:0] n,
input wire start,
clk,
reset,
//output wire done_tick_signal,
output wire [3:0] an,
output wire [7:0] sseg
);
//internal signals
wire [12:0] DE_data_out;
wire DE_done_tick;
wire HD_hold_clk;
Difference_Engine DE (
.n(n), //inpu... | 7.087104 |
module DF (
input wire clk,
input wire rst,
input wire [`StallBus-1:0] stall,
input wire [`EX_TO_DF_WD-1:0] ex_to_df_bus,
output wire [`DF_TO_DC_WD-1:0] df_to_dc_bus,
output wire [`DF_TO_RF_WD-1:0] df_to_rf_bus,
output wire data_sram_en,
output wire [3:0] data_sram_wen,
output wi... | 7.317096 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module of the digital front end. Contains PDM clock generation,
// PDM sampling, and PDM filtering. Produces a 8b 16kHz audio stream which is
// sent to ACO.
// =============================================================================
module dfe #(
// ===========================================================... | 8.182828 |
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset) begin
if (areset == 1'b1) q <= 8'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk) begin
if (resetn == 1'b0) begin
q <= {byteena[1] == 1'b1 ? 8'b0 : q[15:8], byteena[0] == 1'b1 ? 8'b0 : q[7:0]};
end else begin
q <= {byteena[1] == 1'b1 ? ... | 7.203305 |
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