code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
if (reset == 1'b0) begin
q <= d;
end else begin
q <= 8'h34;
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
if (reset == 1'b1) begin
q <= {8{1'b0}};
end else begin
q <= d;
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input in,
output out
);
always @(posedge clk) out <= in ^ out;
endmodule
| 7.203305 |
module testDFF ();
reg clk;
reg enable;
reg [31:0] d;
wire [31:0] q;
dff #(32) dut (
.clk(clk),
.enable(enable),
.d(d),
.q(q)
);
// Generate clock (50MHz)
initial clk = 0;
always #10 clk = !clk; // 50MHz Clock
initial begin
$display("---------------------------------... | 6.735756 |
module d_ff (
clk,
reset,
d,
q,
qb
);
// Step1 : Declare Port Directions
input clk, reset, d;
output reg q;
output qb;
// Step2 : Write the behavioral logic for D flip-flop functionality.
always @(posedge clk) begin
if (reset) q = 0;
else q = d;
end
//Step3. Assign compl... | 6.915651 |
module dff1 (
input d,
input clk,
input reset,
output q,
output qb
);
reg q;
assign qb = ~q;
always @(posedge clk or negedge reset)
if (~reset) q <= 1'b0; // Active low-reset
else q <= d;
endmodule
| 6.947416 |
module dff1 (
d,
clk,
clrn,
q
);
input d, clk, clrn;
output reg q;
always @(negedge clrn or posedge clk)
if (clrn == 0) begin
q <= 0;
end else begin
q <= d;
end
endmodule
| 6.900497 |
module dff12bit (
clk,
rst,
d,
q
);
input clk;
input rst;
input [11:0] d;
output reg [11:0] q;
always @(posedge clk) begin
if (rst == 1) begin
q <= 0;
end else begin
q <= d;
end
end
endmodule
| 6.674006 |
module dff16 (
reset_n,
clk,
d_in,
q_out
);
input reset_n, clk;
input [15:0] d_in;
output reg [15:0] q_out;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) q_out <= 16'h0;
else q_out <= d_in;
end
endmodule
| 7.426239 |
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk) begin
if (!resetn) q[15:0] <= 8'h0;
else begin
if (byteena[0]) q[7:0] <= d[7:0];
else q[7:0] <= q[7:0];
if (byteena[1]) q[15:8] <= d[15:8];
e... | 7.203305 |
module top_module (
input clk,
input d,
input r, // synchronous reset
output q
);
always @(posedge clk)
if (r) q <= 0;
else q <= d;
endmodule
| 7.203305 |
module dff (
(* PAD="14"*)
output wire q1, (* PAD="15"*)
output wire q2, (* PAD="16"*)
output wire q3, (* PAD="17"*)
output wire q4, (* PAD="3"*)
input wire d, (* PAD="1"*)
input wire clk, (* PAD="2"*)
input wire rstin, (* PAD="4"*)
input wire ce, (* PAD="5"*)
input wire oe
... | 7.035162 |
module dff3 (
input d,
input clk,
input reset,
output q,
output qb
);
reg q;
assign qb = ~q;
always @(posedge clk) q <= d;
endmodule
| 6.688989 |
module dff32 (
d,
clk,
clrn,
q
);
input [31:0] d;
input clk, clrn;
output reg [31:0] q;
always @(negedge clrn or posedge clk)
if (clrn == 0) begin
// q <= 0;
q <= -4;
end else begin
q <= d;
end
endmodule
| 7.788889 |
module dff36 (
d,
clk,
reset,
q
);
input [35:0] d;
input clk, reset;
output [35:0] q;
genvar i;
generate
for (i = 0; i < 36; i = i + 1)
dff d1 (
d[i],
clk,
reset,
q[i]
);
endgenerate
endmodule
| 7.044595 |
module dff3bit (
clk,
rst,
d,
q
);
input clk;
input rst;
input [2:0] d;
output reg [2:0] q;
always @(posedge clk) begin
if (rst == 1) begin
q <= 0;
end else begin
q <= d;
end
end
endmodule
| 6.521732 |
module dff4 (
input d,
input clk,
input reset,
output q,
output qb
);
reg q;
assign qb = ~q;
always @(posedge clk or posedge reset)
if (reset) q <= 1'b1; // Active high-reset
else q <= d;
endmodule
| 6.501592 |
module dff4 (
d,
clk,
clrn,
q
);
input [3:0] d;
input clk, clrn;
output reg [3:0] q;
always @(negedge clrn or posedge clk)
if (clrn == 0) begin
q <= 0;
end else begin
q <= d;
end
endmodule
| 6.980897 |
module dff5 (
input d,
input clk,
input reset,
output q,
output qb
);
reg q;
assign qb = ~q;
always @(posedge clk or posedge reset)
if (reset) q <= 1'b0; // Active low-reset
else q <= d;
endmodule
| 7.038231 |
module dff5 (
d,
clk,
clrn,
q
);
input [4:0] d;
input clk, clrn;
output reg [4:0] q;
always @(negedge clrn or posedge clk)
if (clrn == 0) begin
q <= 0;
end else begin
q <= d;
end
endmodule
| 7.055581 |
module dff5bit (
clk,
rst,
d,
q
);
input clk;
input rst;
input [4:0] d;
output reg [4:0] q;
always @(posedge clk) begin
if (rst == 1) begin
q <= 0;
end else begin
q <= d;
end
end
endmodule
| 6.527285 |
module dff6 (
input d,
input clk,
input reset,
output q,
output qb
);
reg q;
assign qb = ~q;
always @(posedge clk)
if (~reset) q <= 1'b0; // Active low-reset
else q <= d;
endmodule
| 6.830418 |
module dff63_0 (
d,
clk,
q
);
input [63:0] d;
input clk;
output [63:0] q;
reg [63:0] q;
always @(posedge clk) begin
q <= d;
end
endmodule
| 6.911639 |
module dff7 (
input d,
input clk,
input reset,
output q,
output qb
);
reg q;
assign qb = ~q;
always @(posedge clk)
if (reset) q <= 1'b0; // Active low-reset
else q <= d;
endmodule
| 7.354238 |
module dff8 (
input d,
input clk,
input reset,
output q,
output qb
);
reg q;
assign qb = ~q;
always @(posedge clk)
if (reset) q <= 1'b1; // Active high-reset
else q <= d;
endmodule
| 6.580801 |
module dff8 (
Din,
Q,
clk,
rst
);
input signed [7:0] Din;
input clk, rst;
output reg signed [7:0] Q;
always @(posedge clk or posedge rst) begin
if (rst) Q <= 0;
else Q <= Din;
end
endmodule
| 6.91952 |
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q[7:0] <= 8'h0;
else q[7:0] <= d[7:0];
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
if (reset) q[7:0] <= 8'h34;
else q[7:0] <= d[7:0];
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
if (reset) q[7:0] <= 8'b0;
else q[7:0] <= d[7:0];
end
endmodule
| 7.203305 |
module dff9 (
input d,
input clk,
input reset,
output q,
output qb
);
reg q;
assign qb = ~q;
always @(posedge clk)
if (~reset) q <= 1'b1; // Active high-reset
else q <= d;
endmodule
| 6.684589 |
module dffa (
q,
d,
clk,
resetb,
setb
);
output q;
input d, clk, resetb, setb;
reg q;
// Note that this synthesizes correctly but can simulate incorrectly
// assert reset -> assert set -> remove reset doesn't switch gate to 1
always @(posedge clk or negedge resetb or negedge setb) begin... | 6.770958 |
module dffar #(
parameter WIDTH = 1
) (
input clk,
input r,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk or negedge r)
if (~r) q <= {WIDTH{1'b0}};
else q <= d;
endmodule
| 8.045534 |
module dffare #(
parameter WIDTH = 1
) (
input clk,
input r,
input en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk or negedge r)
if (~r) q <= {WIDTH{1'b0}};
else if (en) q <= d;
else q <= q;
endmodule
| 8.0462 |
module dffarre #(
parameter WIDTH = 1
) (
input clk,
input ar,
input r,
input en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk or negedge ar)
if (~ar) q <= {WIDTH{1'b0}};
else if (r) q <= {WIDTH{1'b0}};
else if (en) q <= d;
else q <= q;
endmodule
... | 8.389012 |
module dffa_rstn (
clk,
rst_n,
din,
dout
);
//------------------------------------------------------------------------------
//Parameters
parameter DW = 1'b1;
parameter RST_VL = {DW{1'b0}};
//------------------------------------------------------------------------------
// Port declarations... | 8.521496 |
module dff (
input D,
input clk,
input rst,
output Q
);
always @(posedge (clk), posedge (rst)) begin
if (rst == 1) Q <= 1'b0;
else Q <= D;
end
endmodule
| 7.174483 |
module DFFC #(
parameter INIT = 1'b0
) (
input CLEAR,
input CLK,
input D,
output Q
);
reg _r_Q;
initial begin
_r_Q = INIT;
end
always @(posedge CLEAR or posedge CLK) begin
if (CLEAR) begin
_r_Q <= 1'b0;
end else begin
_r_Q <= D;
end
end
assign Q = _r_Q... | 6.622952 |
module dffc_dc (
clk,
dclk,
rst,
c_en,
d_en,
din,
q_ready,
q
);
parameter SIZE = 1;
input clk; //System clock: Regular clock that all the shadow capture system operates on
input dclk; //Data clock: Clock that host dffs run on, may or may not be different from system clock
i... | 6.682966 |
module dffe32 (
d,
clk,
clrn,
e,
q
);
input [31:0] d;
input clk, clrn, e;
output reg [31:0] q;
always @(negedge clrn or posedge clk)
if (clrn == 0) begin
q <= 0;
end else begin
if (e == 1) q <= d;
end
endmodule
| 7.390597 |
module dffe32pc (
d,
clk,
clrn,
e,
q
);
input [31:0] d;
input clk, clrn, e;
output reg [31:0] q;
always @(negedge clrn or posedge clk)
if (clrn == 0) begin
q <= -4; // Make sure instruction at address 0 will be properly executed.
end else begin
if (e == 1) q <= d;
e... | 7.779823 |
module dffe32_pc (
d,
clk,
clrn,
e,
q
);
input [31:0] d;
input clk, clrn, e;
output [31:0] q;
reg [31:0] q;
initial begin
q = 0;
end
always @(negedge clrn or posedge clk)
if (clrn == 0) begin
q <= 0;
end else begin
if (e == 1) q <= d;
end
endmodule
| 7.032493 |
module dffs (d, clk, clrn, prn, sclr, sdata, sload, q );
// input d,clk,clrn,prn, sclr, sdata, sload;
// output q;
// wire q;
// tri0 aload;
// tri1 prn, clrn;
// PRIM_GDFF (q,d,clk,1'b1,!clrn,!prn,1'b0,sdata,sclr,sload);
//endmodule
| 6.699453 |
module dffea (
d,
clk,
ena,
clrn,
prn,
aload,
adata,
q
);
input d, clk, ena, clrn, prn, aload, adata;
output q;
wire q;
tri0 aload;
tri1 prn, clrn, ena;
reg stalled_adata;
initial begin
stalled_adata = adata;
end
always @(adata) begin
#1 stalled_adata = adata;... | 6.622625 |
module dffen_2seg (
input wire clk,
reset,
input wire en,
input wire d,
output reg q
);
// s i g n a l d e c l a r a t i o n
reg data, nextdata;
// body
// D FF
always @(posedge clk, posedge reset)
if (reset) data <= 1'b0;
else data <= nextdata;
always @*
if (en) nextdat... | 7.016038 |
module main (
input I0,
input CE,
input RESET,
output D0,
input CLKIN
);
wire inst0_Q;
SB_DFFESR inst0 (
.C(CLKIN),
.R(RESET),
.E(CE),
.D(I0),
.Q(inst0_Q)
);
assign D0 = inst0_Q;
endmodule
| 7.081372 |
module main (
input I0,
input CE,
input SET,
output D0,
input CLKIN
);
wire inst0_Q;
SB_DFFESS inst0 (
.C(CLKIN),
.S(SET),
.E(CE),
.D(I0),
.Q(inst0_Q)
);
assign D0 = inst0_Q;
endmodule
| 7.081372 |
module dffe_nbit_t #(
parameter
W=6, // register width
PU=6'b0 // "power-up" (reset) value
) (
input wire rstb, // asynchronous reset*
input wire clk, // clock
input wire ena, // enable (as in standard DFFE)
input wire [W-1:0] d, // input dat... | 6.672359 |
module dffe_out (
input wire clk,
input wire d,
input wire e,
output wire q
);
`ifdef FPGA_ICE40
SB_IO #(
.PIN_TYPE(6'b01_01_00),
// | | |
// | | \----- Registered input (and no clock!)
// | \-------- Registered output
// ... | 6.761472 |
module implements a Width bit DFFE
with Write Enable and Reset signals
*/
module dffe_wers #(parameter Width = 32)
(input we, // write enable
input [Width-1:0] din, // data in
output reg [Width-1:0] qout, // data out
i... | 6.904081 |
module top_module (
input clk,
input x,
input y,
output z,
f
);
reg Q1;
reg Q2;
reg Q3;
reg Q4;
reg Q5;
reg Q6;
reg Q7;
reg Q8;
always @(posedge clk) begin
Q1 <= (x ^ Q1);
Q2 <= (x & ~Q2);
Q3 <= (x | ~Q3);
Q4 <= (x | ~Q4);
Q5 <= (y ^ Q5);
Q6 <= (y & Q6);... | 7.203305 |
module dff (
input D,
input clk,
input rst,
output Q
);
SB_DFFR SB_DFFR_inst (
.Q(Q),
.C(clk),
.D(D),
.R(rst)
);
endmodule
| 7.174483 |
module top (
input clk,
rst,
input di,
input hld,
output reg q = 0
);
reg q1 = 0;
always @(posedge clk) begin
if (rst) begin
q <= 0;
q1 <= 0;
end else begin
if (~hld) begin
q <= q1;
q1 <= di;
end
end
end
endmodule
| 7.233807 |
module dffhr (
d,
r,
clk,
q
);
parameter WIDTH = 1;
input r;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk)
if (r) q <= {WIDTH{1'b0}};
else q <= d;
endmodule
| 7.100959 |
module dffl #(
parameter DATA_WIDTH = 16
) (
input wire clk,
input wire en,
input wire [DATA_WIDTH-1 : 0] d,
output wire [DATA_WIDTH-1 : 0] q
);
reg [DATA_WIDTH-1 : 0] q_r;
assign q = q_r;
initial begin
q_r <= 1'b0;
end
always @(posedge clk) begin
if (en == 1'b1) begin
q_... | 7.936209 |
module dffn (
input CLK,
D,
output reg Q,
output QN
);
always @(negedge CLK) Q <= D;
assign QN = ~Q;
endmodule
| 7.496326 |
module dffsr (
input CLK,
D,
CLEAR,
PRESET,
output reg Q,
output QN
);
always @(posedge CLK, posedge CLEAR, posedge PRESET)
if (CLEAR) Q <= 0;
else if (PRESET) Q <= 1;
else Q <= D;
assign QN = ~Q;
endmodule
| 6.804969 |
module dfflop (
input clock,
reset,
d_in,
output Q_out,
Qb_out
);
reg x;
always @(posedge clock) begin
if (reset) x <= 1'b0;
else x <= d_in;
end
assign Q_out = x;
assign Qb_out = !x;
endmodule
| 6.816202 |
module dfflr #(
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) begin : DFFLR_PROC
if (rst_n == 1'b0) qout_r <= {DW{1'b0}};
else if (lden == 1'b1) qout_r ... | 6.936697 |
module dfflrc #(
parameter DATA_WIDTH = 16
) (
input wire clk,
input wire rstn,
input wire en,
input wire [DATA_WIDTH-1 : 0] d,
output wire [DATA_WIDTH-1 : 0] q
);
reg [DATA_WIDTH-1 : 0] q_r;
assign q = q_r;
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) begin
q... | 8.151985 |
module dfflrs #(
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) begin : DFFLRS_PROC
if (rst_n == 1'b0) qout_r <= {DW{1'b1}};
else if (lden == 1'b1) qout_... | 7.088204 |
module DFF (
clk,
in,
out
);
input clk;
input in;
output out;
reg out;
always @(posedge clk) //<--This is the statement that makes the circuit behave with TIME
out = in;
endmodule
| 8.191977 |
module DFFN #(
parameter INIT = 1'b0
) (
input CLK,
input D,
output Q
);
reg _r_Q;
initial begin
_r_Q = INIT;
end
always @(negedge CLK) begin
_r_Q <= D;
end
assign Q = _r_Q;
endmodule
| 6.931354 |
module DFFNC #(
parameter INIT = 1'b0
) (
input CLEAR,
input CLK,
input D,
output Q
);
reg _r_Q;
initial begin
_r_Q = INIT;
end
always @(posedge CLEAR or negedge CLK) begin
if (CLEAR) begin
_r_Q <= 1'b0;
end else begin
_r_Q <= D;
end
end
assign Q = _r_... | 6.557328 |
module DFFNCE #(
parameter INIT = 1'b0
) (
input CLEAR,
input CLK,
input CE,
input D,
output Q
);
reg _r_Q;
initial begin
_r_Q = INIT;
end
always @(posedge CLEAR or negedge CLK) begin
if (CLEAR) begin
_r_Q <= 1'b0;
end else if (CE) begin
_r_Q <= D;
end... | 6.556539 |
module DFFNP #(
parameter INIT = 1'b1
) (
input PRESET,
input CLK,
input D,
output Q
);
reg _r_Q;
initial begin
_r_Q = INIT;
end
always @(posedge PRESET or negedge CLK) begin
if (PRESET) begin
_r_Q <= 1'b1;
end else begin
_r_Q <= D;
end
end
assign Q = ... | 6.528791 |
module DFFNPE #(
parameter INIT = 1'b1
) (
input PRESET,
input CLK,
input CE,
input D,
output Q
);
reg _r_Q;
initial begin
_r_Q = INIT;
end
always @(posedge PRESET or negedge CLK) begin
if (PRESET) begin
_r_Q <= 1'b1;
end else if (CE) begin
_r_Q <= D;
... | 6.645671 |
module DFFP #(
parameter INIT = 1'b1
) (
input PRESET,
input CLK,
input D,
output Q
);
reg _r_Q;
initial begin
_r_Q = INIT;
end
always @(posedge PRESET or posedge CLK) begin
if (PRESET) begin
_r_Q <= 1'b1;
end else begin
_r_Q <= D;
end
end
assign Q = _... | 7.014776 |
module dffram #(
parameter WIDTH = 32,
parameter DEPTH = 256,
// ========================================================================
// Local Parameters - Do Not Edit
// ========================================================================
parameter ADDR_BW = $clog2(DEPTH)
) (
input... | 8.216377 |
module MUX4x1 #(
parameter WIDTH = 32
) (
`ifdef USE_POWER_PINS
input wire VPWR,
input wire VGND,
`endif
input wire [WIDTH-1:0] A0,
A1,
A2,
A3,
input wire [ 1:0] S,
output wire [WIDTH-1:0] X
);
localparam SIZE = WIDTH / 8;
wire [SIZE-1:0] SEL0, SE... | 7.81619 |
module MUX2x1 #(
parameter WIDTH = 32
) (
`ifdef USE_POWER_PINS
input wire VPWR,
input wire VGND,
`endif
input wire [WIDTH-1:0] A0,
A1,
A2,
A3,
input wire S,
output wire [WIDTH-1:0] X
);
localparam SIZE = WIDTH / 8;
wire [SIZE-1:0] SEL;
s... | 8.514928 |
module BYTE #( parameter USE_LATCH=`DFFRAM_USE_LATCH)(
`ifdef USE_POWER_PINS
input wire VPWR,
input wire VGND,
`endif
input wire CLK, // FO: 1
input wire WE, // FO: 1
input wire SEL, // FO: 2
input wire [7:0] Di, // FO: 1
output wire [7:0] Do... | 7.051639 |
module WORD #( parameter USE_LATCH=`DFFRAM_USE_LATCH,
WSIZE=`DFFRAM_WSIZE ) (
`ifdef USE_POWER_PINS
input wire VPWR,
input wire VGND,
`endif
input wire CLK, // FO: 1
input wire [WSIZE-1:0] WE, // FO: 1
input wire SEL, /... | 7.752077 |
module RAM8 #( parameter USE_LATCH=`DFFRAM_USE_LATCH,
WSIZE=`DFFRAM_WSIZE ) (
`ifdef USE_POWER_PINS
input wire VPWR,
input wire VGND,
`endif
input wire CLK, // FO: 1
input wire [WSIZE-1:0] WE, // FO: 1
input EN, /... | 7.426076 |
module RAM32 #( parameter USE_LATCH=`DFFRAM_USE_LATCH,
WSIZE=`DFFRAM_WSIZE )
(
`ifdef USE_POWER_PINS
input wire VPWR,
input wire VGND,
`endif
input wire CLK, // FO: 1
input wire [WSIZE-1:0] WE, // FO: 1
input EN, ... | 7.875466 |
module DFFRAM_1Kx32 #(
parameter USE_LATCH = 0,
WSIZE = 4
) (
`ifdef USE_POWER_PINS
input vccd1,
input vssd1,
`endif
input wire CLK, // FO: 1
input wire [ WSIZE-1:0] WE, // FO: 1
input EN, // FO... | 6.5521 |
module DFFRAM_4K #(
parameter COLS = 4
) (
CLK,
WE,
EN,
Di,
Do,
A
);
input CLK;
input [3:0] WE;
input EN;
input [31:0] Di;
output [31:0] Do;
input [7+$clog2(COLS):0] A;
wire [ 31:0] DOUT [COLS-1:0];
wire [ 31:0] Do_pre;
wire [COLS-1:0] EN_lines;
wire [ 9:... | 6.602964 |
module DFFRAM_beh #(
parameter WSIZE = 4
) (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
CLK,
WE,
EN,
Di,
Do,
A
);
localparam A_WIDTH = 8 + $clog2(WSIZE);
`ifdef USE_POWER_PINS
input wire vccd1;
input wire vssd1;
`endif
input wire CLK;
input wire [3:0] WE;
input wire EN;... | 7.170855 |
module dffram_wrapper #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8,
parameter RAM_DEPTH = 128,
parameter NUM_WMASKS = 4
) (
// input CLK,
// input [( (DATA_WIDTH + 8 - 1) / 8) - 1 : 0]WE,
// input EN,
// input [ADDR_WIDTH - 1 : 0] A,
// input [DATA_WIDTH - 1 : 0]... | 6.983626 |
module DFFRE #(
parameter INIT = 1'b0
) (
input CLK,
input RESET,
input CE,
input D,
output Q
);
reg _r_Q;
initial begin
_r_Q = INIT;
end
always @(posedge CLK) begin
if (RESET) begin
_r_Q <= 1'b0;
end else if (CE) begin
_r_Q <= D;
end
end
assign Q... | 6.537374 |
module RFWORD (
input CLK,
input WE,
input SEL1,
SEL2,
SELW,
output [31:0] D1,
D2,
input [31:0] DW
);
wire [31:0] q_wire;
wire we_wire;
wire [3:0] SEL1_B, SEL2_B;
wire [3:0] GCLK;
sky130_fd_sc_hd__inv_2 INV1[3:0] (
.Y(SEL1_B),
.A(SEL1)
);
sky130_fd_sc_hd__inv_... | 7.358496 |
module RFWORD0 (
input CLK,
input WE,
input SEL1,
SEL2,
SELW,
output [31:0] D1,
D2,
input [31:0] DW
);
wire [31:0] q_wire;
wire we_wire;
wire [3:0] SEL1_B, SEL2_B;
wire [3:0] GCLK;
wire [1:0] lo;
sky130_fd_sc_hd__inv_2 INV1[3:0] (
.Y(SEL1_B),
.A(SEL1)
);
sky... | 6.892105 |
module dffrs #(
parameter DATA_WIDTH = 16
) (
input wire clk,
input wire rstn,
input wire [DATA_WIDTH-1 : 0] d,
output wire [DATA_WIDTH-1 : 0] q
);
reg [DATA_WIDTH-1 : 0] q_r;
assign q = q_r;
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) begin
q_r <= {DATA_WIDTH{1'... | 9.002528 |
module DFFR_11B (
D,
CLK,
RES,
Q,
QN
);
parameter BW = 11;
input signed [BW-1:0] D;
input CLK, RES;
output signed [BW-1:0] QN, Q;
reg signed [BW-1:0] Q;
always @(posedge CLK or posedge RES) begin
if (RES == 1'b1) Q <= 0;
else Q <= D;
end
assign QN = ~Q;
endmodule
| 7.130836 |
module DFFR_21B (
D,
CLK,
RES,
Q,
QN
);
parameter BW = 21;
input signed [BW-1:0] D;
input CLK, RES;
output signed [BW-1:0] QN, Q;
reg signed [BW-1:0] Q;
always @(posedge CLK or posedge RES) begin
if (RES == 1'b1) Q <= 0;
else Q <= D;
end
assign QN = ~Q;
endmodule
| 8.218443 |
module DFFR_6B (
D,
CLK,
RES,
Q,
QN
);
parameter BW = 6;
input signed [BW-1:0] D;
input CLK, RES;
output signed [BW-1:0] QN, Q;
reg signed [BW-1:0] Q;
always @(posedge CLK or posedge RES) begin
if (RES == 1'b1) Q <= 0;
else Q <= D;
end
assign QN = ~Q;
endmodule
| 7.263812 |
module DFFR_6B_3 (
D,
CLK,
RES,
ENABLE,
Q,
QN
);
parameter BW = 6;
input [BW-1:0] D;
input CLK, RES, ENABLE;
output [BW-1:0] QN, Q;
reg [BW-1:0] Q;
always @(posedge CLK or posedge RES) begin
if (RES == 1'b1) begin
Q <= 0;
end else begin
if (ENABLE == 1'b1) begi... | 6.562835 |
module DFFR_6B_4 (
D,
CLK,
RES,
ENABLE,
Q,
QN
);
parameter BW = 6;
input signed [BW-1:0] D;
input CLK, RES, ENABLE;
output signed [BW-1:0] QN, Q;
reg signed [BW-1:0] Q;
always @(posedge CLK or posedge RES) begin
if (RES == 1'b1) begin
Q <= 0;
end else begin
if ... | 6.889901 |
module top_module (
input clk,
input x,
output z
);
wire q1, q2, q3;
xormodule a (
clk,
x,
q1
);
andmodule b (
clk,
x,
q2
);
ormodule c (
clk,
x,
q3
);
assign z = ~(q1 | q2 | q3);
endmodule
| 7.203305 |
module xormodule (
input clk,
input x,
output q
);
wire xorgate;
assign xorgate = x ^ q;
flip_flop f (
clk,
xorgate,
q
);
endmodule
| 6.723772 |
module andmodule (
input clk,
input x,
output q
);
wire andgate;
assign andgate = x & (~q);
flip_flop f (
clk,
andgate,
q
);
endmodule
| 7.151832 |
module ormodule (
input clk,
input x,
output q
);
wire orgate;
assign orgate = x | (~q);
flip_flop f (
clk,
orgate,
q
);
endmodule
| 6.610778 |
module flip_flop (
input clk,
input d,
output q
);
always @(posedge clk) q <= d;
endmodule
| 7.373981 |
module DFFS #(
parameter INIT = 1'b1
) (
input CLK,
input SET,
input D,
output Q
);
reg _r_Q;
initial begin
_r_Q = INIT;
end
always @(posedge CLK) begin
if (SET) begin
_r_Q <= 1'b1;
end else begin
_r_Q <= D;
end
end
assign Q = _r_Q;
endmodule
| 6.875007 |
module T_ff (
q,
clk,
clear
);
// I/O ports
output q;
input clk, clear;
// Instantiate the edge triggered DFF
// Complement of output q is fed back.
// Notice qbar not needed. Empty port.
edge_dff ff1 (
q,
~q,
clk,
clear
);
endmodule
| 6.798952 |
module DFFSR(
input CLK,
input D,
input SETZ,
input RESETZ,
output reg Q
);
always @(posedge CLK or posedge RESETZ or posedge SETZ)
if(RESETZ)
Q <= 0;
else if(SETZ)
Q <= 1;
else
Q <= D;
specify
(posedge CLK *> (Q:D)) = 0;
(posedge SETZ *> (Q:1)) = 0);
(p... | 6.608618 |
module main (
input I0,
input SET,
output D0,
input CLKIN
);
wire inst0_Q;
SB_DFFSS inst0 (
.C(CLKIN),
.S(SET),
.D(I0),
.Q(inst0_Q)
);
assign D0 = inst0_Q;
endmodule
| 7.081372 |
module D_ff_Mem (
input clk,
input reset,
input regWrite,
input decOut1b,
input init,
input d,
output reg q
);
always @(negedge clk) begin
if (reset == 1) q = init;
else if (regWrite == 1 && decOut1b == 1) begin
q = d;
end
end
endmodule
| 6.84774 |
module decoder4to16 (
input [3:0] destReg,
output reg [15:0] decOut
);
always @(destReg)
case (destReg)
4'b0000: decOut = 16'b0000000000000001;
4'b0001: decOut = 16'b0000000000000010;
4'b0010: decOut = 16'b0000000000000100;
4'b0011: decOut = 16'b0000000000001000;
4'b0100: dec... | 8.126959 |
module mux16to1 (
input [31:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [31:0] outBus
);
always@(outR0 or outR1 or outR2 or outR3 or outR4 or... | 7.318793 |
module D_ff (
input clk,
input reset,
input regWrite1,
input decOut1b1,
input regWrite2,
input decOut1b2,
input d1,
input d2,
output reg q
);
always @(posedge clk) begin
if (reset == 1'b1) q = 0;
else if (regWrite1 == 1'b1 && decOut1b1 == 1'b1) begin
q = d1;
end
... | 6.58165 |
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