code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module decoder3to8 (
input [2:0] destReg,
output reg [7:0] decOut
);
always @(destReg) begin
case (destReg)
3'b000: decOut = 8'b00000001;
3'b001: decOut = 8'b00000010;
3'b010: decOut = 8'b00000100;
3'b011: decOut = 8'b00001000;
3'b100: decOut = 8'b00010000;
3'b101: decO... | 8.532605 |
module mux8to1 (
input [31:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
input [2:0] Sel,
output reg [31:0] muxOut
);
always @(Sel or outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7) begin
case (Sel)
3'b000: muxOut = outR0;
3'b0... | 7.465042 |
module registerFile (
input clk,
input reset,
input regWrite1,
input regWrite2,
input [2:0] srcRegA,
input [2:0] srcRegB,
input [2:0] srcRegC,
input [2:0] srcRegD,
input [2:0] writeReg1,
input [2:0] writeReg2,
input [31:0] writeData1,
input [31:0] writeData2,
output [... | 6.674499 |
module D_ff_n (
input clk,
input reset,
input regWrite,
input decOut1b,
input d,
output reg q
);
always @(negedge clk) begin
if (reset == 1'b1) q = 0;
else if (regWrite == 1'b1 && decOut1b == 1'b1) begin
q = d;
end
end
endmodule
| 6.669754 |
module D_ff_n_1 (
input clk,
input reset,
input flush,
input regWrite,
input decOut1b,
input d,
output reg q
);
always @(negedge clk) begin
if (reset == 1'b1 || flush == 1'b1) q = 0;
else if (regWrite == 1'b1 && decOut1b == 1'b1) begin
q = d;
end
end
endmodule
| 6.875726 |
module D_ff_flag (
input clk,
input reset,
input regWrite,
input decOut1b,
input d,
output reg q
);
always @(posedge clk) begin
if (reset == 1'b1) q = 0;
else if (regWrite == 1'b1 && decOut1b == 1'b1) begin
q = d;
end
end
endmodule
| 6.971212 |
module signExt5to32 (
input [4:0] offset,
output reg [31:0] signExtOffset
);
always @(offset) begin
signExtOffset = {{27{offset[4]}}, offset[4:0]};
end
endmodule
| 7.66768 |
module signExt8to32 (
input [7:0] offset,
output reg [31:0] signExtOffset
);
always @(offset) begin
signExtOffset = {{24{offset[7]}}, offset[7:0]};
end
endmodule
| 8.518988 |
module signExt11to32 (
input [10:0] offset,
output reg [31:0] signExtOffset
);
always @(offset) begin
signExtOffset = {{21{offset[10]}}, offset[10:0]};
end
endmodule
| 7.865989 |
module leftshift32_1 (
input [31:0] offset,
output reg [31:0] leftShiftOffset
);
always @(offset) begin
leftShiftOffset = offset << 1;
end
endmodule
| 8.537524 |
module leftshift32_2 (
input [31:0] offset,
output reg [31:0] leftShiftOffset
);
always @(offset) begin
leftShiftOffset = offset << 2;
end
endmodule
| 8.71591 |
module mux2to1_2bit (
input [1:0] in1,
input [1:0] in2,
input sel,
output reg [1:0] muxout
);
always @(in1 or in2 or sel) begin
case (sel)
1'b0: muxout = in1;
1'b1: muxout = in2;
endcase
end
endmodule
| 7.142627 |
module mux4to1_32bit (
input [31:0] in1,
input [31:0] in2,
input [31:0] in3,
input [31:0] in4,
input [1:0] sel,
output reg [31:0] muxout
);
always @(in1 or in2 or in3 or in4 or sel) begin
case (sel)
2'b00: muxout = in1;
2'b01: muxout = in2;
2'b10: muxout = in3;
2'b1... | 7.660658 |
module mux2to1_1bit (
input in1,
input in2,
input sel,
output reg muxout
);
always @(in1 or in2 or sel) begin
case (sel)
1'b0: muxout = in1;
1'b1: muxout = in2;
endcase
end
endmodule
| 6.647989 |
module mux2to1_3bit (
input [2:0] in1,
input [2:0] in2,
input sel,
output reg [2:0] muxout
);
always @(in1 or in2 or sel) begin
case (sel)
1'b0: muxout = in1;
1'b1: muxout = in2;
endcase
end
endmodule
| 7.189762 |
module mux2to1_32bit (
input [31:0] in1,
input [31:0] in2,
input sel,
output reg [31:0] muxout
);
always @(in1 or in2 or sel) begin
case (sel)
1'b0: muxout = in1;
1'b1: muxout = in2;
endcase
end
endmodule
| 7.746454 |
module compareAndSetFlag (
input [31:0] memOut,
input neg_prev,
input zero_prev,
output reg N_Final,
output reg Z_Final
);
always @(memOut or neg_prev or zero_prev) begin
if (memOut < 0) begin
N_Final = 1;
Z_Final = zero_prev;
end else if (memOut == 0) begin
N_Final = neg... | 8.875445 |
module DFFs_tb;
reg clk_i, rst_i;
reg [`TEST_SIZE - 1:0] write_value;
wire [`TEST_SIZE - 1:0] read_value;
integer counter;
always #(`CYCLE_TIME / 2) clk_i = ~clk_i;
DFFs #(
.SIZE(`TEST_SIZE)
) dff4 (
.clk_i (clk_i),
.rst_i (rst_i),
.write_i(write_value),
.read_o (read_va... | 7.20996 |
module dfftb ();
reg din, clk, rst;
wire q;
dff dut (
din,
clk,
rst,
q
);
initial begin
clk = 1;
forever #5 clk = ~clk;
end
initial begin
$dumpfile("dfftb.vcd");
$dumpvars(0, dfftb);
#100 $finish;
end
initial begin
din = 1;
rst = 1;
#10 rst =... | 6.614383 |
module dfftest;
wire q, qn;
reg d, clk;
dff d2 (
.d (d),
.clk(clk),
.q (q),
.qn (qn)
);
initial clk = 1'b0;
always #10 clk = ~clk;
initial begin
#15 d = 1'b1;
#30 d = 1'b0;
#18 d = 1'b1;
#20 d = 1'b0;
#10 $finish;
end
initial begin
$monitor($time, " cl... | 6.795799 |
module is implemented using reg-variables in verilog
*/
`default_nettype none
module DFFusr(
input wire clk,
input wire in,
output reg out
);
always @(negedge clk)
if (in) out <= 1'b1;
else out <= 1'b0;
endmodule
| 6.726025 |
module DFFY (
input clk,
input [63:0] shift_x,
output reg [63:0] shift_x17
);
reg [31:0]
shift_x0,
shift_x1,
shift_x2,
shift_x3,
shift_x4,
shift_x5,
shift_x6,
shift_x7,
shift_x8,
shift_x9,
shift_x10,
shift_x11,
shift_x12,
... | 6.722531 |
module DFF_1 (
clk,
rst,
d,
q
);
input clk, d, rst;
output reg q;
always @(posedge clk) begin
if (rst) q <= 0;
else q <= d;
end
endmodule
| 6.960787 |
module DFF_10Bit (
clk,
d,
q,
reset
);
input [10:1] d;
input clk, reset;
output reg [10:1] q;
initial begin
q <= 10'b0000000000;
end
always @(posedge clk or negedge reset)
if (reset) q <= 10'b0000000000;
else q <= d;
endmodule
| 6.73394 |
module DFF_11Bit (
clk,
d,
q,
reset
);
input [11:1] d;
input clk, reset;
output reg [11:1] q;
initial begin
q <= 11'b00000000000;
end
always @(posedge clk or negedge reset)
if (reset) q <= 11'b00000000000;
else q <= d;
endmodule
| 6.828435 |
module DFF_1bit (
input rst,
input clk,
input load,
input d,
output reg q
);
always @(negedge clk or posedge rst)
if (rst) q <= 0;
else if (load) q <= d;
endmodule
| 8.058397 |
module DFF_2 (
clk,
rst,
d,
q
);
input clk, d, rst;
output reg q;
always @(posedge clk, posedge rst) begin
if (rst) q <= 0;
else q <= d;
end
endmodule
| 6.781836 |
module dff_2out31_0 (
d,
clk,
q,
qb
);
input [31:0] d;
input clk;
output [31:0] q;
output [31:0] qb;
reg [31:0] q;
reg [31:0] qb;
always @(posedge clk) begin
q <= d;
qb <= ~d;
end
endmodule
| 7.536071 |
module DFF_3 (
D,
Clock,
out,
out_bar
);
input [2:0] D;
input Clock;
output [2:0] out;
output [2:0] out_bar;
d_ff DFF1 (
D[0],
Clock,
out[0],
out_bar[0]
);
d_ff DFF2 (
D[1],
Clock,
out[1],
out_bar[1]
);
d_ff DFF3 (
D[2],
Clock... | 7.796993 |
module dff_32 (
D,
clk,
Q
);
input [31:0] D;
input clk;
output reg [31:0] Q;
always @(posedge clk) begin
Q <= D;
end
endmodule
| 7.726678 |
module dff_32_bit (
input clr,
clk,
enable,
input [31:0] D,
output reg [31:0] Q
);
always @(posedge clk or negedge clr) begin
if (clr == 0) Q <= 00000000000000000000000000000000; //32 zeros
else if (enable) Q <= D;
end
endmodule
| 8.597573 |
module DFF_32bits (
input clk,
input Reset,
input [31:0] in,
output reg [31:0] out
);
always @(posedge clk /* or negedge Reset*/) begin
//if(Reset==0) out <= 0;
/*else*/ out <= in;
end
endmodule
| 8.226094 |
module DFF_36Bit (
clk,
d,
q,
reset
);
input [36:1] d;
input clk, reset;
output reg [36:1] q;
initial begin
q <= 36'b000000000000000000000000000000000000;
end
always @(posedge clk or negedge reset)
if (reset) q <= 36'b000000000000000000000000000000000000;
else q <= d;
endmodul... | 7.286663 |
module dff_3_pipe #(
parameter DATA_WIDTH = 8
) (
input clk,
input rst_n,
input [DATA_WIDTH-1:0] d0,
input [DATA_WIDTH-1:0] d1,
input [DATA_WIDTH-1:0] d2,
output reg [DATA_WIDTH-1:0] q0,
output reg [DATA_WIDTH-1:0] q1,
output reg [DATA_WIDTH-1:0] q2
);
always @(posedge clk or neg... | 7.40295 |
module DFF_5Bit (
clk,
d,
q,
reset
);
input [5:1] d;
input clk, reset;
output reg [5:1] q;
initial begin
q <= 5'b00000;
end
always @(posedge clk or negedge reset)
if (reset) q <= 5'b00000;
else q <= d;
endmodule
| 7.113727 |
module dff_ar_en #(
parameter nr_bits = 5
) (
input [nr_bits-1:0] d,
input clk,
input rst,
input en,
output reg [nr_bits-1:0] q
);
always @(posedge clk, negedge rst) begin
if (!rst) q <= {nr_bits{1'b0}};
else if (en) q <= d;
end
endmodule
| 7.340684 |
module dff_asy (
q,
d,
clk,
rst
);
input d, clk, rst;
output reg q;
always @(posedge clk or posedge rst)
if (rst == 1) q <= 0;
else q <= d;
endmodule
| 6.587738 |
module dff_async (
input data_in,
input clk,
input rst_n,
output reg qout
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) qout <= 1'b0;
else qout <= data_in;
end
endmodule
| 7.150072 |
module DFF_AsyncClear (
output reg Q,
input D,
input clk,
input clr
);
// DFF is positive edge-triggered
always @(posedge clk, clr) begin
// if clr becomes 1, immediately clear FF o/p to 0
if (clr) Q <= 1'b0;
else Q <= D;
end
endmodule
| 7.278184 |
module DFF_AsyncClrPre #(
parameter W = 1
) (
input wire clk,
input wire [W-1:0] din,
input wire rst,
output reg [W-1:0] q,
output reg [W-1:0] qn,
input wire [W-1:0] setn,
input wire [W-1:0] clrn,
input wire [W-1:0] cen
);
reg [W-1:0] last_edge;
generate... | 8.553481 |
module dff_asynchronous (
q,
reset,
clock,
data
); // d_flipflop with asynchronous reset
input reset, clock, data;
output q;
reg q;
always @(posedge clock or negedge reset) begin
if (reset == 0) q <= 0;
else q <= data;
end
endmodule
| 6.578919 |
module dff_asynchronous_enable (
q,
reset,
clock,
enable,
data
); // d_flipflop with asynchronous reset
input reset, clock, data, enable;
output q;
reg q;
always @(posedge clock or negedge reset) begin
if (reset == 0) q <= 0;
else if (enable) q <= data;
end
endmodule
| 6.578919 |
module dff_asynchronous_enable_test;
reg reset, clock, data, enable;
output q;
wire q;
dff_asynchronous_enable dffase_1 (
q,
reset,
clock,
enable,
data
);
initial begin
clock = 0;
reset = 0;
enable = 0;
data = 0;
#1 clock = 1;
reset = 0;
enabl... | 6.578919 |
module dff_asynchronous_test;
reg reset, clock, data;
output q;
wire q;
dff_asynchronous dffs_1 (
q,
reset,
clock,
data
);
initial begin
clock = 0;
reset = 0;
data = 0;
#1 clock = 1;
reset = 0;
data = 0;
#1 clock = 0;
reset = 1;
data = 0;
... | 6.578919 |
module dff_asyncres_syncres (
input clk,
input async_reset,
input sync_reset,
input d,
output reg q
);
always @(posedge clk, posedge async_reset) begin
if (async_reset) q <= 1'b0;
else if (sync_reset) q <= 1'b0;
else q <= d;
end
endmodule
| 7.187199 |
module dff_async_clear (
output q,
input d,
input clock,
input clear
);
reg q;
always @(posedge clock or clear) begin
if (clear) q = 0;
else q = d;
end
endmodule
| 7.036976 |
module dff_async_reset (
input clk,
input async_reset,
input d,
output reg q
);
always @(posedge clk, posedge async_reset) begin
if (async_reset) q <= 1'b0;
else q <= d;
end
endmodule
| 7.171044 |
module dff_async_reset_async_preset ();
reg clk, reset, preset, d;
reg q;
always @(posedge clk or posedge reset or posedge preset)
if (reset) begin
q <= 0;
end else if (preset) begin
q <= 1;
end else begin
q <= d;
end
// Testbench code here
initial begin
$monitor("CLK ... | 7.171044 |
module dff_async_reset (
clk,
async_reset,
d,
q
);
wire _0_;
wire _1_;
wire _2_;
input async_reset;
input clk;
input d;
output q;
sky130_fd_sc_hd__clkinv_1 _3_ (
.A(_0_),
.Y(_1_)
);
sky130_fd_sc_hd__dfrtp_1 _4_ (
.CLK(clk),
.D(d),
.Q(q),
.RESET_B(_... | 7.171044 |
module dff_async_rst (
clk,
rst,
d,
q
);
input clk;
input rst;
input d;
output reg q;
always @(posedge clk or negedge rst) begin
if (!rst) q <= 0;
else q <= d;
end
endmodule
| 8.418056 |
module dff_async_rst_n (
input clk,
input rst_n,
input d,
output reg q
);
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0;
else q <= d;
endmodule
| 8.418056 |
module dff_async_rst_n_param #(
parameter WIDTH = 8,
RESET = 8'b0
) (
input clk,
input rst_n,
input [WIDTH - 1 : 0] d,
output reg [WIDTH - 1 : 0] q
);
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= RESET;
else q <= d;
endmodule
... | 8.418056 |
module dff_async_set (
input clk,
input async_set,
input d,
output reg q
);
always @(posedge clk, posedge async_set) begin
if (async_set) q <= 1'b1;
else q <= d;
end
endmodule
| 6.540027 |
module dff_async_set (
clk,
async_set,
d,
q
);
wire _0_;
wire _1_;
wire _2_;
input async_set;
input clk;
input d;
output q;
sky130_fd_sc_hd__clkinv_1 _3_ (
.A(_0_),
.Y(_1_)
);
sky130_fd_sc_hd__dfstp_2 _4_ (
.CLK(clk),
.D(d),
.Q(q),
.SET_B(_2_)
);... | 6.540027 |
module dff_async_tb;
reg d, clk, reset; //register declaration for d, clock and reset
wire q, qb; //wire declaration for q and qbar
dff_async dut (
.i_d (d), //input
.clk (clk), //clock
.reset(reset), //reset
.o_q (q), //output
.o_qb (qb) //output complement
... | 6.886641 |
module dff_asyn_reset_exc (
d,
clk,
q,
qbar,
reset
);
input clk;
input d;
input reset;
output reg q, qbar;
always @(posedge clk or negedge reset) begin
if (!reset) q <= 0;
else begin
q <= d;
qbar <= ~q;
end
end
endmodule
| 7.064872 |
module dff_asyn_reset_exc_tb ();
reg d, clk, reset;
wire q, qbar;
dff_asyn_reset_exc tb (
d,
clk,
q,
qbar,
reset
);
initial begin
clk = 0;
reset = 0;
#20 reset = 1;
end
always #5 clk = ~clk;
initial begin
#10 d = 1;
#10 d = 0;
#10 d = 0;
end... | 7.064872 |
module dff_asyn_rst (
q,
d,
reset,
clk
);
input d, reset, clk;
output q;
reg q;
//posedge triggered D-flip flop with asynchronous reset
always @(posedge clk or posedge reset) begin
if (reset) //if reset=1 (HIGH)
q = 1'b0;
else q = d;
end
endmodule
| 7.240724 |
module dff (
clk,
rst,
d,
q
);
input clk, d, rst;
output reg q;
always @(posedge clk) begin //synchronous reset
if (rst == 1) q <= 0;
else q <= d;
end
endmodule
| 6.824043 |
module for dff written in behavioral style
//with synchronous set and reset.
module dff_behavioral (output reg q,
output wire qbar,
input wire d, set, reset, clk
);
assign qbar= ~q;
always @(posedge clk) begin
if(reset==0) q<= 0; //active low reset
else... | 8.072769 |
module dff_behavioral_tb ();
wire q, qbar;
reg d, set, reset, clk;
dff_behavioral d0 (
q,
qbar,
d,
set,
reset,
clk
);
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
$dumpfile("dff_behavioral_tb.vcd");
$dumpvars(0, dff_behavioral_t... | 6.986965 |
module dff_c (
Q,
Q_BAR,
CLK,
Set,
Reset
); //dff_c stands for dff with Q_BAR connected as the D input
output Q, Q_BAR;
input CLK, Set, Reset; //CLK stands for a general CLK input, specific clock input determined by parent module
wire CLK, Set, Reset;
wire f3, f4, f5, f6; ... | 6.724382 |
module dff_cell #(
parameter DW = 1
) (
clk,
d,
q
);
input clk;
input [DW-1:0] d;
output [DW-1:0] q;
reg [DW-1:0] q;
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.678127 |
module top_DFF_chain_generate
//Clock frequency in unit of MHz
(
input in,
input CLK,
input RST,
output delayed1,
delayed2
);
localparam TAP1 = 5, TAP2 = 7;
//Delay #tap
//Load other module(s)
DFF_chain_generate #(
.TAP(TAP1)
) D1 (
.in(in),
.CLK(CLK),
.RST(RST)... | 7.364514 |
module DFF_chain_generate
//Clock frequency in unit of MHz
(
input in,
input CLK,
input RST,
output delayed
);
parameter TAP = 3;
//Delay #tap
//Load other module(s)
//Definition for Variables in the module
reg [TAP - 1 : 0] D;
//DFF for delay
//Logical
assign delayed = D[TAP-1];
... | 7.336333 |
module dff_clr (
q,
d,
clk,
rst
);
output q;
input d;
input clk;
input rst;
reg state;
assign q = state;
always @(posedge clk or posedge rst) begin
state <= rst ? 1 : d;
end
`ifdef dump_flops
always @(posedge gpu_tb.rst) begin
if ($test$plusargs("dump_flops")) begin
... | 6.856157 |
module dff_col #(
parameter SIZE = 8
) (
input clk,
rst,
wr_en,
start,
input signed [SIZE-1:0] data_in[7:0],
output logic signed [SIZE-1:0] data_out[7:0],
output logic done
);
logic signed [3:0] cnt, n_cnt;
logic signed [SIZE-1:0] next_data_out[7:0];
assign done = (cnt == 4'b0111)... | 8.112895 |
module dff_counter_asyn (
seg_up,
seg_down,
Clk,
resetN
);
input Clk, resetN;
output [7:0] seg_up, seg_down;
wire [3:0] count_up, count_down;
fourBitDFFupCounterWasynClock dff_counter_4bit_up (
count_up,
Clk,
resetN
);
fourBitDFFdownCounterWasynClock dff_counter_4bit_down ... | 7.336102 |
module dff_counter_asyn_tb;
wire [7:0] seg_up, seg_down;
reg Clk, resetN;
dff_counter_asyn dut (
seg_up,
seg_down,
Clk,
resetN
);
initial /*stimulus*/
begin
$dumpfile("Simulation/dff_counter_asyn_tb.vcd");
$dumpvars;
$monitor($time, " Clk=%b, resetN=%b -> seg_up=%7b, se... | 7.336102 |
module dff_counter_sid_top (
seg,
clk,
rst_n
);
input clk, rst_n;
output [7:0] seg;
wire [3:0] sid;
count_sid countSid (
sid,
clk,
rst_n
);
sevenSegmentDisplayDecoder display (
seg,
sid
);
endmodule
| 7.347362 |
module dff_counter_sid_top_tb ();
reg Clk, rst_n;
wire [7:0] seg;
//D.U.T. instantiation
dff_counter_sid_top dff_sid_top (
seg,
Clk,
rst_n
);
//初始化
initial begin
$dumpfile("Simulation/dff_counter_sid_top_tb.vcd");
$dumpvars;
$monitor($time, " out=%7b, <=== clk=%b, rst_n=%b"... | 7.347362 |
module dff_cq (
CLK,
CLR,
D,
Q,
QBAR
);
parameter N = 32;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter d_Q = 1, d_QBAR = 1;
input CLK;
input CLR;
input [(N - 1):0] D;
output [(N - 1):0] Q;
output [(N - 1):0] QBAR;
wire [(N - 1):... | 6.51129 |
module: dffc_dc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module dff_dc_tb;
localparam SIZE = 8;
// Inputs
reg clk;
reg dclk;
reg rst;
reg c_en;
reg d_en;
reg [SIZE-1:0] din... | 8.259546 |
module dff_delay #(
DELAY = 2,
DATA_WIDTH = 1
) (
input wire clk,
input wire rst,
input wire en_i,
input wire [DATA_WIDTH-1:0] data_i,
output reg [DATA_WIDTH-1:0] data_o
);
reg [DATA_WIDTH-1:0] data_reg[DELAY-1:0];
genvar i;
generate... | 7.364515 |
module dff (
clk,
d,
q
);
input clk, d;
output reg q;
always @(posedge clk) q <= d;
endmodule
| 6.824043 |
module dffa (
clk,
arst,
d,
q
);
input clk, arst, d;
output reg q;
always @(posedge clk or posedge arst) begin
if (arst) q <= 1;
else q <= d;
end
endmodule
| 7.730108 |
module dffa1 (
clk,
arst,
d,
q
);
input clk, arst, d;
output reg q;
always @(posedge clk or negedge arst) begin
if (~arst) q <= 0;
else q <= d;
end
endmodule
| 7.246433 |
module dffa2 (
clk,
arst,
d,
q
);
input clk, arst, d;
output reg q;
always @(posedge clk or negedge arst) begin
if (!arst) q <= 0;
else q <= d;
end
endmodule
| 7.517459 |
module dffa3 (
clk,
arst,
d,
q
);
input clk, arst, d;
output reg q;
always @(posedge clk or negedge arst) begin
if (~(!arst)) q <= d;
else q <= 1;
end
endmodule
| 7.076744 |
module dffa4 (
clk,
arst1,
arst2,
arst3,
d,
q
);
input clk, arst1, arst2, arst3, d;
output reg q;
always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
if (arst1) q <= 0;
else if (arst2) q <= 0;
else if (!arst3) q <= 0;
else q <= d;
end
endmodule
| 7.344858 |
module dffsr2 (
clk,
preset,
clear,
d,
q
);
input clk, preset, clear, d;
output q;
(* gentb_clock *)
wire clk, preset, clear, d;
dffsr2_sub uut (
clk,
preset && !clear,
!preset && clear,
d,
q
);
endmodule
| 6.665609 |
module dff_en_fixed_reset_value (
out_value,
in_value,
reset_value,
en,
clk,
rst
);
output [5:0] out_value;
input [5:0] reset_value, in_value;
input en, clk, rst;
wire [5:0] dff_in_value;
assign dff_in_value = rst ? reset_value : in_value;
dff_en ff[5:0] (
out_value,
... | 7.117749 |
module dff_e_cell #(
parameter DW = 1
) (
clk,
en,
d,
q
);
input clk, en;
input [DW-1:0] d;
output [DW-1:0] q;
reg [DW-1:0] q;
always @(posedge clk) begin
if (en) q <= d;
end
endmodule
| 7.154453 |
module dff_e_r0_cell #(
parameter DW = 1
) (
rstz,
clk,
en,
d,
q
);
input rstz, clk, en;
input [DW-1:0] d;
output [DW-1:0] q;
reg [DW-1:0] q;
always @(posedge clk or negedge rstz) begin
if (~rstz) q <= {DW{1'b0}};
else if (en) q <= d;
end
endmodule
| 6.783628 |
module dff_e_r1_cell #(
parameter DW = 1
) (
rstz,
clk,
en,
d,
q
);
input rstz, clk, en;
input [DW-1:0] d;
output [DW-1:0] q;
reg [DW-1:0] q;
always @(posedge clk or negedge rstz) begin
if (~rstz) q <= {DW{1'b1}};
else if (en) q <= d;
end
endmodule
| 6.595 |
module dff_from_nand ();
wire Q, Q_BAR;
reg D, CLK;
nand U1 (X, D, CLK);
nand U2 (Y, X, CLK);
nand U3 (Q, Q_BAR, X);
nand U4 (Q_BAR, Q, Y);
// Testbench of above code
initial begin
$monitor("CLK = %b D = %b Q = %b Q_BAR = %b", CLK, D, Q, Q_BAR);
CLK = 0;
D = 0;
#3 D = 1;
#3 D = 0... | 6.613573 |
module dff_fu (
in,
out,
clk
);
input [9:0] in;
input clk;
output reg [9:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 7.022613 |
module MUX (
IN0,
IN1,
SEL,
F
);
input IN0, IN1, SEL;
output F;
assign F = (~SEL & IN0) | (SEL & IN1);
endmodule
| 7.631171 |
module HADDER (
IN0,
IN1,
SUM,
COUT
);
input IN0, IN1;
output SUM, COUT;
assign SUM = IN0 ^ IN1;
assign COUT = IN0 & IN1;
endmodule
| 8.389834 |
module FADDER (
IN0,
IN1,
CIN,
COUT,
SUM
);
input IN0, IN1, CIN;
output COUT, SUM;
assign SUM = IN0 ^ IN1 ^ CIN;
assign COUT = ((CIN & IN0) | (CIN & IN1) | (IN0 & IN1));
endmodule
| 6.577998 |
module AND (
A,
B,
Z
);
input A, B;
output Z;
assign Z = A & B;
endmodule
| 7.482495 |
module ANDN (
A,
B,
Z
);
input A, B;
output Z;
assign Z = A & ~B;
endmodule
| 8.316656 |
module NAND (
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A & B);
endmodule
| 8.177563 |
module NANDN (
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A & ~B);
endmodule
| 8.189729 |
module OR (
A,
B,
Z
);
input A, B;
output Z;
assign Z = A | B;
endmodule
| 7.211786 |
module ORN (
A,
B,
Z
);
input A, B;
output Z;
assign Z = A | ~B;
endmodule
| 7.794134 |
module NOR (
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A | B);
endmodule
| 8.177256 |
module NORN (
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A | ~B);
endmodule
| 8.462478 |
module XOR (
A,
B,
Z
);
input A, B;
output Z;
assign Z = A ^ B;
endmodule
| 7.868477 |
module XNOR (
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A ^ B);
endmodule
| 7.729097 |
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