code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module IV (
A,
Z
);
input A;
output Z;
assign Z = ~A;
endmodule
| 7.760281 |
module DFF (
CLK,
RST,
D,
I,
Q
);
input CLK, RST, D, I;
output Q;
reg Q;
always @(posedge CLK or posedge RST) begin
if (RST) begin
Q <= I;
end else begin
Q <= D;
end
end
endmodule
| 6.734359 |
module dff_generic(CLK,CLR,D,HOLD,PRE,SCANIN,TEST,Q);
parameter N = 8;
input CLK;
input CLR;
input [(N - 1):0] D;
input HOLD;
input PRE;
input SCANIN;
input TEST;
output [(N - 1):0] Q;
reg [(N - 1):0] Q;
reg [(N - 1):0] temp;
always
@(posedge CLK)
begin
if(((CLR == 1'b0) &&... | 7.557429 |
module dff_hold_sync_high_reset (
clk,
rst,
hold,
D,
Q
);
parameter DATA_WIDTH = 1;
input clk;
input rst;
input hold;
input [DATA_WIDTH-1:0] D;
output [DATA_WIDTH-1:0] Q;
wire clk;
wire rst;
wire hold;
wire [DATA_WIDTH-1:0] D;... | 7.383704 |
module dff0_test (
n1,
n1_inv,
clk
);
input clk;
output n1;
reg n1 = 32'd0;
output n1_inv;
always @(posedge clk) n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
| 6.669977 |
module dff1_test (
n1,
n1_inv,
clk
);
input clk;
(* init = 32'd1 *)
output n1;
reg n1 = 32'd1;
output n1_inv;
always @(posedge clk) n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
| 6.895401 |
module dff0a_test (
n1,
n1_inv,
clk
);
input clk;
(* init = 32'd0 *)
// Must be consistent with reg initialiser below
output n1;
reg n1 = 32'd0;
output n1_inv;
always @(posedge clk) n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
| 7.256393 |
module dff1a_test (
n1,
n1_inv,
clk
);
input clk;
(* init = 32'd1 *)
// Must be consistent with reg initialiser below
output n1;
reg n1 = 32'd1;
output n1_inv;
always @(posedge clk) n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
| 7.138611 |
module dff_inputsel_hold_sync_high_reset (
clk,
rst,
hold,
sel,
D0,
D1,
Q
);
parameter DATA_WIDTH = 1;
input clk;
input rst;
input hold;
input sel;
input [DATA_WIDTH-1:0] D0;
input [DATA_WIDTH-1:0] D1;
output [DATA_WIDTH-1:0] Q;
wire clk;
wire ... | 7.41601 |
module dff_level_convert #(
parameter SIZE = 2
) (
input clk,
rst,
wr_en,
input signed [SIZE-1:0] d,
output logic signed [SIZE-1:0] q
);
/*
genvar i;
generate
for(i =0;i<SIZE;i++)begin
dff_1bit_level_convert d0(.clk(clk),.rst(rst),.wr_en(wr_en),.d(d[i]),.q(q[i]));
end
endgenerate
... | 7.237418 |
module d_ff (
d,
clk,
q
);
parameter WIDTH = 1;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) q <= d;
endmodule
| 7.640793 |
module d_ff_r (
d,
r,
clk,
q
);
parameter WIDTH = 1;
input r;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk)
if (r) q <= {WIDTH{1'b0}};
else q <= d;
endmodule
| 7.515571 |
module d_ff_re (
d,
en,
r,
clk,
q
);
parameter WIDTH = 1;
input en;
input r;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk)
if (r) q <= {WIDTH{1'b0}};
else if (en) q <= d;
else q <= q;
endmodule
| 7.46023 |
module DFF_link_4 (
input CLK,
input RST,
input input_data,
output output_data
);
//Load other module(s)
//Definition for Variables in the module
reg dff[3:0];
//Logical
assign output_data = dff[3];
always @(posedge CLK, negedge RST) begin
if (!RST)
//Reset
begin
dff... | 6.937302 |
module DFF_link_4_combination (
input CLK,
input RST,
input input_data,
output output_data
);
//Load other module(s)
//Definition for Variables in the module
reg dff[3:0];
//Logical
assign output_data = dff[3];
always @(posedge CLK, negedge RST) begin
if (!RST)
//Reset
beg... | 7.112235 |
module DFF_link_4_concatenation (
input CLK,
input RST,
input input_data,
output output_data
);
//Load other module(s)
//Definition for Variables in the module
reg dff[3:0];
//Logical
assign output_data = dff[3];
always @(posedge CLK, negedge RST) begin
if (!RST)
//Reset
b... | 7.112235 |
module DFF_link_4_for (
input CLK,
input RST,
input input_data,
output output_data
);
//Load other module(s)
//Definition for Variables in the module
reg dff[3:0];
integer loop;
//Logical
assign output_data = dff[3];
always @(posedge CLK, negedge RST) begin
if (!RST)
//Reset... | 6.567528 |
module DFF_MS_RST (
input D,
clk,
rst,
output Q,
Q_bar
);
wire D2;
assign D2 = D & ~rst;
DFF_MS CUT (
D2,
clk,
Q,
Q_bar
);
endmodule
| 7.370548 |
module DFF_MS_RST_TB ();
reg DD;
reg cclk = 1'b1;
reg reset = 1'b0;
wire QQ, QQ_bar;
DFF_MS_RST CUT (
DD,
cclk,
reset,
QQ,
QQ_bar
);
always #100 cclk = ~cclk;
initial begin
#150 DD = 1;
#150 DD = 0;
#150 DD = 1;
reset = 1;
#150 DD = 1;
#150 DD = 1... | 7.648663 |
module DFF_MS_TB ();
reg DD;
reg cclk = 1'b1;
wire QQ, QQ_bar;
DFF_MS CUT (
DD,
cclk,
QQ,
QQ_bar
);
always #100 cclk = ~cclk;
initial begin
#150 DD = 1;
#150 DD = 0;
#150 DD = 0;
#150 DD = 1;
#150 $stop;
end
endmodule
| 7.256432 |
module DFF_N #(
parameter N = 3
) (
input clk,
input reset,
input [N-1:0] D,
output reg [N-1:0] Q
);
reg [N-1:0] d0;
reg [N-1:0] d1;
always @(posedge clk or negedge reset)
if (!reset) begin
d0 <= 0; //同步清 0，低电平有效
d1 <= 0; //同步清 0，低电平有效
Q <= 0; //同步清 0，低电平有效
end el... | 8.05977 |
module tb_dff_neg_async ();
reg d, clk, rst;
wire q;
dff_neg_async uut (
.q (q),
.d (d),
.clk(clk),
.rst(rst)
);
// a clock with 100ns 50% duty cycle
initial begin
#00 clk = 1'b0;
forever #50 clk = ~clk;
end
initial begin
#00 rst = 1'b0;
#70 rst = 1'b1;
... | 6.644428 |
module dff_neg_async (
q,
d,
clk,
rst
);
output reg q;
input d, clk, rst;
always @(negedge clk or posedge rst) begin
if (rst) q <= 1'd0;
else q <= d;
end
endmodule
| 6.601465 |
module dff_syncres (
clk,
async_reset,
sync_reset,
d,
q
);
(* src = "dff_syncres.v:3" *)
wire _0_;
wire _1_;
wire _2_;
wire _3_;
wire _4_;
(* src = "dff_syncres.v:2" *)
input async_reset;
(* src = "dff_syncres.v:2" *)
input clk;
(* src = "dff_syncres.v:2" *)
input d;
(* src... | 7.413835 |
module dff (
input dff_clock,
input D,
output reg Q
);
always @(posedge dff_clock) begin
Q <= D;
end
endmodule
| 7.174483 |
module dff_p #(
parameter P_NFF = 1,
parameter P_DEFVAL = 1'b0
) (
////////// inputs //////////
input clk, // clock
input rst_n, // active low reset
input [P_NFF-1:0] a, // input
////////// outputs //////////
output [P_NFF-1:0] y
);
reg [P_NFF-1:0] ff... | 8.651062 |
module dff_pen (
output reg q,
output qbar,
input d,
input en,
input clk
);
always @(posedge clk) begin
if (en) q <= d;
end
assign qn = ~q;
endmodule
| 7.801999 |
module dff_posedge (
d,
clock,
reset,
q
);
input d, clock, reset;
output q;
reg q;
always @(posedge clock or posedge reset) begin
q <= d;
if (reset) q <= 0;
end
endmodule
| 6.878207 |
module dff_pre (
q,
d,
clk,
rst
);
output q;
input d;
input clk;
input rst;
reg state;
assign #(1) q = state;
always @(posedge clk) begin
state = rst ? 1 : d;
end
endmodule
| 7.138296 |
module dff_pre_en (
q,
d,
en,
clk,
rst
);
output q;
input d;
input clk;
input rst;
input en;
reg state;
assign #(1) q = state;
always @(posedge clk) begin
state = rst ? 1 : en ? d : state;
end
endmodule
| 6.6331 |
module DFF_pseudoAsyncClrPre #(
parameter W = 1
) (
input wire clk,
input wire [W-1:0] din,
output wire [W-1:0] q,
output wire [W-1:0] qn,
input wire [W-1:0] set,
input wire [W-1:0] clr,
input wire [W-1:0] cen
);
reg [W-1:0] last_edge;
reg [W-1:0] Q_current;
initial Q... | 7.702041 |
module DFF_pseudoAsyncClrPre2 #(
parameter W = 1
) (
input wire clk,
input wire rst,
input wire [W-1:0] din,
output reg [W-1:0] q,
output reg [W-1:0] qn,
input wire [W-1:0] set, // active high
input wire [W-1:0] clr, // active high
input wire [W-1:0] cen /... | 7.702041 |
module dff_psr_asyn (
output reg q,
qbar,
input d,
clk,
set,
reset
);
always @(posedge clk, posedge reset, posedge set) begin
if (reset) {q, qbar} <= 2'b01;
else if (set) {q, qbar} <= 2'b10;
else {q, qbar} <= {d, ~d};
end
endmodule
| 7.226813 |
module dff_psr_sync (
output reg q,
qbar,
input d,
clk,
reset,
set
);
always @(posedge clk) begin
if (reset) {q, qbar} <= 2'b01;
else if (set) {q, qbar} <= 2'B10;
else {q, qbar} <= {d, ~d};
end
endmodule
| 6.776746 |
module dff_r0_cell #(
parameter DW = 1
) (
rstz,
clk,
d,
q
);
input rstz, clk;
input [DW-1:0] d;
output [DW-1:0] q;
reg [DW-1:0] q;
always @(posedge clk or negedge rstz) begin
if (~rstz) q <= {DW{1'b0}};
else q <= d;
end
endmodule
| 7.131859 |
module dff_r1_cell #(
parameter DW = 1
) (
rstz,
clk,
d,
q
);
input rstz, clk;
input [DW-1:0] d;
output [DW-1:0] q;
reg [DW-1:0] q;
always @(posedge clk or negedge rstz) begin
if (~rstz) q <= {DW{1'b1}};
else q <= d;
end
endmodule
| 6.662906 |
module dff_reset (
D,
Clock,
Resetn,
Q
);
input D, Clock, Resetn;
output Q;
reg Q;
always @(negedge Resetn or posedge Clock)
if (!Resetn) Q <= 0;
else Q <= D;
endmodule
| 7.288092 |
module DFF_RISING (
q,
q_bar,
d,
clk
);
input d, clk;
output q, q_bar;
DFF dff0 (
q0
,,
d,
~clk
);
DFF dff1 (
q,
q_bar,
q0,
clk
);
endmodule
| 7.280498 |
module dff_rst (
clk,
rst,
din,
dout
);
//------------------------------------------------------------------------------
//Parameters
parameter DW = 1'b1;
parameter RST_VL = {DW{1'b0}};
//------------------------------------------------------------------------------
// Port declarations
i... | 8.064534 |
module dff_rstn (
clk,
rst_n,
din,
dout
);
//------------------------------------------------------------------------------
//Parameters
parameter DW = 1'b1;
//------------------------------------------------------------------------------
// Port declarations
input clk;
input rst_n;
inp... | 8.622345 |
module dff_r_2 (
clk,
reset_n,
d,
q
);
input clk, reset_n;
input [1:0] d;
output reg [1:0] q;
always @(posedge clk) begin
if (reset_n == 0) q = 0;
else q = d;
end
endmodule
| 7.055507 |
module dff_s (
d,
q,
clk
);
input d;
input clk;
output reg q;
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.138281 |
module dff_segment_for_cb (
clk,
rst,
hold,
sel,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
Q
);
parameter DATA_WIDTH = 32;
input clk;
input rst;
input hold;
input sel;
input [DATA_WIDTH-1:0] D0;
input [DATA_WIDTH-1:0] D1;
input [DATA_WIDTH-1:0] D2;
i... | 7.230941 |
module dff_segment_for_input (
clk,
rst,
hold,
D,
Q
);
parameter DATA_WIDTH = 32;
input clk;
input rst;
input hold;
input [DATA_WIDTH-1:0] D;
output [DATA_WIDTH-1:0] Q;
wire clk;
wire rst;
wire hold;
wire [DATA_WIDTH-1:0] D;
... | 7.230941 |
module dff_segment_for_output (
clk,
rst,
hold,
sel,
D7,
D1,
Q
);
parameter DATA_WIDTH = 32;
input clk;
input rst;
input hold;
input sel;
input [DATA_WIDTH-1:0] D7;
input [DATA_WIDTH-1:0] D1;
output [DATA_WIDTH-1:0] Q;
wire clk;
wire r... | 7.230941 |
module dff_seq_sync (
d,
clear_,
clock,
q
);
input d, clear_, clock;
output q;
reg q;
always @(posedge clock) begin
if (!clear_) q <= 1'b0;
else q <= d;
end
endmodule
| 6.996507 |
module dff_seq_async (
d,
clear_,
clock,
q
);
input d, clear_, clock;
output q;
reg q;
always @(negedge clear_ or posedge clock) begin
if (!clear_) q <= 1'b0;
else q <= d;
end
endmodule
| 7.252519 |
module dff_set (
q,
d,
clk,
set
);
output q;
input d;
input clk;
input set;
reg state;
assign q = state;
always @(posedge clk) begin
state <= set ? 1 : d;
end
`ifdef dump_flops
always @(posedge gpu_tb.rst) begin
if ($test$plusargs("dump_flops")) begin
$display("%m.st... | 7.22592 |
module dff_set_en (
q,
d,
en,
clk,
set
);
output q;
input d;
input en;
input clk;
input set;
wire d_int, q1;
assign d_int = en ? d : q1;
assign q = q1;
dff_set dff_0 (
.q (q1),
.d (d_int),
.clk(clk),
.set(set)
);
endmodule
| 6.71239 |
module dff_set_en_rst (
d,
q,
en,
clk,
set,
rst
);
output q;
input d;
input en;
input clk;
input set;
input rst;
wire d_int;
reg state;
assign d_int = en ? d : state;
assign q = state;
always @(posedge clk or posedge rst) begin
if (rst) state <= 0;
else state... | 6.603811 |
module dff_single (
d,
q,
clk
);
input [4:0] d;
input clk;
output reg [4:0] q;
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.344817 |
module dff_sr (
aclr,
aset,
clock,
data,
q
);
input aclr;
input aset;
input clock;
input data;
output reg q;
always @(posedge clock or posedge aclr or posedge aset)
if (aclr) q <= 1'b0;
else if (aset) q <= 1'b1;
else q <= data;
endmodule
| 6.823625 |
module dff_sync (
i_d, //input
clk, //clock
reset, //reset
o_q, //output
o_qb //output complement
);
//port declaration
input i_d, clk, reset;
output o_q, o_qb;
reg o_q;
assign o_qb = ~o_q; //assigning qb to be complement of q
always @ (posedge clk) //sensitivity list as pos... | 6.844201 |
module dff_syncres (
input clk,
input async_reset,
input sync_reset,
input d,
output reg q
);
always @(posedge clk) begin
if (sync_reset) q <= 1'b0;
else q <= d;
end
endmodule
| 7.413835 |
module dff_sync_clear (
output q,
input d,
input clear,
input clock
);
reg q;
always @(clock) begin
if (clear) q = 0;
else q = d;
end
endmodule
| 6.679525 |
module dff_sync_reset (
input clk,
input sync_reset,
input d,
output reg q
);
always @(posedge clk) begin
if (sync_reset) q <= 1'b0;
else q <= d;
end
endmodule
| 6.82334 |
module dff_sync_reset (
clk,
sync_reset,
d,
q
);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
wire _4_;
input clk;
input d;
output q;
input sync_reset;
sky130_fd_sc_hd__and2b_2 _5_ (
.A_N(_4_),
.B (_2_),
.X (_3_)
);
sky130_fd_sc_hd__dfxtp_1 _6_ (
.CLK(clk),
... | 6.82334 |
module dff_sync_reset_sync_preset ();
reg clk, reset, preset, d;
reg q;
always @(posedge clk)
if (reset) begin
q <= 0;
end else if (preset) begin
q <= 1;
end else begin
q <= d;
end
// Testbench code here
initial begin
$monitor("CLK = %b RESET = %b PRESET = %b D = %b Q ... | 6.82334 |
module dff_sync_rst_async_clr (
input clk_i, // Input Clock
input rst_i, // Synchronous Reset
input clr_i, // Input Clear
input d_i, // Input D
output reg q_o, // Output Q
output q_n_o // Output ~Q
);
// Combinational Logic
assign q_n_o = ~q_o;
// Seque... | 7.205951 |
module dff_sync_rst_async_clr_tb ();
// Signal Decleration
reg clk_i;
reg rst_i;
reg clr_i;
reg d_i;
wire q_o;
wire q_n_o;
// Instantiation
dff_sync_rst_async_clr dut (
.clk_i(clk_i),
.rst_i(rst_i),
.clr_i(clr_i),
.d_i (d_i),
.q_o (q_o),
.q_n_o(q_n_o)
);
... | 7.205951 |
module dff_sync_rst_n (
input clk,
input rst_n,
input d,
output reg q
);
always @(posedge clk)
if (!rst_n) q <= 0;
else q <= d;
endmodule
| 7.205951 |
module dff_sync_tb;
reg d, clk, reset; //register declaration for d, clock and reset
wire q, qb; //wire declaration for q and qbar
dff_sync dut (
.i_d (d), //input
.clk (clk), //clock
.reset(reset), //reset
.o_q (q), //output
.o_qb (qb) //output complement
... | 6.619116 |
module dff_sync_reset (
d,
clk,
q,
qbar,
reset
);
output reg q, qbar;
input clk, reset;
input d;
always @(posedge clk) begin
if (reset) q <= 0;
else begin
q <= d;
qbar <= ~q;
end
end
endmodule
| 6.82334 |
module dff_sync_reset_tb ();
reg d, clk, reset;
wire q, qbar;
dff_sync_reset tb (
d,
clk,
q,
qbar,
reset
);
always #10 clk = ~clk;
initial begin
clk = 0;
reset = 1;
#10 reset = 0;
end
initial begin
#20 d = 1;
#20 d = 0;
end
endmodule
| 6.82334 |
module d_ff_tb ();
// Step 1. Define a parameter with name "cycle" which is equal to 10
parameter cycle = 10;
reg clk, reset, d;
wire q, qb;
// Step 2. Instantiate the dff design
d_ff DUT (
.clk(clk),
.reset(reset),
.d(d),
.q(q),
.qb(qb)
);
// Step 3. Underst... | 6.785732 |
module DFF_tb2 ();
reg clk, D;
wire Q, Qb;
DFlipFlop DFF (
.clk(clk),
.D (D),
.Q (Q),
.Qb (Qb)
);
initial begin
//Initialize Inputs
clk = 0;
D = 0;
end
always #5 clk = ~clk;
initial begin
#8 D = 1'b1;
#8 D = 1'b0;
#8 D = 1'b1;
#8 D = 1'b0;
... | 6.569264 |
module: dff
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module dff_testbench;
// Inputs
reg clk;
reg d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff uut (
... | 7.23782 |
module dff_udp_tb ();
wire q;
reg d, clock, clear;
dff_udp d0 (
q,
d,
clock,
clear
);
initial begin
clock = 1'b0;
forever #5 clock = ~clock;
end
initial begin
$dumpfile("dff_udp_tb.vcd");
$dumpvars(0, dff_udp_tb);
clear = 1'b1;
#30;
clear = 1'b0;
... | 6.5749 |
module dff_us (
q,
d,
clk,
rst
);
output reg [20:0] q;
input [20:0] d;
input clk, rst;
always @(posedge clk) begin
if (rst) q <= 21'd0;
else q <= d;
end
endmodule
| 7.526248 |
module dff_UsedInS (
clk,
rst,
in,
out
);
input clk, rst, in;
output reg out;
always @(posedge clk, rst) begin
if (rst) out <= 1'b0;
else out <= in;
end
endmodule
| 6.64593 |
module dff_using_mux (
input clk,
input d,
output q
);
wire w;
mux_2_to_1 master (
w,
d,
~clk,
w
);
mux_2_to_1 slave (
q,
w,
clk,
q
);
endmodule
| 6.907832 |
module dff_with_en (
input clk,
input en,
input d,
output reg q
);
always @(posedge clk) if (en) q <= d;
endmodule
| 6.719324 |
module DFG_EG (
input clk,
input rst,
input start,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
input [7:0] e,
output reg [7:0] x_reg,
output reg [7:0] y_reg
);
/*-------------------CP------------------*/
reg [12:0] CV; //Control Vectors
reg [1:0] Src1;
re... | 7.303686 |
module dfifo_16x512 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrusedw
);
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output [8:0] rdusedw;
output [8:0] wrusedw;
wire [ 8:0] sub_wire0;
wire [15:0] sub_wire1;
wire [ ... | 6.815598 |
module dfifo_16x512 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrusedw
);
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output [8:0] rdusedw;
output [8:0] wrusedw;
endmodule
| 6.815598 |
module dfifo_demo #(
parameter DATA_WIDTH = 16,
parameter FIFO_WIDTH = 9,
parameter FIFO_DEPTH = 1024
) (
input wr_clk,
input rd_clk,
input wr_en,
input rd_en,
output reg wr... | 7.883146 |
module DFILT (
input wire SYSRSTn, // system reset
input wire SYSCLK, // system clock
input wire sd_dsd_in, // new direct stream data input
input wire sd_clk_in, // new sigma-delta clock synchronization
input wire [7:0] dfilt_dec_reg, // filter decimation ratio (oversampling ratio)
input... | 6.982203 |
module dflancb (
clk,
reset,
in,
flanc
);
input clk, in, reset;
output flanc;
reg anterior;
always @(posedge clk or posedge reset)
if (reset) anterior <= 0;
else anterior <= in;
assign flanc = anterior && !in;
endmodule
| 7.409948 |
module dflancp (
clk,
reset,
in,
flanc
);
input clk, in, reset;
output flanc;
reg anterior;
always @(posedge clk or posedge reset)
if (reset) anterior <= 0;
else anterior <= in;
assign flanc = !anterior && in;
endmodule
| 7.370574 |
module dflipflop1 (
d,
q,
clk,
reset
);
input d;
input clk, reset;
output reg q;
//reg q;
always @(posedge clk) begin
if (reset == 1'b1) q <= 1'b0;
else q <= d;
end
endmodule
| 7.120155 |
module d_ff (
input wire clock,
input wire D,
input Rst,
output reg Q
);
always @(negedge Rst or posedge clock) begin
if (!Rst) Q = 0;
else Q = D;
end
endmodule
| 6.958195 |
module DFlipFlop_Sync_Clear (
d,
not_clear,
clock,
q
);
input d, not_clear, clock;
output q;
reg q;
always @(posedge clock) begin
if (!not_clear) q <= 1'b0;
else q <= d;
end
endmodule
| 6.533589 |
module DFlipFlop_Async_Clear (
d,
not_clear,
clock,
q
);
input d, not_clear, clock;
output q;
reg q;
always @(negedge not_clear or posedge clock) begin
if (!not_clear) q <= 1'b0;
else q <= d;
end
endmodule
| 6.933649 |
module Testbench_Sync_Clear;
reg d, reset, clock;
wire q;
DFlipFlop_Sync_Clear dff1 (
d,
reset,
clock,
q
);
initial begin
#0 clock = 1'b0;
repeat (10) #5 clock = ~clock;
end
initial begin
$monitor($time, " D = %b, Reset = %b, Clock = %b, Q = %b.", d, reset, clock, q);
... | 6.515571 |
module Testbench_Async_Clear;
reg d, reset, clock;
wire q;
DFlipFlop_Async_Clear dff2 (
d,
reset,
clock,
q
);
initial begin
#0 clock = 1'b0;
repeat (10) #5 clock = ~clock;
end
initial begin
$monitor($time, " D = %b, Reset = %b, Clock = %b, Q = %b.", d, reset, clock, q);... | 6.940518 |
module dflipflop1 (
d,
q,
clk,
reset
);
input [15:0] d;
input clk, reset;
output reg [15:0] q;
//reg q;
always @(posedge clk) begin
if (reset == 1'b1) q <= 16'b0;
else q <= d;
end
endmodule
| 7.120155 |
module dflipflop16 (
d,
q1,
clk,
reset
);
input [15:0] d;
input clk, reset;
output reg [15:0] q1;
always @(posedge clk) begin
if (reset == 1'b1) q1 <= 16'b0;
else q1 <= d;
end
endmodule
| 6.779773 |
module mux16 (
a,
b,
s,
clk,
out
);
input [15:0] a;
input [15:0] b;
input s;
output [15:0] out;
input clk;
wire [15:0] a, b;
reg [15:0] out;
always @(a, b, s) begin
if (s == 0) out = a;
else out = b;
end
endmodule
| 7.126841 |
module dflipflop2 (
d1,
q1,
clk,
reset
);
input [33:0] d1;
input clk, reset;
output reg [33:0] q1;
//reg q1;
always @(posedge clk) begin
if (reset == 1'b1) q1 <= 34'b0;
else q1 <= d1;
end
endmodule
| 6.673436 |
module Dflipflopbp (
clk,
in,
enable,
out
);
parameter DWIDTH = 32;
input clk;
input signed [DWIDTH-1:0] in;
output reg signed [DWIDTH-1:0] out;
input enable;
always @(posedge clk) begin
if (enable == 1) begin
out <= in;
end
end
endmodule
| 7.137871 |
module Dflipflopbp64 (
clk,
in,
enable,
out
);
parameter IWIDTH = 64;
input clk;
input signed [IWIDTH-1:0] in;
output reg signed [IWIDTH-1:0] out;
input enable;
always @(posedge clk) begin
if (enable == 1) begin
out <= in;
end
end
endmodule
| 7.447469 |
module dflipfloplw (
clk,
sel,
D0,
D1,
Q
);
input clk, sel, D0, D1;
output Q;
HDSDFPQ1 SFFInst (
.D (D0),
.SD(D1),
.SE(sel),
.CK(clk),
.Q (Q)
);
endmodule
| 6.555781 |
module D_FF (
c,
r,
d,
q
);
input c, r;
input d;
output reg q;
always @(posedge r or negedge c) begin
if (r) q <= 1'b0;
else q <= d;
end
endmodule
| 7.327167 |
module dFlipFlopNegClkNegRst (
Q,
Qbar,
D,
Clk,
ClrN
);
input D, Clk, ClrN;
output reg Q, Qbar;
always @(negedge Clk or negedge ClrN) begin
if (~ClrN) begin
Q <= 0;
Qbar <= 1;
end else begin
Q <= D;
Qbar <= ~D;
end
end
endmodule
| 7.239689 |
module dFlipFlopPosClkNegRst (
Q,
Qbar,
D,
Clk,
ClrN
);
input D, Clk, ClrN;
output reg Q, Qbar;
always @(posedge Clk or negedge ClrN) begin
if (~ClrN) begin
Q <= 0;
Qbar <= 1;
end else begin
Q <= D;
Qbar <= ~D;
end
end
endmodule
| 7.095348 |
module DFlipFlop (
D,
clk,
en,
async_reset,
Q,
Qb
);
output Q, Qb;
input D, clk, en, async_reset;
assign Q = ~(~(D & clk) & en & ~async_reset);
assign Qb = (~(D & clk) & en & ~async_reset);
endmodule
| 7.170064 |
module DFlipFlop (
D,
clk,
en,
async_reset,
Q,
Qb
);
output Q, Qb;
reg Q, Qb;
input D, clk, en, async_reset;
always @(posedge clk or negedge async_reset) begin
if (en) begin
if (async_reset == 1'b1) begin
Q <= D;
Qb <= ~D;
end else begin
Q <= 1'... | 7.170064 |
module DFlipFlop (
D,
clk,
Q,
Qb
);
output Q, Qb;
input D, clk;
not (X, D);
nand (Y, D, clk);
nand (Z, X, clk);
nand (Q, Y, Qb);
nand (Qb, Z, Q);
endmodule
| 7.170064 |
module DFlipSim;
wire q;
reg data, clk;
initial begin
data = 0;
clk = 0;
end
always #10 clk = ~clk;
always #20 data = ~data;
FlipD my (
q,
data,
clk
);
endmodule
| 6.753024 |
module Dflip_flop (
D,
clk,
r,
s,
Q
);
input D, clk, r, s;
output Q;
wire A_2, A_3, A_4, Q, notQ;
nand #1 A1 (A_1, s, A_4, A_2);
nand #1 A2 (A_2, A_1, r, clk);
nand #1 A3 (A_3, A_2, clk, A_4);
nand #1 A4 (A_4, A_3, r, D);
nand #1 A5 (Q, s, A_2, notQ);
nand #1 A6 (notQ, Q, r, A_3);... | 6.737081 |
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